Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc fixes from Ben Herrenschmidt:
"This series fix a nasty issue with radeon adapters on powerpc servers,
it's all CC'ed stable and has the relevant maintainers ack's/reviews.
Basically, some (radeon) adapters have issues with MSI addresses above
1T (only support 40-bits). We had powerpc specific quirk but it only
listed a specific revision of an adapter that we shipped with our
machines and didn't properly handle the audio function which some
distros enable nowadays.
So we made the quirk generic and fixed both the graphic and audio
drivers properly to use it.
Without that, ppc64 server machines will crash at boot with a radeon
adapter.
Note: This has been brewing for a while, it just needed a last respin
which got delayed due to us moving ozlabs to a new location in town
and other such things taking priority"
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
powerpc/pci: Remove unused force_32bit_msi quirk
powerpc/pseries: Honor the generic "no_64bit_msi" flag
powerpc/powernv: Honor the generic "no_64bit_msi" flag
sound/radeon: Move 64-bit MSI quirk from arch to driver
gpu/radeon: Set flag to indicate broken 64-bit MSI
PCI/MSI: Add device flag indicating that 64-bit MSIs don't work
ALSA: hda - Limit 40bit DMA for AMD HDMI controllers
+60
-22
-2
arch/powerpc/include/asm/pci-bridge.h
-2
arch/powerpc/include/asm/pci-bridge.h
-10
arch/powerpc/kernel/pci_64.c
-10
arch/powerpc/kernel/pci_64.c
···
266
266
}
267
267
EXPORT_SYMBOL(pcibus_to_node);
268
268
#endif
269
-
270
-
static void quirk_radeon_32bit_msi(struct pci_dev *dev)
271
-
{
272
-
struct pci_dn *pdn = pci_get_pdn(dev);
273
-
274
-
if (pdn)
275
-
pdn->force_32bit_msi = true;
276
-
}
277
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon_32bit_msi);
278
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon_32bit_msi);
+1
-2
arch/powerpc/platforms/powernv/pci-ioda.c
+1
-2
arch/powerpc/platforms/powernv/pci-ioda.c
···
1509
1509
unsigned int is_64, struct msi_msg *msg)
1510
1510
{
1511
1511
struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
1512
-
struct pci_dn *pdn = pci_get_pdn(dev);
1513
1512
unsigned int xive_num = hwirq - phb->msi_base;
1514
1513
__be32 data;
1515
1514
int rc;
···
1522
1523
return -ENXIO;
1523
1524
1524
1525
/* Force 32-bit MSI on some broken devices */
1525
-
if (pdn && pdn->force_32bit_msi)
1526
+
if (dev->no_64bit_msi)
1526
1527
is_64 = 0;
1527
1528
1528
1529
/* Assign XIVE to PE */
+1
-2
arch/powerpc/platforms/powernv/pci.c
+1
-2
arch/powerpc/platforms/powernv/pci.c
···
50
50
{
51
51
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
52
52
struct pnv_phb *phb = hose->private_data;
53
-
struct pci_dn *pdn = pci_get_pdn(pdev);
54
53
struct msi_desc *entry;
55
54
struct msi_msg msg;
56
55
int hwirq;
···
59
60
if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
60
61
return -ENODEV;
61
62
62
-
if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
63
+
if (pdev->no_64bit_msi && !phb->msi32_support)
63
64
return -ENODEV;
64
65
65
66
list_for_each_entry(entry, &pdev->msi_list, list) {
+1
-1
arch/powerpc/platforms/pseries/msi.c
+1
-1
arch/powerpc/platforms/pseries/msi.c
+10
drivers/gpu/drm/radeon/radeon_irq_kms.c
+10
drivers/gpu/drm/radeon/radeon_irq_kms.c
···
185
185
if (rdev->flags & RADEON_IS_AGP)
186
186
return false;
187
187
188
+
/*
189
+
* Older chips have a HW limitation, they can only generate 40 bits
190
+
* of address for "64-bit" MSIs which breaks on some platforms, notably
191
+
* IBM POWER servers, so we limit them
192
+
*/
193
+
if (rdev->family < CHIP_BONAIRE) {
194
+
dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
195
+
rdev->pdev->no_64bit_msi = 1;
196
+
}
197
+
188
198
/* force MSI on */
189
199
if (radeon_msi == 1)
190
200
return true;
+26
drivers/pci/msi.c
+26
drivers/pci/msi.c
···
590
590
return entry;
591
591
}
592
592
593
+
static int msi_verify_entries(struct pci_dev *dev)
594
+
{
595
+
struct msi_desc *entry;
596
+
597
+
list_for_each_entry(entry, &dev->msi_list, list) {
598
+
if (!dev->no_64bit_msi || !entry->msg.address_hi)
599
+
continue;
600
+
dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
601
+
" tried to assign one above 4G\n");
602
+
return -EIO;
603
+
}
604
+
return 0;
605
+
}
606
+
593
607
/**
594
608
* msi_capability_init - configure device's MSI capability structure
595
609
* @dev: pointer to the pci_dev data structure of MSI device function
···
635
621
636
622
/* Configure MSI capability structure */
637
623
ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
624
+
if (ret) {
625
+
msi_mask_irq(entry, mask, ~mask);
626
+
free_msi_irqs(dev);
627
+
return ret;
628
+
}
629
+
630
+
ret = msi_verify_entries(dev);
638
631
if (ret) {
639
632
msi_mask_irq(entry, mask, ~mask);
640
633
free_msi_irqs(dev);
···
759
738
ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
760
739
if (ret)
761
740
goto out_avail;
741
+
742
+
/* Check if all MSI entries honor device restrictions */
743
+
ret = msi_verify_entries(dev);
744
+
if (ret)
745
+
goto out_free;
762
746
763
747
/*
764
748
* Some devices require MSI-X to be enabled before we can touch the
+1
include/linux/pci.h
+1
include/linux/pci.h
···
331
331
unsigned int is_added:1;
332
332
unsigned int is_busmaster:1; /* device is busmaster */
333
333
unsigned int no_msi:1; /* device may not use msi */
334
+
unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
334
335
unsigned int block_cfg_access:1; /* config space access is blocked */
335
336
unsigned int broken_parity_status:1; /* Device generates false positive parity */
336
337
unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
+19
-5
sound/pci/hda/hda_intel.c
+19
-5
sound/pci/hda/hda_intel.c
···
298
298
299
299
/* quirks for ATI/AMD HDMI */
300
300
#define AZX_DCAPS_PRESET_ATI_HDMI \
301
-
(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
301
+
(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
302
+
AZX_DCAPS_NO_MSI64)
302
303
303
304
/* quirks for Nvidia */
304
305
#define AZX_DCAPS_PRESET_NVIDIA \
···
1487
1486
struct snd_card *card = chip->card;
1488
1487
int err;
1489
1488
unsigned short gcap;
1489
+
unsigned int dma_bits = 64;
1490
1490
1491
1491
#if BITS_PER_LONG != 64
1492
1492
/* Fix up base address on ULI M5461 */
···
1511
1509
return -ENXIO;
1512
1510
}
1513
1511
1514
-
if (chip->msi)
1512
+
if (chip->msi) {
1513
+
if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1514
+
dev_dbg(card->dev, "Disabling 64bit MSI\n");
1515
+
pci->no_64bit_msi = true;
1516
+
}
1515
1517
if (pci_enable_msi(pci) < 0)
1516
1518
chip->msi = 0;
1519
+
}
1517
1520
1518
1521
if (azx_acquire_irq(chip, 0) < 0)
1519
1522
return -EBUSY;
···
1529
1522
gcap = azx_readw(chip, GCAP);
1530
1523
dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1531
1524
1525
+
/* AMD devices support 40 or 48bit DMA, take the safe one */
1526
+
if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1527
+
dma_bits = 40;
1528
+
1532
1529
/* disable SB600 64bit support for safety */
1533
1530
if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1534
1531
struct pci_dev *p_smbus;
1532
+
dma_bits = 40;
1535
1533
p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1536
1534
PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1537
1535
NULL);
···
1566
1554
}
1567
1555
1568
1556
/* allow 64bit DMA address if supported by H/W */
1569
-
if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
1570
-
pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
1571
-
else {
1557
+
if (!(gcap & AZX_GCAP_64OK))
1558
+
dma_bits = 32;
1559
+
if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1560
+
pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1561
+
} else {
1572
1562
pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1573
1563
pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
1574
1564
}
+1
sound/pci/hda/hda_priv.h
+1
sound/pci/hda/hda_priv.h
···
171
171
#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
172
172
#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
173
173
#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
174
+
#define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */
174
175
175
176
/* HD Audio class code */
176
177
#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403