tjh.dev / kernel
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clk: qcom: gcc-msm8960: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-4-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson d247abe6 861466d4

+48 -48
+48 -48
drivers/clk/qcom/gcc-msm8960.c
··· 349 349 .hw.init = &(struct clk_init_data){ 350 350 .name = "gsbi1_uart_src", 351 351 .parent_names = gcc_pxo_pll8, 352 - .num_parents = 2, 352 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 353 353 .ops = &clk_rcg_ops, 354 354 .flags = CLK_SET_PARENT_GATE, 355 355 }, ··· 400 400 .hw.init = &(struct clk_init_data){ 401 401 .name = "gsbi2_uart_src", 402 402 .parent_names = gcc_pxo_pll8, 403 - .num_parents = 2, 403 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 404 404 .ops = &clk_rcg_ops, 405 405 .flags = CLK_SET_PARENT_GATE, 406 406 }, ··· 451 451 .hw.init = &(struct clk_init_data){ 452 452 .name = "gsbi3_uart_src", 453 453 .parent_names = gcc_pxo_pll8, 454 - .num_parents = 2, 454 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 455 455 .ops = &clk_rcg_ops, 456 456 .flags = CLK_SET_PARENT_GATE, 457 457 }, ··· 502 502 .hw.init = &(struct clk_init_data){ 503 503 .name = "gsbi4_uart_src", 504 504 .parent_names = gcc_pxo_pll8, 505 - .num_parents = 2, 505 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 506 506 .ops = &clk_rcg_ops, 507 507 .flags = CLK_SET_PARENT_GATE, 508 508 }, ··· 553 553 .hw.init = &(struct clk_init_data){ 554 554 .name = "gsbi5_uart_src", 555 555 .parent_names = gcc_pxo_pll8, 556 - .num_parents = 2, 556 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 557 557 .ops = &clk_rcg_ops, 558 558 .flags = CLK_SET_PARENT_GATE, 559 559 }, ··· 604 604 .hw.init = &(struct clk_init_data){ 605 605 .name = "gsbi6_uart_src", 606 606 .parent_names = gcc_pxo_pll8, 607 - .num_parents = 2, 607 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 608 608 .ops = &clk_rcg_ops, 609 609 .flags = CLK_SET_PARENT_GATE, 610 610 }, ··· 655 655 .hw.init = &(struct clk_init_data){ 656 656 .name = "gsbi7_uart_src", 657 657 .parent_names = gcc_pxo_pll8, 658 - .num_parents = 2, 658 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 659 659 .ops = &clk_rcg_ops, 660 660 .flags = CLK_SET_PARENT_GATE, 661 661 }, ··· 706 706 .hw.init = &(struct clk_init_data){ 707 707 .name = "gsbi8_uart_src", 708 708 .parent_names = gcc_pxo_pll8, 709 - .num_parents = 2, 709 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 710 710 .ops = &clk_rcg_ops, 711 711 .flags = CLK_SET_PARENT_GATE, 712 712 }, ··· 755 755 .hw.init = &(struct clk_init_data){ 756 756 .name = "gsbi9_uart_src", 757 757 .parent_names = gcc_pxo_pll8, 758 - .num_parents = 2, 758 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 759 759 .ops = &clk_rcg_ops, 760 760 .flags = CLK_SET_PARENT_GATE, 761 761 }, ··· 804 804 .hw.init = &(struct clk_init_data){ 805 805 .name = "gsbi10_uart_src", 806 806 .parent_names = gcc_pxo_pll8, 807 - .num_parents = 2, 807 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 808 808 .ops = &clk_rcg_ops, 809 809 .flags = CLK_SET_PARENT_GATE, 810 810 }, ··· 853 853 .hw.init = &(struct clk_init_data){ 854 854 .name = "gsbi11_uart_src", 855 855 .parent_names = gcc_pxo_pll8, 856 - .num_parents = 2, 856 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 857 857 .ops = &clk_rcg_ops, 858 858 .flags = CLK_SET_PARENT_GATE, 859 859 }, ··· 902 902 .hw.init = &(struct clk_init_data){ 903 903 .name = "gsbi12_uart_src", 904 904 .parent_names = gcc_pxo_pll8, 905 - .num_parents = 2, 905 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 906 906 .ops = &clk_rcg_ops, 907 907 .flags = CLK_SET_PARENT_GATE, 908 908 }, ··· 964 964 .hw.init = &(struct clk_init_data){ 965 965 .name = "gsbi1_qup_src", 966 966 .parent_names = gcc_pxo_pll8, 967 - .num_parents = 2, 967 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 968 968 .ops = &clk_rcg_ops, 969 969 .flags = CLK_SET_PARENT_GATE, 970 970 }, ··· 1013 1013 .hw.init = &(struct clk_init_data){ 1014 1014 .name = "gsbi2_qup_src", 1015 1015 .parent_names = gcc_pxo_pll8, 1016 - .num_parents = 2, 1016 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1017 1017 .ops = &clk_rcg_ops, 1018 1018 .flags = CLK_SET_PARENT_GATE, 1019 1019 }, ··· 1062 1062 .hw.init = &(struct clk_init_data){ 1063 1063 .name = "gsbi3_qup_src", 1064 1064 .parent_names = gcc_pxo_pll8, 1065 - .num_parents = 2, 1065 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1066 1066 .ops = &clk_rcg_ops, 1067 1067 .flags = CLK_SET_PARENT_GATE, 1068 1068 }, ··· 1111 1111 .hw.init = &(struct clk_init_data){ 1112 1112 .name = "gsbi4_qup_src", 1113 1113 .parent_names = gcc_pxo_pll8, 1114 - .num_parents = 2, 1114 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1115 1115 .ops = &clk_rcg_ops, 1116 1116 .flags = CLK_SET_PARENT_GATE, 1117 1117 }, ··· 1160 1160 .hw.init = &(struct clk_init_data){ 1161 1161 .name = "gsbi5_qup_src", 1162 1162 .parent_names = gcc_pxo_pll8, 1163 - .num_parents = 2, 1163 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1164 1164 .ops = &clk_rcg_ops, 1165 1165 .flags = CLK_SET_PARENT_GATE, 1166 1166 }, ··· 1209 1209 .hw.init = &(struct clk_init_data){ 1210 1210 .name = "gsbi6_qup_src", 1211 1211 .parent_names = gcc_pxo_pll8, 1212 - .num_parents = 2, 1212 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1213 1213 .ops = &clk_rcg_ops, 1214 1214 .flags = CLK_SET_PARENT_GATE, 1215 1215 }, ··· 1258 1258 .hw.init = &(struct clk_init_data){ 1259 1259 .name = "gsbi7_qup_src", 1260 1260 .parent_names = gcc_pxo_pll8, 1261 - .num_parents = 2, 1261 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1262 1262 .ops = &clk_rcg_ops, 1263 1263 .flags = CLK_SET_PARENT_GATE, 1264 1264 }, ··· 1307 1307 .hw.init = &(struct clk_init_data){ 1308 1308 .name = "gsbi8_qup_src", 1309 1309 .parent_names = gcc_pxo_pll8, 1310 - .num_parents = 2, 1310 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1311 1311 .ops = &clk_rcg_ops, 1312 1312 .flags = CLK_SET_PARENT_GATE, 1313 1313 }, ··· 1356 1356 .hw.init = &(struct clk_init_data){ 1357 1357 .name = "gsbi9_qup_src", 1358 1358 .parent_names = gcc_pxo_pll8, 1359 - .num_parents = 2, 1359 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1360 1360 .ops = &clk_rcg_ops, 1361 1361 .flags = CLK_SET_PARENT_GATE, 1362 1362 }, ··· 1405 1405 .hw.init = &(struct clk_init_data){ 1406 1406 .name = "gsbi10_qup_src", 1407 1407 .parent_names = gcc_pxo_pll8, 1408 - .num_parents = 2, 1408 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1409 1409 .ops = &clk_rcg_ops, 1410 1410 .flags = CLK_SET_PARENT_GATE, 1411 1411 }, ··· 1454 1454 .hw.init = &(struct clk_init_data){ 1455 1455 .name = "gsbi11_qup_src", 1456 1456 .parent_names = gcc_pxo_pll8, 1457 - .num_parents = 2, 1457 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1458 1458 .ops = &clk_rcg_ops, 1459 1459 .flags = CLK_SET_PARENT_GATE, 1460 1460 }, ··· 1503 1503 .hw.init = &(struct clk_init_data){ 1504 1504 .name = "gsbi12_qup_src", 1505 1505 .parent_names = gcc_pxo_pll8, 1506 - .num_parents = 2, 1506 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1507 1507 .ops = &clk_rcg_ops, 1508 1508 .flags = CLK_SET_PARENT_GATE, 1509 1509 }, ··· 1565 1565 .hw.init = &(struct clk_init_data){ 1566 1566 .name = "gp0_src", 1567 1567 .parent_names = gcc_pxo_pll8_cxo, 1568 - .num_parents = 3, 1568 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1569 1569 .ops = &clk_rcg_ops, 1570 1570 .flags = CLK_SET_PARENT_GATE, 1571 1571 }, ··· 1614 1614 .hw.init = &(struct clk_init_data){ 1615 1615 .name = "gp1_src", 1616 1616 .parent_names = gcc_pxo_pll8_cxo, 1617 - .num_parents = 3, 1617 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1618 1618 .ops = &clk_rcg_ops, 1619 1619 .flags = CLK_SET_RATE_GATE, 1620 1620 }, ··· 1663 1663 .hw.init = &(struct clk_init_data){ 1664 1664 .name = "gp2_src", 1665 1665 .parent_names = gcc_pxo_pll8_cxo, 1666 - .num_parents = 3, 1666 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1667 1667 .ops = &clk_rcg_ops, 1668 1668 .flags = CLK_SET_RATE_GATE, 1669 1669 }, ··· 1715 1715 .hw.init = &(struct clk_init_data){ 1716 1716 .name = "prng_src", 1717 1717 .parent_names = gcc_pxo_pll8, 1718 - .num_parents = 2, 1718 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1719 1719 .ops = &clk_rcg_ops, 1720 1720 }, 1721 1721 }, ··· 1777 1777 .hw.init = &(struct clk_init_data){ 1778 1778 .name = "sdc1_src", 1779 1779 .parent_names = gcc_pxo_pll8, 1780 - .num_parents = 2, 1780 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1781 1781 .ops = &clk_rcg_ops, 1782 1782 }, 1783 1783 } ··· 1825 1825 .hw.init = &(struct clk_init_data){ 1826 1826 .name = "sdc2_src", 1827 1827 .parent_names = gcc_pxo_pll8, 1828 - .num_parents = 2, 1828 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1829 1829 .ops = &clk_rcg_ops, 1830 1830 }, 1831 1831 } ··· 1873 1873 .hw.init = &(struct clk_init_data){ 1874 1874 .name = "sdc3_src", 1875 1875 .parent_names = gcc_pxo_pll8, 1876 - .num_parents = 2, 1876 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1877 1877 .ops = &clk_rcg_ops, 1878 1878 }, 1879 1879 } ··· 1921 1921 .hw.init = &(struct clk_init_data){ 1922 1922 .name = "sdc4_src", 1923 1923 .parent_names = gcc_pxo_pll8, 1924 - .num_parents = 2, 1924 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1925 1925 .ops = &clk_rcg_ops, 1926 1926 }, 1927 1927 } ··· 1969 1969 .hw.init = &(struct clk_init_data){ 1970 1970 .name = "sdc5_src", 1971 1971 .parent_names = gcc_pxo_pll8, 1972 - .num_parents = 2, 1972 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1973 1973 .ops = &clk_rcg_ops, 1974 1974 }, 1975 1975 } ··· 2022 2022 .hw.init = &(struct clk_init_data){ 2023 2023 .name = "tsif_ref_src", 2024 2024 .parent_names = gcc_pxo_pll8, 2025 - .num_parents = 2, 2025 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2026 2026 .ops = &clk_rcg_ops, 2027 2027 .flags = CLK_SET_RATE_GATE, 2028 2028 }, ··· 2076 2076 .hw.init = &(struct clk_init_data){ 2077 2077 .name = "usb_hs1_xcvr_src", 2078 2078 .parent_names = gcc_pxo_pll8, 2079 - .num_parents = 2, 2079 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2080 2080 .ops = &clk_rcg_ops, 2081 2081 .flags = CLK_SET_RATE_GATE, 2082 2082 }, ··· 2125 2125 .hw.init = &(struct clk_init_data){ 2126 2126 .name = "usb_hs3_xcvr_src", 2127 2127 .parent_names = gcc_pxo_pll8, 2128 - .num_parents = 2, 2128 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2129 2129 .ops = &clk_rcg_ops, 2130 2130 .flags = CLK_SET_RATE_GATE, 2131 2131 }, ··· 2174 2174 .hw.init = &(struct clk_init_data){ 2175 2175 .name = "usb_hs4_xcvr_src", 2176 2176 .parent_names = gcc_pxo_pll8, 2177 - .num_parents = 2, 2177 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2178 2178 .ops = &clk_rcg_ops, 2179 2179 .flags = CLK_SET_RATE_GATE, 2180 2180 }, ··· 2223 2223 .hw.init = &(struct clk_init_data){ 2224 2224 .name = "usb_hsic_xcvr_fs_src", 2225 2225 .parent_names = gcc_pxo_pll8, 2226 - .num_parents = 2, 2226 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2227 2227 .ops = &clk_rcg_ops, 2228 2228 .flags = CLK_SET_RATE_GATE, 2229 2229 }, ··· 2241 2241 .hw.init = &(struct clk_init_data){ 2242 2242 .name = "usb_hsic_xcvr_fs_clk", 2243 2243 .parent_names = usb_hsic_xcvr_fs_src_p, 2244 - .num_parents = 1, 2244 + .num_parents = ARRAY_SIZE(usb_hsic_xcvr_fs_src_p), 2245 2245 .ops = &clk_branch_ops, 2246 2246 .flags = CLK_SET_RATE_PARENT, 2247 2247 }, ··· 2256 2256 .enable_mask = BIT(4), 2257 2257 .hw.init = &(struct clk_init_data){ 2258 2258 .parent_names = usb_hsic_xcvr_fs_src_p, 2259 - .num_parents = 1, 2259 + .num_parents = ARRAY_SIZE(usb_hsic_xcvr_fs_src_p), 2260 2260 .name = "usb_hsic_system_clk", 2261 2261 .ops = &clk_branch_ops, 2262 2262 .flags = CLK_SET_RATE_PARENT, ··· 2318 2318 .hw.init = &(struct clk_init_data){ 2319 2319 .name = "usb_fs1_xcvr_fs_src", 2320 2320 .parent_names = gcc_pxo_pll8, 2321 - .num_parents = 2, 2321 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2322 2322 .ops = &clk_rcg_ops, 2323 2323 .flags = CLK_SET_RATE_GATE, 2324 2324 }, ··· 2336 2336 .hw.init = &(struct clk_init_data){ 2337 2337 .name = "usb_fs1_xcvr_fs_clk", 2338 2338 .parent_names = usb_fs1_xcvr_fs_src_p, 2339 - .num_parents = 1, 2339 + .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), 2340 2340 .ops = &clk_branch_ops, 2341 2341 .flags = CLK_SET_RATE_PARENT, 2342 2342 }, ··· 2351 2351 .enable_mask = BIT(4), 2352 2352 .hw.init = &(struct clk_init_data){ 2353 2353 .parent_names = usb_fs1_xcvr_fs_src_p, 2354 - .num_parents = 1, 2354 + .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), 2355 2355 .name = "usb_fs1_system_clk", 2356 2356 .ops = &clk_branch_ops, 2357 2357 .flags = CLK_SET_RATE_PARENT, ··· 2385 2385 .hw.init = &(struct clk_init_data){ 2386 2386 .name = "usb_fs2_xcvr_fs_src", 2387 2387 .parent_names = gcc_pxo_pll8, 2388 - .num_parents = 2, 2388 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2389 2389 .ops = &clk_rcg_ops, 2390 2390 .flags = CLK_SET_RATE_GATE, 2391 2391 }, ··· 2403 2403 .hw.init = &(struct clk_init_data){ 2404 2404 .name = "usb_fs2_xcvr_fs_clk", 2405 2405 .parent_names = usb_fs2_xcvr_fs_src_p, 2406 - .num_parents = 1, 2406 + .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), 2407 2407 .ops = &clk_branch_ops, 2408 2408 .flags = CLK_SET_RATE_PARENT, 2409 2409 }, ··· 2419 2419 .hw.init = &(struct clk_init_data){ 2420 2420 .name = "usb_fs2_system_clk", 2421 2421 .parent_names = usb_fs2_xcvr_fs_src_p, 2422 - .num_parents = 1, 2422 + .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), 2423 2423 .ops = &clk_branch_ops, 2424 2424 .flags = CLK_SET_RATE_PARENT, 2425 2425 }, ··· 2873 2873 .hw.init = &(struct clk_init_data){ 2874 2874 .name = "ce3_src", 2875 2875 .parent_names = gcc_pxo_pll8_pll3, 2876 - .num_parents = 3, 2876 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3), 2877 2877 .ops = &clk_rcg_ops, 2878 2878 .flags = CLK_SET_RATE_GATE, 2879 2879 }, ··· 2935 2935 .hw.init = &(struct clk_init_data){ 2936 2936 .name = "sata_clk_src", 2937 2937 .parent_names = gcc_pxo_pll8_pll3, 2938 - .num_parents = 3, 2938 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3), 2939 2939 .ops = &clk_rcg_ops, 2940 2940 .flags = CLK_SET_RATE_GATE, 2941 2941 },