Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-fix-v6.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"We've got more fixes here for the Cadence QSPI controller, this time
fixing some issues that come up when working with slower flashes on
some platforms plus a general race condition.
We also add support for the Allwinner A523, this is just some new
compatibles"
* tag 'spi-fix-v6.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: cadence-quadspi: Improve CQSPI_SLOW_SRAM quirk if flash is slow
spi: cadence-quadspi: Prevent lost complete() call during indirect read
spi: sun6i: Support A523's SPI controllers
spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers
+22
-16
+4
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
+4
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
···
17
17
compatible:
18
18
oneOf:
19
19
- const: allwinner,sun50i-r329-spi
20
+
- const: allwinner,sun55i-a523-spi
20
21
- const: allwinner,sun6i-a31-spi
21
22
- const: allwinner,sun8i-h3-spi
22
23
- items:
···
36
35
- const: allwinner,sun20i-d1-spi-dbi
37
36
- const: allwinner,sun50i-r329-spi-dbi
38
37
- const: allwinner,sun50i-r329-spi
38
+
- items:
39
+
- const: allwinner,sun55i-a523-spi-dbi
40
+
- const: allwinner,sun55i-a523-spi
39
41
40
42
reg:
41
43
maxItems: 1
+11
-12
drivers/spi/spi-cadence-quadspi.c
+11
-12
drivers/spi/spi-cadence-quadspi.c
···
300
300
CQSPI_REG_IRQ_IND_SRAM_FULL | \
301
301
CQSPI_REG_IRQ_IND_COMP)
302
302
303
+
#define CQSPI_IRQ_MASK_RD_SLOW_SRAM (CQSPI_REG_IRQ_WATERMARK | \
304
+
CQSPI_REG_IRQ_IND_COMP)
305
+
303
306
#define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
304
307
CQSPI_REG_IRQ_WATERMARK | \
305
308
CQSPI_REG_IRQ_UNDERFLOW)
···
384
381
else if (!cqspi->slow_sram)
385
382
irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
386
383
else
387
-
irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR;
384
+
irq_status &= CQSPI_IRQ_MASK_RD_SLOW_SRAM | CQSPI_IRQ_MASK_WR;
388
385
389
386
if (irq_status)
390
387
complete(&cqspi->transfer_complete);
···
760
757
*/
761
758
762
759
if (use_irq && cqspi->slow_sram)
763
-
writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
760
+
writel(CQSPI_IRQ_MASK_RD_SLOW_SRAM, reg_base + CQSPI_REG_IRQMASK);
764
761
else if (use_irq)
765
762
writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
766
763
else
···
772
769
readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */
773
770
774
771
while (remaining > 0) {
772
+
ret = 0;
775
773
if (use_irq &&
776
774
!wait_for_completion_timeout(&cqspi->transfer_complete,
777
775
msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
778
776
ret = -ETIMEDOUT;
779
777
780
778
/*
781
-
* Disable all read interrupts until
782
-
* we are out of "bytes to read"
779
+
* Prevent lost interrupt and race condition by reinitializing early.
780
+
* A spurious wakeup and another wait cycle can occur here,
781
+
* which is preferable to waiting until timeout if interrupt is lost.
783
782
*/
784
-
if (cqspi->slow_sram)
785
-
writel(0x0, reg_base + CQSPI_REG_IRQMASK);
783
+
if (use_irq)
784
+
reinit_completion(&cqspi->transfer_complete);
786
785
787
786
bytes_to_read = cqspi_get_rd_sram_level(cqspi);
788
787
···
815
810
rxbuf += bytes_to_read;
816
811
remaining -= bytes_to_read;
817
812
bytes_to_read = cqspi_get_rd_sram_level(cqspi);
818
-
}
819
-
820
-
if (use_irq && remaining > 0) {
821
-
reinit_completion(&cqspi->transfer_complete);
822
-
if (cqspi->slow_sram)
823
-
writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
824
813
}
825
814
}
826
815
+7
-4
drivers/spi/spi-sun6i.c
+7
-4
drivers/spi/spi-sun6i.c
···
795
795
static const struct of_device_id sun6i_spi_match[] = {
796
796
{ .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg },
797
797
{ .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg },
798
-
{
799
-
.compatible = "allwinner,sun50i-r329-spi",
800
-
.data = &sun50i_r329_spi_cfg
801
-
},
798
+
{ .compatible = "allwinner,sun50i-r329-spi", .data = &sun50i_r329_spi_cfg },
799
+
/*
800
+
* A523's SPI controller has a combined RX buffer + FIFO counter
801
+
* at offset 0x400, instead of split buffer count in FIFO status
802
+
* register. But in practice we only care about the FIFO level.
803
+
*/
804
+
{ .compatible = "allwinner,sun55i-a523-spi", .data = &sun50i_r329_spi_cfg },
802
805
{}
803
806
};
804
807
MODULE_DEVICE_TABLE(of, sun6i_spi_match);