Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'staging-5.10-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging and IIO fixes from Greg KH:
"Here are some small Staging and IIO driver fixes for 5.10-rc5. They
include:
- IIO fixes for reported regressions and problems
- new device ids for IIO drivers
- new device id for rtl8723bs driver
- staging ralink driver Kconfig dependency fix
- staging mt7621-pci bus resource fix
All of these have been in linux-next all week with no reported issues"
* tag 'staging-5.10-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
iio: accel: kxcjk1013: Add support for KIOX010A ACPI DSM for setting tablet-mode
iio: accel: kxcjk1013: Replace is_smo8500_device with an acpi_type enum
docs: ABI: testing: iio: stm32: remove re-introduced unsupported ABI
iio: light: fix kconfig dependency bug for VCNL4035
iio/adc: ingenic: Fix AUX/VBAT readings when touchscreen is used
iio/adc: ingenic: Fix battery VREF for JZ4770 SoC
staging: rtl8723bs: Add 024c:0627 to the list of SDIO device-ids
staging: ralink-gdma: fix kconfig dependency bug for DMA_RALINK
staging: mt7621-pci: avoid to request pci bus resources
iio: imu: st_lsm6dsx: set 10ms as min shub slave timeout
counter/ti-eqep: Fix regmap max_register
iio: adc: stm32-adc: fix a regression when using dma and irq
iio: adc: mediatek: fix unset field
iio: cros_ec: Use default frequencies when EC returns invalid information
+165
-85
-24
Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
-24
Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
···
109
109
When counting down the counter start from preset value
110
110
and fire event when reach 0.
111
111
112
-
What: /sys/bus/iio/devices/iio:deviceX/in_count_quadrature_mode_available
113
-
KernelVersion: 4.12
114
-
Contact: benjamin.gaignard@st.com
115
-
Description:
116
-
Reading returns the list possible quadrature modes.
117
-
118
-
What: /sys/bus/iio/devices/iio:deviceX/in_count0_quadrature_mode
119
-
KernelVersion: 4.12
120
-
Contact: benjamin.gaignard@st.com
121
-
Description:
122
-
Configure the device counter quadrature modes:
123
-
124
-
channel_A:
125
-
Encoder A input servers as the count input and B as
126
-
the UP/DOWN direction control input.
127
-
128
-
channel_B:
129
-
Encoder B input serves as the count input and A as
130
-
the UP/DOWN direction control input.
131
-
132
-
quadrature:
133
-
Encoder A and B inputs are mixed to get direction
134
-
and count with a scale of 0.25.
135
-
136
112
What: /sys/bus/iio/devices/iio:deviceX/in_count_enable_mode_available
137
113
KernelVersion: 4.12
138
114
Contact: benjamin.gaignard@st.com
+2
-2
drivers/counter/ti-eqep.c
+2
-2
drivers/counter/ti-eqep.c
···
368
368
.reg_bits = 32,
369
369
.val_bits = 32,
370
370
.reg_stride = 4,
371
-
.max_register = 0x24,
371
+
.max_register = QUPRD,
372
372
};
373
373
374
374
static const struct regmap_config ti_eqep_regmap16_config = {
···
376
376
.reg_bits = 16,
377
377
.val_bits = 16,
378
378
.reg_stride = 2,
379
-
.max_register = 0x1e,
379
+
.max_register = QCPRDLAT,
380
380
};
381
381
382
382
static int ti_eqep_probe(struct platform_device *pdev)
+46
-5
drivers/iio/accel/kxcjk-1013.c
+46
-5
drivers/iio/accel/kxcjk-1013.c
···
126
126
KX_MAX_CHIPS /* this must be last */
127
127
};
128
128
129
+
enum kx_acpi_type {
130
+
ACPI_GENERIC,
131
+
ACPI_SMO8500,
132
+
ACPI_KIOX010A,
133
+
};
134
+
129
135
struct kxcjk1013_data {
130
136
struct i2c_client *client;
131
137
struct iio_trigger *dready_trig;
···
149
143
bool motion_trigger_on;
150
144
int64_t timestamp;
151
145
enum kx_chipset chipset;
152
-
bool is_smo8500_device;
146
+
enum kx_acpi_type acpi_type;
153
147
};
154
148
155
149
enum kxcjk1013_axis {
···
276
270
{19163, 1, 0},
277
271
{38326, 0, 1} };
278
272
273
+
#ifdef CONFIG_ACPI
274
+
enum kiox010a_fn_index {
275
+
KIOX010A_SET_LAPTOP_MODE = 1,
276
+
KIOX010A_SET_TABLET_MODE = 2,
277
+
};
278
+
279
+
static int kiox010a_dsm(struct device *dev, int fn_index)
280
+
{
281
+
acpi_handle handle = ACPI_HANDLE(dev);
282
+
guid_t kiox010a_dsm_guid;
283
+
union acpi_object *obj;
284
+
285
+
if (!handle)
286
+
return -ENODEV;
287
+
288
+
guid_parse("1f339696-d475-4e26-8cad-2e9f8e6d7a91", &kiox010a_dsm_guid);
289
+
290
+
obj = acpi_evaluate_dsm(handle, &kiox010a_dsm_guid, 1, fn_index, NULL);
291
+
if (!obj)
292
+
return -EIO;
293
+
294
+
ACPI_FREE(obj);
295
+
return 0;
296
+
}
297
+
#endif
298
+
279
299
static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
280
300
enum kxcjk1013_mode mode)
281
301
{
···
378
346
static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
379
347
{
380
348
int ret;
349
+
350
+
#ifdef CONFIG_ACPI
351
+
if (data->acpi_type == ACPI_KIOX010A) {
352
+
/* Make sure the kbd and touchpad on 2-in-1s using 2 KXCJ91008-s work */
353
+
kiox010a_dsm(&data->client->dev, KIOX010A_SET_LAPTOP_MODE);
354
+
}
355
+
#endif
381
356
382
357
ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);
383
358
if (ret < 0) {
···
1286
1247
1287
1248
static const char *kxcjk1013_match_acpi_device(struct device *dev,
1288
1249
enum kx_chipset *chipset,
1289
-
bool *is_smo8500_device)
1250
+
enum kx_acpi_type *acpi_type)
1290
1251
{
1291
1252
const struct acpi_device_id *id;
1292
1253
···
1295
1256
return NULL;
1296
1257
1297
1258
if (strcmp(id->id, "SMO8500") == 0)
1298
-
*is_smo8500_device = true;
1259
+
*acpi_type = ACPI_SMO8500;
1260
+
else if (strcmp(id->id, "KIOX010A") == 0)
1261
+
*acpi_type = ACPI_KIOX010A;
1299
1262
1300
1263
*chipset = (enum kx_chipset)id->driver_data;
1301
1264
···
1340
1299
} else if (ACPI_HANDLE(&client->dev)) {
1341
1300
name = kxcjk1013_match_acpi_device(&client->dev,
1342
1301
&data->chipset,
1343
-
&data->is_smo8500_device);
1302
+
&data->acpi_type);
1344
1303
} else
1345
1304
return -ENODEV;
1346
1305
···
1357
1316
indio_dev->modes = INDIO_DIRECT_MODE;
1358
1317
indio_dev->info = &kxcjk1013_info;
1359
1318
1360
-
if (client->irq > 0 && !data->is_smo8500_device) {
1319
+
if (client->irq > 0 && data->acpi_type != ACPI_SMO8500) {
1361
1320
ret = devm_request_threaded_irq(&client->dev, client->irq,
1362
1321
kxcjk1013_data_rdy_trig_poll,
1363
1322
kxcjk1013_event_handler,
+27
-7
drivers/iio/adc/ingenic-adc.c
+27
-7
drivers/iio/adc/ingenic-adc.c
···
71
71
#define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
72
72
#define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
73
73
#define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
74
-
#define JZ4770_ADC_BATTERY_VREF 6600
74
+
#define JZ4770_ADC_BATTERY_VREF 1200
75
75
#define JZ4770_ADC_BATTERY_VREF_BITS 12
76
76
77
77
#define JZ_ADC_IRQ_AUX BIT(0)
···
177
177
mutex_unlock(&adc->lock);
178
178
}
179
179
180
-
static void ingenic_adc_enable(struct ingenic_adc *adc,
181
-
int engine,
182
-
bool enabled)
180
+
static void ingenic_adc_enable_unlocked(struct ingenic_adc *adc,
181
+
int engine,
182
+
bool enabled)
183
183
{
184
184
u8 val;
185
185
186
-
mutex_lock(&adc->lock);
187
186
val = readb(adc->base + JZ_ADC_REG_ENABLE);
188
187
189
188
if (enabled)
···
191
192
val &= ~BIT(engine);
192
193
193
194
writeb(val, adc->base + JZ_ADC_REG_ENABLE);
195
+
}
196
+
197
+
static void ingenic_adc_enable(struct ingenic_adc *adc,
198
+
int engine,
199
+
bool enabled)
200
+
{
201
+
mutex_lock(&adc->lock);
202
+
ingenic_adc_enable_unlocked(adc, engine, enabled);
194
203
mutex_unlock(&adc->lock);
195
204
}
196
205
197
206
static int ingenic_adc_capture(struct ingenic_adc *adc,
198
207
int engine)
199
208
{
209
+
u32 cfg;
200
210
u8 val;
201
211
int ret;
202
212
203
-
ingenic_adc_enable(adc, engine, true);
213
+
/*
214
+
* Disable CMD_SEL temporarily, because it causes wrong VBAT readings,
215
+
* probably due to the switch of VREF. We must keep the lock here to
216
+
* avoid races with the buffer enable/disable functions.
217
+
*/
218
+
mutex_lock(&adc->lock);
219
+
cfg = readl(adc->base + JZ_ADC_REG_CFG);
220
+
writel(cfg & ~JZ_ADC_REG_CFG_CMD_SEL, adc->base + JZ_ADC_REG_CFG);
221
+
222
+
ingenic_adc_enable_unlocked(adc, engine, true);
204
223
ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
205
224
!(val & BIT(engine)), 250, 1000);
206
225
if (ret)
207
-
ingenic_adc_enable(adc, engine, false);
226
+
ingenic_adc_enable_unlocked(adc, engine, false);
227
+
228
+
writel(cfg, adc->base + JZ_ADC_REG_CFG);
229
+
mutex_unlock(&adc->lock);
208
230
209
231
return ret;
210
232
}
+4
-2
drivers/iio/adc/mt6577_auxadc.c
+4
-2
drivers/iio/adc/mt6577_auxadc.c
···
9
9
#include <linux/err.h>
10
10
#include <linux/kernel.h>
11
11
#include <linux/module.h>
12
-
#include <linux/of.h>
13
-
#include <linux/of_device.h>
12
+
#include <linux/mod_devicetable.h>
14
13
#include <linux/platform_device.h>
14
+
#include <linux/property.h>
15
15
#include <linux/iopoll.h>
16
16
#include <linux/io.h>
17
17
#include <linux/iio/iio.h>
···
275
275
dev_err(&pdev->dev, "null clock rate\n");
276
276
goto err_disable_clk;
277
277
}
278
+
279
+
adc_dev->dev_comp = device_get_match_data(&pdev->dev);
278
280
279
281
mutex_init(&adc_dev->lock);
280
282
+17
-24
drivers/iio/adc/stm32-adc-core.c
+17
-24
drivers/iio/adc/stm32-adc-core.c
···
41
41
* struct stm32_adc_common_regs - stm32 common registers
42
42
* @csr: common status register offset
43
43
* @ccr: common control register offset
44
-
* @eoc1_msk: adc1 end of conversion flag in @csr
45
-
* @eoc2_msk: adc2 end of conversion flag in @csr
46
-
* @eoc3_msk: adc3 end of conversion flag in @csr
44
+
* @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
45
+
* @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
47
46
* @ier: interrupt enable register offset for each adc
48
47
* @eocie_msk: end of conversion interrupt enable mask in @ier
49
48
*/
50
49
struct stm32_adc_common_regs {
51
50
u32 csr;
52
51
u32 ccr;
53
-
u32 eoc1_msk;
54
-
u32 eoc2_msk;
55
-
u32 eoc3_msk;
52
+
u32 eoc_msk[STM32_ADC_MAX_ADCS];
53
+
u32 ovr_msk[STM32_ADC_MAX_ADCS];
56
54
u32 ier;
57
55
u32 eocie_msk;
58
56
};
···
280
282
static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
281
283
.csr = STM32F4_ADC_CSR,
282
284
.ccr = STM32F4_ADC_CCR,
283
-
.eoc1_msk = STM32F4_EOC1 | STM32F4_OVR1,
284
-
.eoc2_msk = STM32F4_EOC2 | STM32F4_OVR2,
285
-
.eoc3_msk = STM32F4_EOC3 | STM32F4_OVR3,
285
+
.eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
286
+
.ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
286
287
.ier = STM32F4_ADC_CR1,
287
-
.eocie_msk = STM32F4_EOCIE | STM32F4_OVRIE,
288
+
.eocie_msk = STM32F4_EOCIE,
288
289
};
289
290
290
291
/* STM32H7 common registers definitions */
291
292
static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
292
293
.csr = STM32H7_ADC_CSR,
293
294
.ccr = STM32H7_ADC_CCR,
294
-
.eoc1_msk = STM32H7_EOC_MST | STM32H7_OVR_MST,
295
-
.eoc2_msk = STM32H7_EOC_SLV | STM32H7_OVR_SLV,
295
+
.eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
296
+
.ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
296
297
.ier = STM32H7_ADC_IER,
297
-
.eocie_msk = STM32H7_EOCIE | STM32H7_OVRIE,
298
+
.eocie_msk = STM32H7_EOCIE,
298
299
};
299
300
300
301
static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
···
315
318
{
316
319
struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
317
320
struct irq_chip *chip = irq_desc_get_chip(desc);
321
+
int i;
318
322
u32 status;
319
323
320
324
chained_irq_enter(chip, desc);
···
333
335
* before invoking the interrupt handler (e.g. call ISR only for
334
336
* IRQ-enabled ADCs).
335
337
*/
336
-
if (status & priv->cfg->regs->eoc1_msk &&
337
-
stm32_adc_eoc_enabled(priv, 0))
338
-
generic_handle_irq(irq_find_mapping(priv->domain, 0));
339
-
340
-
if (status & priv->cfg->regs->eoc2_msk &&
341
-
stm32_adc_eoc_enabled(priv, 1))
342
-
generic_handle_irq(irq_find_mapping(priv->domain, 1));
343
-
344
-
if (status & priv->cfg->regs->eoc3_msk &&
345
-
stm32_adc_eoc_enabled(priv, 2))
346
-
generic_handle_irq(irq_find_mapping(priv->domain, 2));
338
+
for (i = 0; i < priv->cfg->num_irqs; i++) {
339
+
if ((status & priv->cfg->regs->eoc_msk[i] &&
340
+
stm32_adc_eoc_enabled(priv, i)) ||
341
+
(status & priv->cfg->regs->ovr_msk[i]))
342
+
generic_handle_irq(irq_find_mapping(priv->domain, i));
343
+
}
347
344
348
345
chained_irq_exit(chip, desc);
349
346
};
+48
-2
drivers/iio/adc/stm32-adc.c
+48
-2
drivers/iio/adc/stm32-adc.c
···
154
154
* @start_conv: routine to start conversions
155
155
* @stop_conv: routine to stop conversions
156
156
* @unprepare: optional unprepare routine (disable, power-down)
157
+
* @irq_clear: routine to clear irqs
157
158
* @smp_cycles: programmable sampling time (ADC clock cycles)
158
159
*/
159
160
struct stm32_adc_cfg {
···
167
166
void (*start_conv)(struct iio_dev *, bool dma);
168
167
void (*stop_conv)(struct iio_dev *);
169
168
void (*unprepare)(struct iio_dev *);
169
+
void (*irq_clear)(struct iio_dev *indio_dev, u32 msk);
170
170
const unsigned int *smp_cycles;
171
171
};
172
172
···
623
621
STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
624
622
}
625
623
624
+
static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
625
+
{
626
+
struct stm32_adc *adc = iio_priv(indio_dev);
627
+
628
+
stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
629
+
}
630
+
626
631
static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma)
627
632
{
628
633
struct stm32_adc *adc = iio_priv(indio_dev);
···
666
657
dev_warn(&indio_dev->dev, "stop failed\n");
667
658
668
659
stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
660
+
}
661
+
662
+
static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
663
+
{
664
+
struct stm32_adc *adc = iio_priv(indio_dev);
665
+
/* On STM32H7 IRQs are cleared by writing 1 into ISR register */
666
+
stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
669
667
}
670
668
671
669
static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev)
···
1251
1235
}
1252
1236
}
1253
1237
1238
+
static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
1239
+
{
1240
+
struct stm32_adc *adc = iio_priv(indio_dev);
1241
+
1242
+
adc->cfg->irq_clear(indio_dev, msk);
1243
+
}
1244
+
1254
1245
static irqreturn_t stm32_adc_threaded_isr(int irq, void *data)
1255
1246
{
1256
1247
struct iio_dev *indio_dev = data;
1257
1248
struct stm32_adc *adc = iio_priv(indio_dev);
1258
1249
const struct stm32_adc_regspec *regs = adc->cfg->regs;
1259
1250
u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1251
+
u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg);
1260
1252
1261
-
if (status & regs->isr_ovr.mask)
1253
+
/* Check ovr status right now, as ovr mask should be already disabled */
1254
+
if (status & regs->isr_ovr.mask) {
1255
+
/*
1256
+
* Clear ovr bit to avoid subsequent calls to IRQ handler.
1257
+
* This requires to stop ADC first. OVR bit state in ISR,
1258
+
* is propaged to CSR register by hardware.
1259
+
*/
1260
+
adc->cfg->stop_conv(indio_dev);
1261
+
stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask);
1262
1262
dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n");
1263
+
return IRQ_HANDLED;
1264
+
}
1263
1265
1264
-
return IRQ_HANDLED;
1266
+
if (!(status & mask))
1267
+
dev_err_ratelimited(&indio_dev->dev,
1268
+
"Unexpected IRQ: IER=0x%08x, ISR=0x%08x\n",
1269
+
mask, status);
1270
+
1271
+
return IRQ_NONE;
1265
1272
}
1266
1273
1267
1274
static irqreturn_t stm32_adc_isr(int irq, void *data)
···
1293
1254
struct stm32_adc *adc = iio_priv(indio_dev);
1294
1255
const struct stm32_adc_regspec *regs = adc->cfg->regs;
1295
1256
u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1257
+
u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg);
1258
+
1259
+
if (!(status & mask))
1260
+
return IRQ_WAKE_THREAD;
1296
1261
1297
1262
if (status & regs->isr_ovr.mask) {
1298
1263
/*
···
2089
2046
.start_conv = stm32f4_adc_start_conv,
2090
2047
.stop_conv = stm32f4_adc_stop_conv,
2091
2048
.smp_cycles = stm32f4_adc_smp_cycles,
2049
+
.irq_clear = stm32f4_adc_irq_clear,
2092
2050
};
2093
2051
2094
2052
static const struct stm32_adc_cfg stm32h7_adc_cfg = {
···
2101
2057
.prepare = stm32h7_adc_prepare,
2102
2058
.unprepare = stm32h7_adc_unprepare,
2103
2059
.smp_cycles = stm32h7_adc_smp_cycles,
2060
+
.irq_clear = stm32h7_adc_irq_clear,
2104
2061
};
2105
2062
2106
2063
static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
···
2114
2069
.prepare = stm32h7_adc_prepare,
2115
2070
.unprepare = stm32h7_adc_unprepare,
2116
2071
.smp_cycles = stm32h7_adc_smp_cycles,
2072
+
.irq_clear = stm32h7_adc_irq_clear,
2117
2073
};
2118
2074
2119
2075
static const struct of_device_id stm32_adc_of_match[] = {
+11
-5
drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c
+11
-5
drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c
···
256
256
struct cros_ec_sensorhub *sensor_hub = dev_get_drvdata(dev->parent);
257
257
struct cros_ec_dev *ec = sensor_hub->ec;
258
258
struct cros_ec_sensor_platform *sensor_platform = dev_get_platdata(dev);
259
-
u32 ver_mask;
259
+
u32 ver_mask, temp;
260
260
int frequencies[ARRAY_SIZE(state->frequencies) / 2] = { 0 };
261
261
int ret, i;
262
262
···
311
311
&frequencies[2],
312
312
&state->fifo_max_event_count);
313
313
} else {
314
-
frequencies[1] = state->resp->info_3.min_frequency;
315
-
frequencies[2] = state->resp->info_3.max_frequency;
316
-
state->fifo_max_event_count =
317
-
state->resp->info_3.fifo_max_event_count;
314
+
if (state->resp->info_3.max_frequency == 0) {
315
+
get_default_min_max_freq(state->resp->info.type,
316
+
&frequencies[1],
317
+
&frequencies[2],
318
+
&temp);
319
+
} else {
320
+
frequencies[1] = state->resp->info_3.min_frequency;
321
+
frequencies[2] = state->resp->info_3.max_frequency;
322
+
}
323
+
state->fifo_max_event_count = state->resp->info_3.fifo_max_event_count;
318
324
}
319
325
for (i = 0; i < ARRAY_SIZE(frequencies); i++) {
320
326
state->frequencies[2 * i] = frequencies[i] / 1000;
+4
-2
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c
+4
-2
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c
···
156
156
static void st_lsm6dsx_shub_wait_complete(struct st_lsm6dsx_hw *hw)
157
157
{
158
158
struct st_lsm6dsx_sensor *sensor;
159
-
u32 odr;
159
+
u32 odr, timeout;
160
160
161
161
sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
162
162
odr = (hw->enable_mask & BIT(ST_LSM6DSX_ID_ACC)) ? sensor->odr : 12500;
163
-
msleep((2000000U / odr) + 1);
163
+
/* set 10ms as minimum timeout for i2c slave configuration */
164
+
timeout = max_t(u32, 2000000U / odr + 1, 10);
165
+
msleep(timeout);
164
166
}
165
167
166
168
/*
+1
drivers/iio/light/Kconfig
+1
drivers/iio/light/Kconfig
+3
-12
drivers/staging/mt7621-pci/pci-mt7621.c
+3
-12
drivers/staging/mt7621-pci/pci-mt7621.c
···
653
653
return 0;
654
654
}
655
655
656
-
static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
657
-
struct list_head *res)
656
+
static void mt7621_pcie_add_resources(struct mt7621_pcie *pcie,
657
+
struct list_head *res)
658
658
{
659
-
struct device *dev = pcie->dev;
660
-
661
659
pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
662
660
pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
663
-
pci_add_resource(res, &pcie->busn);
664
-
665
-
return devm_request_pci_bus_resources(dev, res);
666
661
}
667
662
668
663
static int mt7621_pcie_register_host(struct pci_host_bridge *host,
···
733
738
734
739
setup_cm_memory_region(pcie);
735
740
736
-
err = mt7621_pcie_request_resources(pcie, &res);
737
-
if (err) {
738
-
dev_err(dev, "Error requesting resources\n");
739
-
return err;
740
-
}
741
+
mt7621_pcie_add_resources(pcie, &res);
741
742
742
743
err = mt7621_pcie_register_host(bridge, &res);
743
744
if (err) {
+1
drivers/staging/ralink-gdma/Kconfig
+1
drivers/staging/ralink-gdma/Kconfig