Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mmc-v5.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC host fixes from Ulf Hansson:
- mtk-sd: Fix tuning for MT8173 HS200/HS400 mode
- sdhci: Revert a fix for incorrect switch to HS mode
- sdhci-msm: Fixup accesses to the DDR_CONFIG register
- sdhci-of-esdhc: Revert a bad fix for erratum A-009204
- sdhci-of-esdhc: Re-implement fix for erratum A-009204
- sdhci-of-esdhc: Fixup P2020 errata handling
- sdhci-pci: Disable broken CMDQ on Intel GLK based Lenovo systems
* tag 'mmc-v5.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: sdhci-of-esdhc: re-implement erratum A-009204 workaround
mmc: sdhci: Add a quirk for broken command queuing
mmc: sdhci: Workaround broken command queuing on Intel GLK
mmc: sdhci-of-esdhc: fix P2020 errata handling
mmc: sdhci: Update the tuning failed messages to pr_debug level
mmc: sdhci-of-esdhc: Revert "mmc: sdhci-of-esdhc: add erratum A-009204 support"
mmc: mediatek: fix CMD_TA to 2 for MT8173 HS200/HS400 mode
mmc: sdhci-msm: Correct the offset and value for DDR_CONFIG register
Revert "mmc: sdhci: Fix incorrect switch to HS mode"
+50
-20
+2
drivers/mmc/host/mtk-sd.c
+2
drivers/mmc/host/mtk-sd.c
···
228
228
#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
229
229
#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
230
230
231
+
#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
231
232
#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
232
233
233
234
#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
···
1882
1881
1883
1882
/* select EMMC50 PAD CMD tune */
1884
1883
sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1884
+
sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
1885
1885
1886
1886
if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1887
1887
mmc->ios.timing == MMC_TIMING_UHS_SDR104)
+19
-9
drivers/mmc/host/sdhci-msm.c
+19
-9
drivers/mmc/host/sdhci-msm.c
···
99
99
100
100
#define CORE_PWRSAVE_DLL BIT(3)
101
101
102
-
#define DDR_CONFIG_POR_VAL 0x80040853
102
+
#define DDR_CONFIG_POR_VAL 0x80040873
103
103
104
104
105
105
#define INVALID_TUNING_PHASE -1
···
148
148
u32 core_ddr_200_cfg;
149
149
u32 core_vendor_spec3;
150
150
u32 core_dll_config_2;
151
+
u32 core_dll_config_3;
152
+
u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
151
153
u32 core_ddr_config;
152
-
u32 core_ddr_config_2;
153
154
};
154
155
155
156
static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
···
178
177
.core_ddr_200_cfg = 0x224,
179
178
.core_vendor_spec3 = 0x250,
180
179
.core_dll_config_2 = 0x254,
181
-
.core_ddr_config = 0x258,
182
-
.core_ddr_config_2 = 0x25c,
180
+
.core_dll_config_3 = 0x258,
181
+
.core_ddr_config = 0x25c,
183
182
};
184
183
185
184
static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
···
208
207
.core_ddr_200_cfg = 0x184,
209
208
.core_vendor_spec3 = 0x1b0,
210
209
.core_dll_config_2 = 0x1b4,
211
-
.core_ddr_config = 0x1b8,
212
-
.core_ddr_config_2 = 0x1bc,
210
+
.core_ddr_config_old = 0x1b8,
211
+
.core_ddr_config = 0x1bc,
213
212
};
214
213
215
214
struct sdhci_msm_variant_ops {
···
254
253
const struct sdhci_msm_offset *offset;
255
254
bool use_cdr;
256
255
u32 transfer_mode;
256
+
bool updated_ddr_cfg;
257
257
};
258
258
259
259
static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
···
926
924
static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
927
925
{
928
926
struct mmc_host *mmc = host->mmc;
929
-
u32 dll_status, config;
927
+
u32 dll_status, config, ddr_cfg_offset;
930
928
int ret;
929
+
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
930
+
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
931
931
const struct sdhci_msm_offset *msm_offset =
932
932
sdhci_priv_msm_offset(host);
933
933
···
942
938
* bootloaders. In the future, if this changes, then the desired
943
939
* values will need to be programmed appropriately.
944
940
*/
945
-
writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr +
946
-
msm_offset->core_ddr_config);
941
+
if (msm_host->updated_ddr_cfg)
942
+
ddr_cfg_offset = msm_offset->core_ddr_config;
943
+
else
944
+
ddr_cfg_offset = msm_offset->core_ddr_config_old;
945
+
writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset);
947
946
948
947
if (mmc->ios.enhanced_strobe) {
949
948
config = readl_relaxed(host->ioaddr +
···
1905
1898
writel_relaxed(config, host->ioaddr +
1906
1899
msm_offset->core_vendor_spec_capabilities0);
1907
1900
}
1901
+
1902
+
if (core_major == 1 && core_minor >= 0x49)
1903
+
msm_host->updated_ddr_cfg = true;
1908
1904
1909
1905
/*
1910
1906
* Power on reset state may trigger power irq if previous status of
+12
-5
drivers/mmc/host/sdhci-of-esdhc.c
+12
-5
drivers/mmc/host/sdhci-of-esdhc.c
···
80
80
bool quirk_tuning_erratum_type1;
81
81
bool quirk_tuning_erratum_type2;
82
82
bool quirk_ignore_data_inhibit;
83
+
bool quirk_delay_before_data_reset;
83
84
bool in_sw_tuning;
84
85
unsigned int peripheral_clock;
85
86
const struct esdhc_clk_fixup *clk_fixup;
···
760
759
struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
761
760
u32 val;
762
761
762
+
if (esdhc->quirk_delay_before_data_reset &&
763
+
(mask & SDHCI_RESET_DATA) &&
764
+
(host->flags & SDHCI_REQ_USE_DMA))
765
+
mdelay(5);
766
+
763
767
sdhci_reset(host, mask);
764
768
765
769
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
766
770
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
767
-
768
-
if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc"))
769
-
mdelay(5);
770
771
771
772
if (mask & SDHCI_RESET_ALL) {
772
773
val = sdhci_readl(host, ESDHC_TBCTL);
···
1224
1221
if (match)
1225
1222
esdhc->clk_fixup = match->data;
1226
1223
np = pdev->dev.of_node;
1224
+
1225
+
if (of_device_is_compatible(np, "fsl,p2020-esdhc"))
1226
+
esdhc->quirk_delay_before_data_reset = true;
1227
+
1227
1228
clk = of_clk_get(np, 0);
1228
1229
if (!IS_ERR(clk)) {
1229
1230
/*
···
1310
1303
host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1311
1304
1312
1305
if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
1313
-
host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
1314
-
host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1306
+
host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
1307
+
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1315
1308
}
1316
1309
1317
1310
if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
+9
-1
drivers/mmc/host/sdhci-pci-core.c
+9
-1
drivers/mmc/host/sdhci-pci-core.c
···
27
27
#include <linux/mmc/slot-gpio.h>
28
28
#include <linux/mmc/sdhci-pci-data.h>
29
29
#include <linux/acpi.h>
30
+
#include <linux/dmi.h>
30
31
31
32
#ifdef CONFIG_X86
32
33
#include <asm/iosf_mbi.h>
···
784
783
return 0;
785
784
}
786
785
786
+
static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
787
+
{
788
+
return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
789
+
dmi_match(DMI_BIOS_VENDOR, "LENOVO");
790
+
}
791
+
787
792
static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
788
793
{
789
794
int ret = byt_emmc_probe_slot(slot);
790
795
791
-
slot->host->mmc->caps2 |= MMC_CAP2_CQE;
796
+
if (!glk_broken_cqhci(slot))
797
+
slot->host->mmc->caps2 |= MMC_CAP2_CQE;
792
798
793
799
if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
794
800
slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
+6
-5
drivers/mmc/host/sdhci.c
+6
-5
drivers/mmc/host/sdhci.c
···
1882
1882
ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1883
1883
else if (timing == MMC_TIMING_UHS_SDR12)
1884
1884
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1885
-
else if (timing == MMC_TIMING_SD_HS ||
1886
-
timing == MMC_TIMING_MMC_HS ||
1887
-
timing == MMC_TIMING_UHS_SDR25)
1885
+
else if (timing == MMC_TIMING_UHS_SDR25)
1888
1886
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1889
1887
else if (timing == MMC_TIMING_UHS_SDR50)
1890
1888
ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
···
2417
2419
sdhci_send_tuning(host, opcode);
2418
2420
2419
2421
if (!host->tuning_done) {
2420
-
pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2421
-
mmc_hostname(host->mmc));
2422
+
pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2423
+
mmc_hostname(host->mmc));
2422
2424
sdhci_abort_tuning(host, opcode);
2423
2425
return -ETIMEDOUT;
2424
2426
}
···
3766
3768
pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3767
3769
mmc_hostname(mmc), host->version);
3768
3770
}
3771
+
3772
+
if (host->quirks & SDHCI_QUIRK_BROKEN_CQE)
3773
+
mmc->caps2 &= ~MMC_CAP2_CQE;
3769
3774
3770
3775
if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3771
3776
host->flags |= SDHCI_USE_SDMA;
+2
drivers/mmc/host/sdhci.h
+2
drivers/mmc/host/sdhci.h
···
409
409
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
410
410
/* Controller reports inverted write-protect state */
411
411
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
412
+
/* Controller has unusable command queue engine */
413
+
#define SDHCI_QUIRK_BROKEN_CQE (1<<17)
412
414
/* Controller does not like fast PIO transfers */
413
415
#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
414
416
/* Controller does not have a LED */