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phy: renesas: r8a779f0-eth-serdes: Add .power_on() into phy_ops

Add r8a779f0_eth_serdes_power_on() to initialize the hardware for
each channel from the step 9 or later on the datasheet. In other words,
the procedure from the step 1 to 8 is for all channel and it is needed
once only. So, the .init() in any channel instance is called, this
driver initializes the hardware from step 1 to 8. And then, .power_on()
is called, this driver initializes the hardware from step 9 or later.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221226065316.3895480-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Yoshihiro Shimoda and committed by
Vinod Koul d2aa66a9 4214f371

+29 -28
+29 -28
drivers/phy/renesas/r8a779f0-ether-serdes.c
··· 242 242 if (ret) 243 243 return ret; 244 244 245 - ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0); 246 - if (ret) 247 - return ret; 248 - 249 - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 250 - ret = r8a779f0_eth_serdes_chan_setting(&dd->channel[i]); 251 - if (ret) 252 - return ret; 253 - } 254 - 255 - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 256 - ret = r8a779f0_eth_serdes_chan_speed(&dd->channel[i]); 257 - if (ret) 258 - return ret; 259 - } 260 - 261 - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) 262 - r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03c0, 0x380, 0x0000); 263 - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) 264 - r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0000); 265 - 266 - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 267 - ret = r8a779f0_eth_serdes_monitor_linkup(&dd->channel[i]); 268 - if (ret) 269 - return ret; 270 - } 271 - 272 - return 0; 245 + return r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0); 273 246 } 274 247 275 248 static int r8a779f0_eth_serdes_init(struct phy *p) ··· 260 287 } 261 288 262 289 return ret; 290 + } 291 + 292 + static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel 293 + *channel) 294 + { 295 + int ret; 296 + 297 + ret = r8a779f0_eth_serdes_chan_setting(channel); 298 + if (ret) 299 + return ret; 300 + 301 + ret = r8a779f0_eth_serdes_chan_speed(channel); 302 + if (ret) 303 + return ret; 304 + 305 + r8a779f0_eth_serdes_write32(channel->addr, 0x03c0, 0x380, 0x0000); 306 + 307 + r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000); 308 + 309 + return r8a779f0_eth_serdes_monitor_linkup(channel); 310 + } 311 + 312 + static int r8a779f0_eth_serdes_power_on(struct phy *p) 313 + { 314 + struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p); 315 + 316 + return r8a779f0_eth_serdes_hw_init_late(channel); 263 317 } 264 318 265 319 static int r8a779f0_eth_serdes_set_mode(struct phy *p, enum phy_mode mode, ··· 319 319 320 320 static const struct phy_ops r8a779f0_eth_serdes_ops = { 321 321 .init = r8a779f0_eth_serdes_init, 322 + .power_on = r8a779f0_eth_serdes_power_on, 322 323 .set_mode = r8a779f0_eth_serdes_set_mode, 323 324 .set_speed = r8a779f0_eth_serdes_set_speed, 324 325 };