Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
fpga: dfl: afu: add AFU state related sysfs interfaces
This patch introduces more sysfs interfaces for Accelerated
Function Unit (AFU). These interfaces allow users to read
current AFU Power State (APx), read / clear AFU Power (APx)
events which are sticky to identify transient APx state,
and manage AFU's LTR (latency tolerance reporting).
Signed-off-by: Ananda Ravuri <ananda.ravuri@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/1564914022-3710-4-git-send-email-hao.wu@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Wu Hao
and committed by
Greg Kroah-Hartman
d2ad5ac1
bdd4f307
+180
+32
Documentation/ABI/testing/sysfs-platform-dfl-port
+32
Documentation/ABI/testing/sysfs-platform-dfl-port
···
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Accelerator Function Unit (AFU) for different functions. It
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returns uuid which could be used to identify which PR bitstream
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is programmed in this AFU.
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What: /sys/bus/platform/devices/dfl-port.0/power_state
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. It reports the APx (AFU Power) state, different APx
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means different throttling level. When reading this file, it
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returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
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What: /sys/bus/platform/devices/dfl-port.0/ap1_event
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
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It's used to indicate transient AP1 state. Write 1 to this
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file to clear AP1 event.
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What: /sys/bus/platform/devices/dfl-port.0/ap2_event
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-write. Read this file for AP2 (AFU Power State 2) event.
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It's used to indicate transient AP2 state. Write 1 to this
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file to clear AP2 event.
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What: /sys/bus/platform/devices/dfl-port.0/ltr
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-write. Read or set AFU latency tolerance reporting value.
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Set ltr to 1 if the AFU can tolerate latency >= 40us or set it
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to 0 if it is latency sensitive.
+137
drivers/fpga/dfl-afu-main.c
+137
drivers/fpga/dfl-afu-main.c
···
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}
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static DEVICE_ATTR_RO(id);
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static ssize_t
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ltr_show(struct device *dev, struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
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mutex_lock(&pdata->lock);
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v = readq(base + PORT_HDR_CTRL);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_CTRL_LATENCY, v));
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}
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static ssize_t
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ltr_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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bool ltr;
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u64 v;
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if (kstrtobool(buf, <r))
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
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mutex_lock(&pdata->lock);
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v = readq(base + PORT_HDR_CTRL);
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v &= ~PORT_CTRL_LATENCY;
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v |= FIELD_PREP(PORT_CTRL_LATENCY, ltr ? 1 : 0);
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writeq(v, base + PORT_HDR_CTRL);
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mutex_unlock(&pdata->lock);
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return count;
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}
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static DEVICE_ATTR_RW(ltr);
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static ssize_t
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ap1_event_show(struct device *dev, struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
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mutex_lock(&pdata->lock);
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v = readq(base + PORT_HDR_STS);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_STS_AP1_EVT, v));
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}
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static ssize_t
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ap1_event_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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bool clear;
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if (kstrtobool(buf, &clear) || !clear)
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
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mutex_lock(&pdata->lock);
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writeq(PORT_STS_AP1_EVT, base + PORT_HDR_STS);
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mutex_unlock(&pdata->lock);
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return count;
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}
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static DEVICE_ATTR_RW(ap1_event);
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static ssize_t
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ap2_event_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
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mutex_lock(&pdata->lock);
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v = readq(base + PORT_HDR_STS);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_STS_AP2_EVT, v));
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}
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static ssize_t
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ap2_event_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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bool clear;
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if (kstrtobool(buf, &clear) || !clear)
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
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mutex_lock(&pdata->lock);
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writeq(PORT_STS_AP2_EVT, base + PORT_HDR_STS);
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mutex_unlock(&pdata->lock);
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return count;
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}
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static DEVICE_ATTR_RW(ap2_event);
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static ssize_t
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power_state_show(struct device *dev, struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
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mutex_lock(&pdata->lock);
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v = readq(base + PORT_HDR_STS);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%x\n", (u8)FIELD_GET(PORT_STS_PWR_STATE, v));
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}
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static DEVICE_ATTR_RO(power_state);
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static struct attribute *port_hdr_attrs[] = {
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&dev_attr_id.attr,
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&dev_attr_ltr.attr,
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&dev_attr_ap1_event.attr,
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&dev_attr_ap2_event.attr,
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&dev_attr_power_state.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(port_hdr);
+11
drivers/fpga/dfl.h
+11
drivers/fpga/dfl.h
···
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#define PORT_HDR_NEXT_AFU NEXT_AFU
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#define PORT_HDR_CAP 0x30
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#define PORT_HDR_CTRL 0x38
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#define PORT_HDR_STS 0x40
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/* Port Capability Register Bitfield */
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#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
···
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/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
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#define PORT_CTRL_LATENCY BIT_ULL(2)
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#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
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/* Port Status Register Bitfield */
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#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
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#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
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#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
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#define PORT_STS_PWR_STATE_NORM 0
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#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
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#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
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#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
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/**
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* struct dfl_fpga_port_ops - port ops
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*