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drm/msm: Fix a7xx per pipe register programming

GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe
but it needs to be programmed for both.

Program both pipes in hw_init and introducea separate reglist for it in
order to add this register to the dynamic reglist which supports
restoring registers per pipe.

Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info")
Cc: stable@vger.kernel.org
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/691553/
Message-ID: <20251201-gras_nc_mode_fix-v3-1-92a8a10d91d0@gmail.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Anna Maniscalco and committed by
Rob Clark d2b6e710 6c6915bf

+55 -5
+11 -1
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
··· 1376 1376 REG_A6XX_UCHE_MODE_CNTL, 1377 1377 REG_A6XX_RB_NC_MODE_CNTL, 1378 1378 REG_A6XX_RB_CMP_DBG_ECO_CNTL, 1379 - REG_A7XX_GRAS_NC_MODE_CNTL, 1380 1379 REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 1381 1380 REG_A6XX_UCHE_GBIF_GX_CONFIG, 1382 1381 REG_A6XX_UCHE_CLIENT_PF, ··· 1448 1449 1449 1450 DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); 1450 1451 1452 + static const struct adreno_reglist_pipe a7xx_dyn_pwrup_reglist_regs[] = { 1453 + { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1454 + }; 1455 + 1456 + DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist); 1457 + 1451 1458 static const struct adreno_info a7xx_gpus[] = { 1452 1459 { 1453 1460 .chip_ids = ADRENO_CHIP_IDS(0x07000200), ··· 1497 1492 .hwcg = a730_hwcg, 1498 1493 .protect = &a730_protect, 1499 1494 .pwrup_reglist = &a7xx_pwrup_reglist, 1495 + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, 1500 1496 .gbif_cx = a640_gbif, 1501 1497 .gmu_cgc_mode = 0x00020000, 1502 1498 }, ··· 1520 1514 .hwcg = a740_hwcg, 1521 1515 .protect = &a730_protect, 1522 1516 .pwrup_reglist = &a7xx_pwrup_reglist, 1517 + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, 1523 1518 .gbif_cx = a640_gbif, 1524 1519 .gmu_chipid = 0x7020100, 1525 1520 .gmu_cgc_mode = 0x00020202, ··· 1555 1548 .hwcg = a740_hwcg, 1556 1549 .protect = &a730_protect, 1557 1550 .pwrup_reglist = &a7xx_pwrup_reglist, 1551 + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, 1558 1552 .ifpc_reglist = &a750_ifpc_reglist, 1559 1553 .gbif_cx = a640_gbif, 1560 1554 .gmu_chipid = 0x7050001, ··· 1598 1590 .a6xx = &(const struct a6xx_info) { 1599 1591 .protect = &a730_protect, 1600 1592 .pwrup_reglist = &a7xx_pwrup_reglist, 1593 + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, 1601 1594 .ifpc_reglist = &a750_ifpc_reglist, 1602 1595 .gbif_cx = a640_gbif, 1603 1596 .gmu_chipid = 0x7090100, ··· 1633 1624 .hwcg = a740_hwcg, 1634 1625 .protect = &a730_protect, 1635 1626 .pwrup_reglist = &a7xx_pwrup_reglist, 1627 + .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist, 1636 1628 .gbif_cx = a640_gbif, 1637 1629 .gmu_chipid = 0x70f0000, 1638 1630 .gmu_cgc_mode = 0x00020222,
+30 -4
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 849 849 min_acc_len_64b << 3 | 850 850 hbb_lo << 1 | ubwc_mode); 851 851 852 - if (adreno_is_a7xx(adreno_gpu)) 853 - gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 854 - FIELD_PREP(GENMASK(8, 5), hbb_lo)); 852 + if (adreno_is_a7xx(adreno_gpu)) { 853 + for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) { 854 + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 855 + A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); 856 + gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 857 + FIELD_PREP(GENMASK(8, 5), hbb_lo)); 858 + } 859 + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 860 + A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); 861 + } 855 862 856 863 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 857 864 min_acc_len_64b << 23 | hbb_lo << 21); ··· 872 865 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 873 866 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 874 867 const struct adreno_reglist_list *reglist; 868 + const struct adreno_reglist_pipe_list *dyn_pwrup_reglist; 875 869 void *ptr = a6xx_gpu->pwrup_reglist_ptr; 876 870 struct cpu_gpu_lock *lock = ptr; 877 871 u32 *dest = (u32 *)&lock->regs[0]; 872 + u32 dyn_pwrup_reglist_count = 0; 878 873 int i; 879 874 880 875 lock->gpu_req = lock->cpu_req = lock->turn = 0; ··· 918 909 * (<aperture, shifted 12 bits> <address> <data>), and the length is 919 910 * stored as number for triplets in dynamic_list_len. 920 911 */ 921 - lock->dynamic_list_len = 0; 912 + dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist; 913 + if (dyn_pwrup_reglist) { 914 + for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) { 915 + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 916 + A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); 917 + for (i = 0; i < dyn_pwrup_reglist->count; i++) { 918 + if ((dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)) == 0) 919 + continue; 920 + *dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id); 921 + *dest++ = dyn_pwrup_reglist->regs[i].offset; 922 + *dest++ = gpu_read(gpu, dyn_pwrup_reglist->regs[i].offset); 923 + dyn_pwrup_reglist_count++; 924 + } 925 + } 926 + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 927 + A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); 928 + } 929 + lock->dynamic_list_len = dyn_pwrup_reglist_count; 922 930 } 923 931 924 932 static int a7xx_preempt_start(struct msm_gpu *gpu)
+1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
··· 45 45 const struct adreno_reglist *hwcg; 46 46 const struct adreno_protect *protect; 47 47 const struct adreno_reglist_list *pwrup_reglist; 48 + const struct adreno_reglist_pipe_list *dyn_pwrup_reglist; 48 49 const struct adreno_reglist_list *ifpc_reglist; 49 50 const struct adreno_reglist *gbif_cx; 50 51 const struct adreno_reglist_pipe *nonctxt_reglist;
+13
drivers/gpu/drm/msm/adreno/adreno_gpu.h
··· 188 188 .count = ARRAY_SIZE(name ## _regs), \ 189 189 }; 190 190 191 + struct adreno_reglist_pipe_list { 192 + /** @reg: List of register **/ 193 + const struct adreno_reglist_pipe *regs; 194 + /** @count: Number of registers in the list **/ 195 + u32 count; 196 + }; 197 + 198 + #define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \ 199 + static const struct adreno_reglist_pipe_list name = { \ 200 + .regs = name ## _regs, \ 201 + .count = ARRAY_SIZE(name ## _regs), \ 202 + }; 203 + 191 204 struct adreno_gpu { 192 205 struct msm_gpu base; 193 206 const struct adreno_info *info;