+5 -1

Documentation/devicetree/bindings/eeprom/eeprom.txt

reviewed

··· 16 16 17 17 "renesas,r1ex24002" 18 18 19 19 + The following manufacturers values have been deprecated: 20 20 + "at", "at24" 21 21 + 19 22 If there is no specific driver for <manufacturer>, a generic 20 20 - driver based on <type> is selected. Possible types are: 23 23 + device with <type> and manufacturer "atmel" should be used. 24 24 + Possible types are: 21 25 "24c00", "24c01", "24c02", "24c04", "24c08", "24c16", "24c32", "24c64", 22 26 "24c128", "24c256", "24c512", "24c1024", "spd" 23 27

+8 -7

Documentation/devicetree/bindings/i2c/i2c-mtk.txt

reviewed

··· 1 1 - * Mediatek's I2C controller 1 1 + * MediaTek's I2C controller 2 2 3 3 - The Mediatek's I2C controller is used to interface with I2C devices. 3 3 + The MediaTek's I2C controller is used to interface with I2C devices. 4 4 5 5 Required properties: 6 6 - compatible: value should be either of the following. 7 7 - "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701 8 8 - "mediatek,mt6577-i2c": for i2c compatible with mt6577. 9 9 - "mediatek,mt6589-i2c": for i2c compatible with mt6589. 10 10 - "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623. 11 11 - "mediatek,mt8173-i2c": for i2c compatible with mt8173. 7 7 + "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701 8 8 + "mediatek,mt6577-i2c": for MediaTek MT6577 9 9 + "mediatek,mt6589-i2c": for MediaTek MT6589 10 10 + "mediatek,mt7622-i2c": for MediaTek MT7622 11 11 + "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 12 12 + "mediatek,mt8173-i2c": for MediaTek MT8173 12 13 - reg: physical base address of the controller and dma base, length of memory 13 14 mapped region. 14 15 - interrupts: interrupt number to the cpu.

+4 -1

Documentation/devicetree/bindings/i2c/i2c-rcar.txt

reviewed

··· 2 2 3 3 Required properties: 4 4 - compatible: 5 5 + "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC. 6 6 + "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC. 5 7 "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC. 6 8 "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC. 7 9 "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC. ··· 14 12 "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. 15 13 "renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC. 16 14 "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. 17 17 - "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device. 15 15 + "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible 16 16 + device. 18 17 "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device. 19 18 "renesas,i2c-rcar" (deprecated) 20 19

+1

Documentation/devicetree/bindings/i2c/i2c-rk3x.txt

reviewed

··· 7 7 8 8 - reg : Offset and length of the register set for the device 9 9 - compatible: should be one of the following: 10 10 + - "rockchip,rv1108-i2c": for rv1108 10 11 - "rockchip,rk3066-i2c": for rk3066 11 12 - "rockchip,rk3188-i2c": for rk3188 12 13 - "rockchip,rk3228-i2c": for rk3228

+4 -1

Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt

reviewed

··· 4 4 - compatible : 5 5 - "renesas,iic-r8a73a4" (R-Mobile APE6) 6 6 - "renesas,iic-r8a7740" (R-Mobile A1) 7 7 + - "renesas,iic-r8a7743" (RZ/G1M) 8 8 + - "renesas,iic-r8a7745" (RZ/G1E) 7 9 - "renesas,iic-r8a7790" (R-Car H2) 8 10 - "renesas,iic-r8a7791" (R-Car M2-W) 9 11 - "renesas,iic-r8a7792" (R-Car V2H) ··· 14 12 - "renesas,iic-r8a7795" (R-Car H3) 15 13 - "renesas,iic-r8a7796" (R-Car M3-W) 16 14 - "renesas,iic-sh73a0" (SH-Mobile AG5) 17 17 - - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device) 15 15 + - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1 16 16 + compatible device) 18 17 - "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device) 19 18 - "renesas,rmobile-iic" (generic device) 20 19

+31

Documentation/devicetree/bindings/i2c/i2c-sprd.txt

reviewed

··· 1 1 + I2C for Spreadtrum platforms 2 2 + 3 3 + Required properties: 4 4 + - compatible: Should be "sprd,sc9860-i2c". 5 5 + - reg: Specify the physical base address of the controller and length 6 6 + of memory mapped region. 7 7 + - interrupts: Should contain I2C interrupt. 8 8 + - clock-names: Should contain following entries: 9 9 + "i2c" for I2C clock, 10 10 + "source" for I2C source (parent) clock, 11 11 + "enable" for I2C module enable clock. 12 12 + - clocks: Should contain a clock specifier for each entry in clock-names. 13 13 + - clock-frequency: Constains desired I2C bus clock frequency in Hz. 14 14 + - #address-cells: Should be 1 to describe address cells for I2C device address. 15 15 + - #size-cells: Should be 0 means no size cell for I2C device address. 16 16 + 17 17 + Optional properties: 18 18 + - Child nodes conforming to I2C bus binding 19 19 + 20 20 + Examples: 21 21 + i2c0: i2c@70500000 { 22 22 + compatible = "sprd,sc9860-i2c"; 23 23 + reg = <0 0x70500000 0 0x1000>; 24 24 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 25 25 + clock-names = "i2c", "source", "enable"; 26 26 + clocks = <&clk_i2c3>, <&ext_26m>, <&clk_ap_apb_gates 11>; 27 27 + clock-frequency = <400000>; 28 28 + #address-cells = <1>; 29 29 + #size-cells = <0>; 30 30 + }; 31 31 +

+6

Documentation/i2c/i2c-topology

reviewed

··· 42 42 i2c-mux-gpio Normally parent-locked, mux-locked iff 43 43 all involved gpio pins are controlled by the 44 44 same i2c root adapter that they mux. 45 45 + i2c-mux-gpmux Normally parent-locked, mux-locked iff 46 46 + specified in device-tree. 47 47 + i2c-mux-ltc4306 Mux-locked 48 48 + i2c-mux-mlxcpld Parent-locked 45 49 i2c-mux-pca9541 Parent-locked 46 50 i2c-mux-pca954x Parent-locked 47 51 i2c-mux-pinctrl Normally parent-locked, mux-locked iff ··· 54 50 i2c-mux-reg Parent-locked 55 51 56 52 In drivers/iio/ 53 53 + gyro/mpu3050 Mux-locked 57 54 imu/inv_mpu6050/ Mux-locked 58 55 59 56 In drivers/media/ 57 57 + dvb-frontends/lgdt3306a Mux-locked 60 58 dvb-frontends/m88ds3103 Parent-locked 61 59 dvb-frontends/rtl2830 Parent-locked 62 60 dvb-frontends/rtl2832 Mux-locked

+6 -9

MAINTAINERS

reviewed

··· 2575 2575 S: Supported 2576 2576 F: drivers/net/ethernet/adi/ 2577 2577 2578 2578 - BLACKFIN I2C TWI DRIVER 2579 2579 - M: Sonic Zhang <sonic.zhang@analog.com> 2580 2580 - L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) 2581 2581 - W: http://blackfin.uclinux.org/ 2582 2582 - S: Supported 2583 2583 - F: drivers/i2c/busses/i2c-bfin-twi.c 2584 2584 - 2585 2578 BLACKFIN MEDIA DRIVER 2586 2579 M: Scott Jiang <scott.jiang.linux@gmail.com> 2587 2580 L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) ··· 2591 2598 F: drivers/rtc/rtc-bfin.c 2592 2599 2593 2600 BLACKFIN SDH DRIVER 2594 2594 - M: Sonic Zhang <sonic.zhang@analog.com> 2595 2601 L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) 2596 2602 W: http://blackfin.uclinux.org 2597 2603 S: Supported 2598 2604 F: drivers/mmc/host/bfin_sdh.c 2599 2605 2600 2606 BLACKFIN SERIAL DRIVER 2601 2601 - M: Sonic Zhang <sonic.zhang@analog.com> 2602 2607 L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) 2603 2608 W: http://blackfin.uclinux.org 2604 2609 S: Supported ··· 6431 6440 F: drivers/i2c/busses/i2c-sis96x.c 6432 6441 F: drivers/i2c/busses/i2c-via.c 6433 6442 F: drivers/i2c/busses/i2c-viapro.c 6443 6443 + 6444 6444 + I2C/SMBUS INTEL CHT WHISKEY COVE PMIC DRIVER 6445 6445 + M: Hans de Goede <hdegoede@redhat.com> 6446 6446 + L: linux-i2c@vger.kernel.org 6447 6447 + S: Maintained 6448 6448 + F: drivers/i2c/busses/i2c-cht-wc.c 6434 6449 6435 6450 I2C/SMBUS ISMT DRIVER 6436 6451 M: Seth Heasley <seth.heasley@intel.com>

+133 -1

arch/blackfin/include/asm/bfin_twi.h

reviewed

··· 1 1 /* 2 2 * bfin_twi.h - interface to Blackfin TWIs 3 3 * 4 4 - * Copyright 2005-2010 Analog Devices Inc. 4 4 + * Copyright 2005-2014 Analog Devices Inc. 5 5 * 6 6 * Licensed under the GPL-2 or later. 7 7 */ ··· 10 10 #define __ASM_BFIN_TWI_H__ 11 11 12 12 #include <asm/blackfin.h> 13 13 + #include <linux/types.h> 14 14 + #include <linux/i2c.h> 15 15 + 16 16 + /* 17 17 + * ADI twi registers layout 18 18 + */ 19 19 + struct bfin_twi_regs { 20 20 + u16 clkdiv; 21 21 + u16 dummy1; 22 22 + u16 control; 23 23 + u16 dummy2; 24 24 + u16 slave_ctl; 25 25 + u16 dummy3; 26 26 + u16 slave_stat; 27 27 + u16 dummy4; 28 28 + u16 slave_addr; 29 29 + u16 dummy5; 30 30 + u16 master_ctl; 31 31 + u16 dummy6; 32 32 + u16 master_stat; 33 33 + u16 dummy7; 34 34 + u16 master_addr; 35 35 + u16 dummy8; 36 36 + u16 int_stat; 37 37 + u16 dummy9; 38 38 + u16 int_mask; 39 39 + u16 dummy10; 40 40 + u16 fifo_ctl; 41 41 + u16 dummy11; 42 42 + u16 fifo_stat; 43 43 + u16 dummy12; 44 44 + u32 __pad[20]; 45 45 + u16 xmt_data8; 46 46 + u16 dummy13; 47 47 + u16 xmt_data16; 48 48 + u16 dummy14; 49 49 + u16 rcv_data8; 50 50 + u16 dummy15; 51 51 + u16 rcv_data16; 52 52 + u16 dummy16; 53 53 + }; 54 54 + 55 55 + struct bfin_twi_iface { 56 56 + int irq; 57 57 + spinlock_t lock; 58 58 + char read_write; 59 59 + u8 command; 60 60 + u8 *transPtr; 61 61 + int readNum; 62 62 + int writeNum; 63 63 + int cur_mode; 64 64 + int manual_stop; 65 65 + int result; 66 66 + struct i2c_adapter adap; 67 67 + struct completion complete; 68 68 + struct i2c_msg *pmsg; 69 69 + int msg_num; 70 70 + int cur_msg; 71 71 + u16 saved_clkdiv; 72 72 + u16 saved_control; 73 73 + struct bfin_twi_regs __iomem *regs_base; 74 74 + }; 75 75 + 76 76 + /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/ 77 77 + /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 78 78 + #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ 79 79 + #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 80 80 + 81 81 + /* TWI_PRESCALE Masks */ 82 82 + #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ 83 83 + #define TWI_ENA 0x0080 /* TWI Enable */ 84 84 + #define SCCB 0x0200 /* SCCB Compatibility Enable */ 85 85 + 86 86 + /* TWI_SLAVE_CTL Masks */ 87 87 + #define SEN 0x0001 /* Slave Enable */ 88 88 + #define SADD_LEN 0x0002 /* Slave Address Length */ 89 89 + #define STDVAL 0x0004 /* Slave Transmit Data Valid */ 90 90 + #define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */ 91 91 + #define GEN 0x0010 /* General Call Address Matching Enabled */ 92 92 + 93 93 + /* TWI_SLAVE_STAT Masks */ 94 94 + #define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */ 95 95 + #define GCALL 0x0002 /* General Call Indicator */ 96 96 + 97 97 + /* TWI_MASTER_CTL Masks */ 98 98 + #define MEN 0x0001 /* Master Mode Enable */ 99 99 + #define MADD_LEN 0x0002 /* Master Address Length */ 100 100 + #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 101 101 + #define FAST 0x0008 /* Use Fast Mode Timing Specs */ 102 102 + #define STOP 0x0010 /* Issue Stop Condition */ 103 103 + #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ 104 104 + #define DCNT 0x3FC0 /* Data Bytes To Transfer */ 105 105 + #define SDAOVR 0x4000 /* Serial Data Override */ 106 106 + #define SCLOVR 0x8000 /* Serial Clock Override */ 107 107 + 108 108 + /* TWI_MASTER_STAT Masks */ 109 109 + #define MPROG 0x0001 /* Master Transfer In Progress */ 110 110 + #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ 111 111 + #define ANAK 0x0004 /* Address Not Acknowledged */ 112 112 + #define DNAK 0x0008 /* Data Not Acknowledged */ 113 113 + #define BUFRDERR 0x0010 /* Buffer Read Error */ 114 114 + #define BUFWRERR 0x0020 /* Buffer Write Error */ 115 115 + #define SDASEN 0x0040 /* Serial Data Sense */ 116 116 + #define SCLSEN 0x0080 /* Serial Clock Sense */ 117 117 + #define BUSBUSY 0x0100 /* Bus Busy Indicator */ 118 118 + 119 119 + /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ 120 120 + #define SINIT 0x0001 /* Slave Transfer Initiated */ 121 121 + #define SCOMP 0x0002 /* Slave Transfer Complete */ 122 122 + #define SERR 0x0004 /* Slave Transfer Error */ 123 123 + #define SOVF 0x0008 /* Slave Overflow */ 124 124 + #define MCOMP 0x0010 /* Master Transfer Complete */ 125 125 + #define MERR 0x0020 /* Master Transfer Error */ 126 126 + #define XMTSERV 0x0040 /* Transmit FIFO Service */ 127 127 + #define RCVSERV 0x0080 /* Receive FIFO Service */ 128 128 + 129 129 + /* TWI_FIFO_CTRL Masks */ 130 130 + #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 131 131 + #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 132 132 + #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 133 133 + #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ 134 134 + 135 135 + /* TWI_FIFO_STAT Masks */ 136 136 + #define XMTSTAT 0x0003 /* Transmit FIFO Status */ 137 137 + #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ 138 138 + #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ 139 139 + #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ 140 140 + 141 141 + #define RCVSTAT 0x000C /* Receive FIFO Status */ 142 142 + #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 143 143 + #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 144 144 + #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 13 145 14 146 #define DEFINE_TWI_REG(reg_name, reg) \ 15 147 static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \

-1

arch/blackfin/kernel/debug-mmrs.c

reviewed

··· 10 10 #include <linux/fs.h> 11 11 #include <linux/kernel.h> 12 12 #include <linux/module.h> 13 13 - #include <linux/i2c/bfin_twi.h> 14 13 #include <linux/gpio.h> 15 14 16 15 #include <asm/blackfin.h>

+1 -1

arch/x86/platform/intel-mid/device_libs/platform_tc35876x.c

reviewed

··· 11 11 */ 12 12 13 13 #include <linux/gpio.h> 14 14 - #include <linux/i2c/tc35876x.h> 14 14 + #include <linux/platform_data/tc35876x.h> 15 15 #include <asm/intel-mid.h> 16 16 17 17 /*tc35876x DSI_LVDS bridge chip and panel platform data*/

+1 -1

drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c

reviewed

··· 26 26 #include "mdfld_output.h" 27 27 #include "mdfld_dsi_pkg_sender.h" 28 28 #include "tc35876x-dsi-lvds.h" 29 29 - #include <linux/i2c/tc35876x.h> 29 29 + #include <linux/platform_data/tc35876x.h> 30 30 #include <linux/kernel.h> 31 31 #include <linux/module.h> 32 32 #include <asm/intel_scu_ipc.h>

+15

drivers/i2c/busses/Kconfig

reviewed

··· 189 189 This driver can also be built as a module. If so, the module 190 190 will be called i2c-piix4. 191 191 192 192 + config I2C_CHT_WC 193 193 + tristate "Intel Cherry Trail Whiskey Cove PMIC smbus controller" 194 194 + depends on INTEL_SOC_PMIC_CHTWC 195 195 + help 196 196 + If you say yes to this option, support will be included for the 197 197 + SMBus controller found in the Intel Cherry Trail Whiskey Cove PMIC 198 198 + found on some Intel Cherry Trail systems. 199 199 + 192 200 config I2C_NFORCE2 193 201 tristate "Nvidia nForce2, nForce3 and nForce4" 194 202 depends on PCI ··· 907 899 908 900 This driver can also be built as a module. If so, the module 909 901 will be called i2c-sirf. 902 902 + 903 903 + config I2C_SPRD 904 904 + bool "Spreadtrum I2C interface" 905 905 + depends on I2C=y && ARCH_SPRD 906 906 + help 907 907 + If you say yes to this option, support will be included for the 908 908 + Spreadtrum I2C interface. 910 909 911 910 config I2C_ST 912 911 tristate "STMicroelectronics SSC I2C support"

+2

drivers/i2c/busses/Makefile

reviewed

··· 12 12 obj-$(CONFIG_I2C_AMD756) += i2c-amd756.o 13 13 obj-$(CONFIG_I2C_AMD756_S4882) += i2c-amd756-s4882.o 14 14 obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o 15 15 + obj-$(CONFIG_I2C_CHT_WC) += i2c-cht-wc.o 15 16 obj-$(CONFIG_I2C_I801) += i2c-i801.o 16 17 obj-$(CONFIG_I2C_ISCH) += i2c-isch.o 17 18 obj-$(CONFIG_I2C_ISMT) += i2c-ismt.o ··· 90 89 obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o 91 90 obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o 92 91 obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o 92 92 + obj-$(CONFIG_I2C_SPRD) += i2c-sprd.o 93 93 obj-$(CONFIG_I2C_ST) += i2c-st.o 94 94 obj-$(CONFIG_I2C_STM32F4) += i2c-stm32f4.o 95 95 obj-$(CONFIG_I2C_STU300) += i2c-stu300.o

+63 -18

drivers/i2c/busses/i2c-aspeed.c

reviewed

··· 53 53 #define ASPEED_I2CD_MASTER_EN BIT(0) 54 54 55 55 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */ 56 56 + #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28) 57 57 + #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24) 58 58 + #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20) 56 59 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16 57 60 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16) 58 61 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12 ··· 135 132 /* Synchronizes I/O mem access to base. */ 136 133 spinlock_t lock; 137 134 struct completion cmd_complete; 135 135 + u32 (*get_clk_reg_val)(u32 divisor); 138 136 unsigned long parent_clk_frequency; 139 137 u32 bus_frequency; 140 138 /* Transaction state. */ ··· 679 675 #endif /* CONFIG_I2C_SLAVE */ 680 676 }; 681 677 682 682 - static u32 aspeed_i2c_get_clk_reg_val(u32 divisor) 678 678 + static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor) 683 679 { 684 680 u32 base_clk, clk_high, clk_low, tmp; 685 681 ··· 699 695 * Thus, 700 696 * SCL_freq = APB_freq / 701 697 * ((1 << base_clk) * (clk_high + 1 + clk_low + 1)) 702 702 - * The documentation recommends clk_high >= 8 and clk_low >= 7 when 703 703 - * possible; this last constraint gives us the following solution: 698 698 + * The documentation recommends clk_high >= clk_high_max / 2 and 699 699 + * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint 700 700 + * gives us the following solution: 704 701 */ 705 705 - base_clk = divisor > 33 ? ilog2((divisor - 1) / 32) + 1 : 0; 706 706 - tmp = divisor / (1 << base_clk); 707 707 - clk_high = tmp / 2 + tmp % 2; 708 708 - clk_low = tmp - clk_high; 702 702 + base_clk = divisor > clk_high_low_max ? 703 703 + ilog2((divisor - 1) / clk_high_low_max) + 1 : 0; 704 704 + tmp = (divisor + (1 << base_clk) - 1) >> base_clk; 705 705 + clk_low = tmp / 2; 706 706 + clk_high = tmp - clk_low; 709 707 710 710 - clk_high -= 1; 711 711 - clk_low -= 1; 708 708 + if (clk_high) 709 709 + clk_high--; 710 710 + 711 711 + if (clk_low) 712 712 + clk_low--; 713 713 + 712 714 713 715 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT) 714 716 & ASPEED_I2CD_TIME_SCL_HIGH_MASK) ··· 723 713 | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK); 724 714 } 725 715 716 716 + static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor) 717 717 + { 718 718 + /* 719 719 + * clk_high and clk_low are each 3 bits wide, so each can hold a max 720 720 + * value of 8 giving a clk_high_low_max of 16. 721 721 + */ 722 722 + return aspeed_i2c_get_clk_reg_val(16, divisor); 723 723 + } 724 724 + 725 725 + static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor) 726 726 + { 727 727 + /* 728 728 + * clk_high and clk_low are each 4 bits wide, so each can hold a max 729 729 + * value of 16 giving a clk_high_low_max of 32. 730 730 + */ 731 731 + return aspeed_i2c_get_clk_reg_val(32, divisor); 732 732 + } 733 733 + 726 734 /* precondition: bus.lock has been acquired. */ 727 735 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) 728 736 { 729 737 u32 divisor, clk_reg_val; 730 738 731 731 - divisor = bus->parent_clk_frequency / bus->bus_frequency; 732 732 - clk_reg_val = aspeed_i2c_get_clk_reg_val(divisor); 739 739 + divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency); 740 740 + clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1); 741 741 + clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK | 742 742 + ASPEED_I2CD_TIME_THDSTA_MASK | 743 743 + ASPEED_I2CD_TIME_TACST_MASK); 744 744 + clk_reg_val |= bus->get_clk_reg_val(divisor); 733 745 writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); 734 746 writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); 735 747 ··· 810 778 return ret; 811 779 } 812 780 781 781 + static const struct of_device_id aspeed_i2c_bus_of_table[] = { 782 782 + { 783 783 + .compatible = "aspeed,ast2400-i2c-bus", 784 784 + .data = aspeed_i2c_24xx_get_clk_reg_val, 785 785 + }, 786 786 + { 787 787 + .compatible = "aspeed,ast2500-i2c-bus", 788 788 + .data = aspeed_i2c_25xx_get_clk_reg_val, 789 789 + }, 790 790 + { }, 791 791 + }; 792 792 + MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table); 793 793 + 813 794 static int aspeed_i2c_probe_bus(struct platform_device *pdev) 814 795 { 796 796 + const struct of_device_id *match; 815 797 struct aspeed_i2c_bus *bus; 816 798 struct clk *parent_clk; 817 799 struct resource *res; ··· 854 808 "Could not read bus-frequency property\n"); 855 809 bus->bus_frequency = 100000; 856 810 } 811 811 + 812 812 + match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node); 813 813 + if (!match) 814 814 + bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val; 815 815 + else 816 816 + bus->get_clk_reg_val = match->data; 857 817 858 818 /* Initialize the I2C adapter */ 859 819 spin_lock_init(&bus->lock); ··· 921 869 922 870 return 0; 923 871 } 924 924 - 925 925 - static const struct of_device_id aspeed_i2c_bus_of_table[] = { 926 926 - { .compatible = "aspeed,ast2400-i2c-bus", }, 927 927 - { .compatible = "aspeed,ast2500-i2c-bus", }, 928 928 - { }, 929 929 - }; 930 930 - MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table); 931 872 932 873 static struct platform_driver aspeed_i2c_bus_driver = { 933 874 .probe = aspeed_i2c_probe_bus,

+1 -1

drivers/i2c/busses/i2c-at91.c

reviewed

··· 809 809 * The hardware can handle at most two messages concatenated by a 810 810 * repeated start via it's internal address feature. 811 811 */ 812 812 - static struct i2c_adapter_quirks at91_twi_quirks = { 812 812 + static const struct i2c_adapter_quirks at91_twi_quirks = { 813 813 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR, 814 814 .max_comb_1st_msg_len = 3, 815 815 };

+2 -4

drivers/i2c/busses/i2c-bcm-iproc.c

reviewed

··· 510 510 511 511 static int bcm_iproc_i2c_suspend(struct device *dev) 512 512 { 513 513 - struct platform_device *pdev = to_platform_device(dev); 514 514 - struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); 513 513 + struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 515 514 516 515 /* make sure there's no pending interrupt when we go into suspend */ 517 516 writel(0, iproc_i2c->base + IE_OFFSET); ··· 525 526 526 527 static int bcm_iproc_i2c_resume(struct device *dev) 527 528 { 528 528 - struct platform_device *pdev = to_platform_device(dev); 529 529 - struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); 529 529 + struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 530 530 int ret; 531 531 u32 val; 532 532

-1

drivers/i2c/busses/i2c-bfin-twi.c

reviewed

··· 21 21 #include <linux/interrupt.h> 22 22 #include <linux/platform_device.h> 23 23 #include <linux/delay.h> 24 24 - #include <linux/i2c/bfin_twi.h> 25 24 26 25 #include <asm/irq.h> 27 26 #include <asm/portmux.h>

+2 -4

drivers/i2c/busses/i2c-cadence.c

reviewed

··· 826 826 */ 827 827 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) 828 828 { 829 829 - struct platform_device *pdev = to_platform_device(dev); 830 830 - struct cdns_i2c *xi2c = platform_get_drvdata(pdev); 829 829 + struct cdns_i2c *xi2c = dev_get_drvdata(dev); 831 830 832 831 clk_disable(xi2c->clk); 833 832 ··· 843 844 */ 844 845 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) 845 846 { 846 846 - struct platform_device *pdev = to_platform_device(dev); 847 847 - struct cdns_i2c *xi2c = platform_get_drvdata(pdev); 847 847 + struct cdns_i2c *xi2c = dev_get_drvdata(dev); 848 848 int ret; 849 849 850 850 ret = clk_enable(xi2c->clk);

+363

drivers/i2c/busses/i2c-cht-wc.c

reviewed

··· 1 1 + /* 2 2 + * Intel CHT Whiskey Cove PMIC I2C Master driver 3 3 + * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com> 4 4 + * 5 5 + * Based on various non upstream patches to support the CHT Whiskey Cove PMIC: 6 6 + * Copyright (C) 2011 - 2014 Intel Corporation. All rights reserved. 7 7 + * 8 8 + * This program is free software; you can redistribute it and/or 9 9 + * modify it under the terms of the GNU General Public License version 10 10 + * 2 as published by the Free Software Foundation, or (at your option) 11 11 + * any later version. 12 12 + * 13 13 + * This program is distributed in the hope that it will be useful, 14 14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 16 + * GNU General Public License for more details. 17 17 + */ 18 18 + 19 19 + #include <linux/completion.h> 20 20 + #include <linux/delay.h> 21 21 + #include <linux/i2c.h> 22 22 + #include <linux/interrupt.h> 23 23 + #include <linux/irq.h> 24 24 + #include <linux/irqdomain.h> 25 25 + #include <linux/mfd/intel_soc_pmic.h> 26 26 + #include <linux/module.h> 27 27 + #include <linux/platform_device.h> 28 28 + #include <linux/slab.h> 29 29 + 30 30 + #define CHT_WC_I2C_CTRL 0x5e24 31 31 + #define CHT_WC_I2C_CTRL_WR BIT(0) 32 32 + #define CHT_WC_I2C_CTRL_RD BIT(1) 33 33 + #define CHT_WC_I2C_CLIENT_ADDR 0x5e25 34 34 + #define CHT_WC_I2C_REG_OFFSET 0x5e26 35 35 + #define CHT_WC_I2C_WRDATA 0x5e27 36 36 + #define CHT_WC_I2C_RDDATA 0x5e28 37 37 + 38 38 + #define CHT_WC_EXTCHGRIRQ 0x6e0a 39 39 + #define CHT_WC_EXTCHGRIRQ_CLIENT_IRQ BIT(0) 40 40 + #define CHT_WC_EXTCHGRIRQ_WRITE_IRQ BIT(1) 41 41 + #define CHT_WC_EXTCHGRIRQ_READ_IRQ BIT(2) 42 42 + #define CHT_WC_EXTCHGRIRQ_NACK_IRQ BIT(3) 43 43 + #define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK ((u8)GENMASK(3, 1)) 44 44 + #define CHT_WC_EXTCHGRIRQ_MSK 0x6e17 45 45 + 46 46 + struct cht_wc_i2c_adap { 47 47 + struct i2c_adapter adapter; 48 48 + wait_queue_head_t wait; 49 49 + struct irq_chip irqchip; 50 50 + struct mutex adap_lock; 51 51 + struct mutex irqchip_lock; 52 52 + struct regmap *regmap; 53 53 + struct irq_domain *irq_domain; 54 54 + struct i2c_client *client; 55 55 + int client_irq; 56 56 + u8 irq_mask; 57 57 + u8 old_irq_mask; 58 58 + int read_data; 59 59 + bool io_error; 60 60 + bool done; 61 61 + }; 62 62 + 63 63 + static irqreturn_t cht_wc_i2c_adap_thread_handler(int id, void *data) 64 64 + { 65 65 + struct cht_wc_i2c_adap *adap = data; 66 66 + int ret, reg; 67 67 + 68 68 + mutex_lock(&adap->adap_lock); 69 69 + 70 70 + /* Read IRQs */ 71 71 + ret = regmap_read(adap->regmap, CHT_WC_EXTCHGRIRQ, &reg); 72 72 + if (ret) { 73 73 + dev_err(&adap->adapter.dev, "Error reading extchgrirq reg\n"); 74 74 + mutex_unlock(&adap->adap_lock); 75 75 + return IRQ_NONE; 76 76 + } 77 77 + 78 78 + reg &= ~adap->irq_mask; 79 79 + 80 80 + /* Reads must be acked after reading the received data. */ 81 81 + ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, &adap->read_data); 82 82 + if (ret) 83 83 + adap->io_error = true; 84 84 + 85 85 + /* 86 86 + * Immediately ack IRQs, so that if new IRQs arrives while we're 87 87 + * handling the previous ones our irq will re-trigger when we're done. 88 88 + */ 89 89 + ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, reg); 90 90 + if (ret) 91 91 + dev_err(&adap->adapter.dev, "Error writing extchgrirq reg\n"); 92 92 + 93 93 + if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) { 94 94 + adap->io_error |= !!(reg & CHT_WC_EXTCHGRIRQ_NACK_IRQ); 95 95 + adap->done = true; 96 96 + } 97 97 + 98 98 + mutex_unlock(&adap->adap_lock); 99 99 + 100 100 + if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) 101 101 + wake_up(&adap->wait); 102 102 + 103 103 + /* 104 104 + * Do NOT use handle_nested_irq here, the client irq handler will 105 105 + * likely want to do i2c transfers and the i2c controller uses this 106 106 + * interrupt handler as well, so running the client irq handler from 107 107 + * this thread will cause things to lock up. 108 108 + */ 109 109 + if (reg & CHT_WC_EXTCHGRIRQ_CLIENT_IRQ) { 110 110 + /* 111 111 + * generic_handle_irq expects local IRQs to be disabled 112 112 + * as normally it is called from interrupt context. 113 113 + */ 114 114 + local_irq_disable(); 115 115 + generic_handle_irq(adap->client_irq); 116 116 + local_irq_enable(); 117 117 + } 118 118 + 119 119 + return IRQ_HANDLED; 120 120 + } 121 121 + 122 122 + static u32 cht_wc_i2c_adap_master_func(struct i2c_adapter *adap) 123 123 + { 124 124 + /* This i2c adapter only supports SMBUS byte transfers */ 125 125 + return I2C_FUNC_SMBUS_BYTE_DATA; 126 126 + } 127 127 + 128 128 + static int cht_wc_i2c_adap_smbus_xfer(struct i2c_adapter *_adap, u16 addr, 129 129 + unsigned short flags, char read_write, 130 130 + u8 command, int size, 131 131 + union i2c_smbus_data *data) 132 132 + { 133 133 + struct cht_wc_i2c_adap *adap = i2c_get_adapdata(_adap); 134 134 + int ret; 135 135 + 136 136 + mutex_lock(&adap->adap_lock); 137 137 + adap->io_error = false; 138 138 + adap->done = false; 139 139 + mutex_unlock(&adap->adap_lock); 140 140 + 141 141 + ret = regmap_write(adap->regmap, CHT_WC_I2C_CLIENT_ADDR, addr); 142 142 + if (ret) 143 143 + return ret; 144 144 + 145 145 + if (read_write == I2C_SMBUS_WRITE) { 146 146 + ret = regmap_write(adap->regmap, CHT_WC_I2C_WRDATA, data->byte); 147 147 + if (ret) 148 148 + return ret; 149 149 + } 150 150 + 151 151 + ret = regmap_write(adap->regmap, CHT_WC_I2C_REG_OFFSET, command); 152 152 + if (ret) 153 153 + return ret; 154 154 + 155 155 + ret = regmap_write(adap->regmap, CHT_WC_I2C_CTRL, 156 156 + (read_write == I2C_SMBUS_WRITE) ? 157 157 + CHT_WC_I2C_CTRL_WR : CHT_WC_I2C_CTRL_RD); 158 158 + if (ret) 159 159 + return ret; 160 160 + 161 161 + ret = wait_event_timeout(adap->wait, adap->done, msecs_to_jiffies(30)); 162 162 + if (ret == 0) { 163 163 + /* 164 164 + * The CHT GPIO controller serializes all IRQs, sometimes 165 165 + * causing significant delays, check status manually. 166 166 + */ 167 167 + cht_wc_i2c_adap_thread_handler(0, adap); 168 168 + if (!adap->done) 169 169 + return -ETIMEDOUT; 170 170 + } 171 171 + 172 172 + ret = 0; 173 173 + mutex_lock(&adap->adap_lock); 174 174 + if (adap->io_error) 175 175 + ret = -EIO; 176 176 + else if (read_write == I2C_SMBUS_READ) 177 177 + data->byte = adap->read_data; 178 178 + mutex_unlock(&adap->adap_lock); 179 179 + 180 180 + return ret; 181 181 + } 182 182 + 183 183 + static const struct i2c_algorithm cht_wc_i2c_adap_algo = { 184 184 + .functionality = cht_wc_i2c_adap_master_func, 185 185 + .smbus_xfer = cht_wc_i2c_adap_smbus_xfer, 186 186 + }; 187 187 + 188 188 + /**** irqchip for the client connected to the extchgr i2c adapter ****/ 189 189 + static void cht_wc_i2c_irq_lock(struct irq_data *data) 190 190 + { 191 191 + struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 192 192 + 193 193 + mutex_lock(&adap->irqchip_lock); 194 194 + } 195 195 + 196 196 + static void cht_wc_i2c_irq_sync_unlock(struct irq_data *data) 197 197 + { 198 198 + struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 199 199 + int ret; 200 200 + 201 201 + if (adap->irq_mask != adap->old_irq_mask) { 202 202 + ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, 203 203 + adap->irq_mask); 204 204 + if (ret == 0) 205 205 + adap->old_irq_mask = adap->irq_mask; 206 206 + else 207 207 + dev_err(&adap->adapter.dev, "Error writing EXTCHGRIRQ_MSK\n"); 208 208 + } 209 209 + 210 210 + mutex_unlock(&adap->irqchip_lock); 211 211 + } 212 212 + 213 213 + static void cht_wc_i2c_irq_enable(struct irq_data *data) 214 214 + { 215 215 + struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 216 216 + 217 217 + adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; 218 218 + } 219 219 + 220 220 + static void cht_wc_i2c_irq_disable(struct irq_data *data) 221 221 + { 222 222 + struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 223 223 + 224 224 + adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; 225 225 + } 226 226 + 227 227 + static const struct irq_chip cht_wc_i2c_irq_chip = { 228 228 + .irq_bus_lock = cht_wc_i2c_irq_lock, 229 229 + .irq_bus_sync_unlock = cht_wc_i2c_irq_sync_unlock, 230 230 + .irq_disable = cht_wc_i2c_irq_disable, 231 231 + .irq_enable = cht_wc_i2c_irq_enable, 232 232 + .name = "cht_wc_ext_chrg_irq_chip", 233 233 + }; 234 234 + 235 235 + static const struct property_entry bq24190_props[] = { 236 236 + PROPERTY_ENTRY_STRING("extcon-name", "cht_wcove_pwrsrc"), 237 237 + PROPERTY_ENTRY_BOOL("omit-battery-class"), 238 238 + PROPERTY_ENTRY_BOOL("disable-reset"), 239 239 + { } 240 240 + }; 241 241 + 242 242 + static int cht_wc_i2c_adap_i2c_probe(struct platform_device *pdev) 243 243 + { 244 244 + struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent); 245 245 + struct cht_wc_i2c_adap *adap; 246 246 + struct i2c_board_info board_info = { 247 247 + .type = "bq24190", 248 248 + .addr = 0x6b, 249 249 + .properties = bq24190_props, 250 250 + }; 251 251 + int ret, reg, irq; 252 252 + 253 253 + irq = platform_get_irq(pdev, 0); 254 254 + if (irq < 0) { 255 255 + dev_err(&pdev->dev, "Error missing irq resource\n"); 256 256 + return -EINVAL; 257 257 + } 258 258 + 259 259 + adap = devm_kzalloc(&pdev->dev, sizeof(*adap), GFP_KERNEL); 260 260 + if (!adap) 261 261 + return -ENOMEM; 262 262 + 263 263 + init_waitqueue_head(&adap->wait); 264 264 + mutex_init(&adap->adap_lock); 265 265 + mutex_init(&adap->irqchip_lock); 266 266 + adap->irqchip = cht_wc_i2c_irq_chip; 267 267 + adap->regmap = pmic->regmap; 268 268 + adap->adapter.owner = THIS_MODULE; 269 269 + adap->adapter.class = I2C_CLASS_HWMON; 270 270 + adap->adapter.algo = &cht_wc_i2c_adap_algo; 271 271 + strlcpy(adap->adapter.name, "PMIC I2C Adapter", 272 272 + sizeof(adap->adapter.name)); 273 273 + adap->adapter.dev.parent = &pdev->dev; 274 274 + 275 275 + /* Clear and activate i2c-adapter interrupts, disable client IRQ */ 276 276 + adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK; 277 277 + 278 278 + ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, &reg); 279 279 + if (ret) 280 280 + return ret; 281 281 + 282 282 + ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask); 283 283 + if (ret) 284 284 + return ret; 285 285 + 286 286 + ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask); 287 287 + if (ret) 288 288 + return ret; 289 289 + 290 290 + /* Alloc and register client IRQ */ 291 291 + adap->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 1, 292 292 + &irq_domain_simple_ops, NULL); 293 293 + if (!adap->irq_domain) 294 294 + return -ENOMEM; 295 295 + 296 296 + adap->client_irq = irq_create_mapping(adap->irq_domain, 0); 297 297 + if (!adap->client_irq) { 298 298 + ret = -ENOMEM; 299 299 + goto remove_irq_domain; 300 300 + } 301 301 + 302 302 + irq_set_chip_data(adap->client_irq, adap); 303 303 + irq_set_chip_and_handler(adap->client_irq, &adap->irqchip, 304 304 + handle_simple_irq); 305 305 + 306 306 + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 307 307 + cht_wc_i2c_adap_thread_handler, 308 308 + IRQF_ONESHOT, "PMIC I2C Adapter", adap); 309 309 + if (ret) 310 310 + goto remove_irq_domain; 311 311 + 312 312 + i2c_set_adapdata(&adap->adapter, adap); 313 313 + ret = i2c_add_adapter(&adap->adapter); 314 314 + if (ret) 315 315 + goto remove_irq_domain; 316 316 + 317 317 + board_info.irq = adap->client_irq; 318 318 + adap->client = i2c_new_device(&adap->adapter, &board_info); 319 319 + if (!adap->client) { 320 320 + ret = -ENOMEM; 321 321 + goto del_adapter; 322 322 + } 323 323 + 324 324 + platform_set_drvdata(pdev, adap); 325 325 + return 0; 326 326 + 327 327 + del_adapter: 328 328 + i2c_del_adapter(&adap->adapter); 329 329 + remove_irq_domain: 330 330 + irq_domain_remove(adap->irq_domain); 331 331 + return ret; 332 332 + } 333 333 + 334 334 + static int cht_wc_i2c_adap_i2c_remove(struct platform_device *pdev) 335 335 + { 336 336 + struct cht_wc_i2c_adap *adap = platform_get_drvdata(pdev); 337 337 + 338 338 + i2c_unregister_device(adap->client); 339 339 + i2c_del_adapter(&adap->adapter); 340 340 + irq_domain_remove(adap->irq_domain); 341 341 + 342 342 + return 0; 343 343 + } 344 344 + 345 345 + static struct platform_device_id cht_wc_i2c_adap_id_table[] = { 346 346 + { .name = "cht_wcove_ext_chgr" }, 347 347 + {}, 348 348 + }; 349 349 + MODULE_DEVICE_TABLE(platform, cht_wc_i2c_adap_id_table); 350 350 + 351 351 + static struct platform_driver cht_wc_i2c_adap_driver = { 352 352 + .probe = cht_wc_i2c_adap_i2c_probe, 353 353 + .remove = cht_wc_i2c_adap_i2c_remove, 354 354 + .driver = { 355 355 + .name = "cht_wcove_ext_chgr", 356 356 + }, 357 357 + .id_table = cht_wc_i2c_adap_id_table, 358 358 + }; 359 359 + module_platform_driver(cht_wc_i2c_adap_driver); 360 360 + 361 361 + MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC I2C Master driver"); 362 362 + MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 363 363 + MODULE_LICENSE("GPL");

+1 -1

drivers/i2c/busses/i2c-cpm.c

reviewed

··· 413 413 }; 414 414 415 415 /* CPM_MAX_READ is also limiting writes according to the code! */ 416 416 - static struct i2c_adapter_quirks cpm_i2c_quirks = { 416 416 + static const struct i2c_adapter_quirks cpm_i2c_quirks = { 417 417 .max_num_msgs = CPM_MAXBD, 418 418 .max_read_len = CPM_MAX_READ, 419 419 .max_write_len = CPM_MAX_READ,

+4 -6

drivers/i2c/busses/i2c-davinci.c

reviewed

··· 733 733 } 734 734 #endif 735 735 736 736 - static struct i2c_algorithm i2c_davinci_algo = { 736 736 + static const struct i2c_algorithm i2c_davinci_algo = { 737 737 .master_xfer = i2c_davinci_xfer, 738 738 .functionality = i2c_davinci_func, 739 739 }; ··· 801 801 802 802 dev->clk = devm_clk_get(&pdev->dev, NULL); 803 803 if (IS_ERR(dev->clk)) 804 804 - return -ENODEV; 804 804 + return PTR_ERR(dev->clk); 805 805 clk_prepare_enable(dev->clk); 806 806 807 807 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ··· 876 876 #ifdef CONFIG_PM 877 877 static int davinci_i2c_suspend(struct device *dev) 878 878 { 879 879 - struct platform_device *pdev = to_platform_device(dev); 880 880 - struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 879 879 + struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev); 881 880 882 881 /* put I2C into reset */ 883 882 davinci_i2c_reset_ctrl(i2c_dev, 0); ··· 887 888 888 889 static int davinci_i2c_resume(struct device *dev) 889 890 { 890 890 - struct platform_device *pdev = to_platform_device(dev); 891 891 - struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 891 891 + struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev); 892 892 893 893 clk_prepare_enable(i2c_dev->clk); 894 894 /* take I2C out of reset */

+2 -4

drivers/i2c/busses/i2c-designware-platdrv.c

reviewed

··· 439 439 #ifdef CONFIG_PM 440 440 static int dw_i2c_plat_runtime_suspend(struct device *dev) 441 441 { 442 442 - struct platform_device *pdev = to_platform_device(dev); 443 443 - struct dw_i2c_dev *i_dev = platform_get_drvdata(pdev); 442 442 + struct dw_i2c_dev *i_dev = dev_get_drvdata(dev); 444 443 445 444 i_dev->disable(i_dev); 446 445 i2c_dw_plat_prepare_clk(i_dev, false); ··· 449 450 450 451 static int dw_i2c_plat_resume(struct device *dev) 451 452 { 452 452 - struct platform_device *pdev = to_platform_device(dev); 453 453 - struct dw_i2c_dev *i_dev = platform_get_drvdata(pdev); 453 453 + struct dw_i2c_dev *i_dev = dev_get_drvdata(dev); 454 454 455 455 i2c_dw_plat_prepare_clk(i_dev, true); 456 456 i_dev->init(i_dev);

+1 -1

drivers/i2c/busses/i2c-designware-slave.c

reviewed

··· 346 346 return IRQ_RETVAL(ret); 347 347 } 348 348 349 349 - static struct i2c_algorithm i2c_dw_algo = { 349 349 + static const struct i2c_algorithm i2c_dw_algo = { 350 350 .functionality = i2c_dw_func, 351 351 .reg_slave = i2c_dw_reg_slave, 352 352 .unreg_slave = i2c_dw_unreg_slave,

+2 -4

drivers/i2c/busses/i2c-exynos5.c

reviewed

··· 803 803 #ifdef CONFIG_PM_SLEEP 804 804 static int exynos5_i2c_suspend_noirq(struct device *dev) 805 805 { 806 806 - struct platform_device *pdev = to_platform_device(dev); 807 807 - struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 806 806 + struct exynos5_i2c *i2c = dev_get_drvdata(dev); 808 807 809 808 i2c->suspended = 1; 810 809 ··· 814 815 815 816 static int exynos5_i2c_resume_noirq(struct device *dev) 816 817 { 817 817 - struct platform_device *pdev = to_platform_device(dev); 818 818 - struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 818 818 + struct exynos5_i2c *i2c = dev_get_drvdata(dev); 819 819 int ret = 0; 820 820 821 821 ret = clk_prepare_enable(i2c->clk);

+2 -2

drivers/i2c/busses/i2c-gpio.c

reviewed

··· 98 98 return -EPROBE_DEFER; 99 99 100 100 if (!gpio_is_valid(*sda_pin) || !gpio_is_valid(*scl_pin)) { 101 101 - pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n", 102 102 - np->full_name, *sda_pin, *scl_pin); 101 101 + pr_err("%pOF: invalid GPIO pins, sda=%d/scl=%d\n", 102 102 + np, *sda_pin, *scl_pin); 103 103 return -ENODEV; 104 104 } 105 105

+2 -4

drivers/i2c/busses/i2c-hix5hd2.c

reviewed

··· 505 505 #ifdef CONFIG_PM 506 506 static int hix5hd2_i2c_runtime_suspend(struct device *dev) 507 507 { 508 508 - struct platform_device *pdev = to_platform_device(dev); 509 509 - struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 508 508 + struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev); 510 509 511 510 clk_disable_unprepare(priv->clk); 512 511 ··· 514 515 515 516 static int hix5hd2_i2c_runtime_resume(struct device *dev) 516 517 { 517 517 - struct platform_device *pdev = to_platform_device(dev); 518 518 - struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 518 518 + struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev); 519 519 520 520 clk_prepare_enable(priv->clk); 521 521 hix5hd2_i2c_init(priv);

+8 -4

drivers/i2c/busses/i2c-i801.c

reviewed

··· 1332 1332 u32 tco_base, tco_ctl; 1333 1333 u32 base_addr, ctrl_val; 1334 1334 u64 base64_addr; 1335 1335 + u8 hidden; 1335 1336 1336 1337 if (!(priv->features & FEATURE_TCO)) 1337 1338 return; ··· 1377 1376 1378 1377 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1379 1378 1380 1380 - /* Unhide the P2SB device */ 1381 1381 - pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1379 1379 + /* Unhide the P2SB device, if it is hidden */ 1380 1380 + pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1381 1381 + if (hidden) 1382 1382 + pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1382 1383 1383 1384 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1384 1385 base64_addr = base_addr & 0xfffffff0; ··· 1388 1385 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1389 1386 base64_addr |= (u64)base_addr << 32; 1390 1387 1391 1391 - /* Hide the P2SB device */ 1392 1392 - pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1); 1388 1388 + /* Hide the P2SB device, if it was hidden before */ 1389 1389 + if (hidden) 1390 1390 + pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1393 1391 spin_unlock(&p2sb_spinlock); 1394 1392 1395 1393 res = &tco_res[ICH_RES_MEM_OFF];

+1 -1

drivers/i2c/busses/i2c-kempld.c

reviewed

··· 289 289 .functionality = kempld_i2c_func, 290 290 }; 291 291 292 292 - static struct i2c_adapter kempld_i2c_adapter = { 292 292 + static const struct i2c_adapter kempld_i2c_adapter = { 293 293 .owner = THIS_MODULE, 294 294 .name = "i2c-kempld", 295 295 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,

+2 -4

drivers/i2c/busses/i2c-lpc2k.c

reviewed

··· 457 457 #ifdef CONFIG_PM 458 458 static int i2c_lpc2k_suspend(struct device *dev) 459 459 { 460 460 - struct platform_device *pdev = to_platform_device(dev); 461 461 - struct lpc2k_i2c *i2c = platform_get_drvdata(pdev); 460 460 + struct lpc2k_i2c *i2c = dev_get_drvdata(dev); 462 461 463 462 clk_disable(i2c->clk); 464 463 ··· 466 467 467 468 static int i2c_lpc2k_resume(struct device *dev) 468 469 { 469 469 - struct platform_device *pdev = to_platform_device(dev); 470 470 - struct lpc2k_i2c *i2c = platform_get_drvdata(pdev); 470 470 + struct lpc2k_i2c *i2c = dev_get_drvdata(dev); 471 471 472 472 clk_enable(i2c->clk); 473 473 i2c_lpc2k_reset(i2c);

+1 -1

drivers/i2c/busses/i2c-mlxcpld.c

reviewed

··· 433 433 .functionality = mlxcpld_i2c_func 434 434 }; 435 435 436 436 - static struct i2c_adapter_quirks mlxcpld_i2c_quirks = { 436 436 + static const struct i2c_adapter_quirks mlxcpld_i2c_quirks = { 437 437 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 438 438 .max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN, 439 439 .max_write_len = MLXCPLD_I2C_DATA_REG_SZ,

+60 -19

drivers/i2c/busses/i2c-mt65xx.c

reviewed

··· 50 50 #define I2C_FS_START_CON 0x1800 51 51 #define I2C_TIME_CLR_VALUE 0x0000 52 52 #define I2C_TIME_DEFAULT_VALUE 0x0003 53 53 - #define I2C_FS_TIME_INIT_VALUE 0x1303 54 53 #define I2C_WRRD_TRANAC_VALUE 0x0002 55 54 #define I2C_RD_TRANAC_VALUE 0x0001 56 55 ··· 153 154 bool use_push_pull; /* IO config push-pull mode */ 154 155 155 156 u16 irq_stat; /* interrupt status */ 157 157 + unsigned int clk_src_div; 156 158 unsigned int speed_hz; /* The speed in transfer */ 157 159 enum mtk_trans_op op; 158 160 u16 timing_reg; ··· 170 170 .max_read_len = 255, 171 171 .max_comb_1st_msg_len = 255, 172 172 .max_comb_2nd_msg_len = 31, 173 173 + }; 174 174 + 175 175 + static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 176 176 + .max_num_msgs = 255, 173 177 }; 174 178 175 179 static const struct mtk_i2c_compatible mt6577_compat = { ··· 194 190 .support_33bits = 0, 195 191 }; 196 192 193 193 + static const struct mtk_i2c_compatible mt7622_compat = { 194 194 + .quirks = &mt7622_i2c_quirks, 195 195 + .pmic_i2c = 0, 196 196 + .dcm = 1, 197 197 + .auto_restart = 1, 198 198 + .aux_len_reg = 1, 199 199 + .support_33bits = 0, 200 200 + }; 201 201 + 197 202 static const struct mtk_i2c_compatible mt8173_compat = { 198 203 .pmic_i2c = 0, 199 204 .dcm = 1, ··· 214 201 static const struct of_device_id mtk_i2c_of_match[] = { 215 202 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 216 203 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 204 204 + { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 217 205 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 218 206 {} 219 207 }; ··· 299 285 * less than or equal to i2c->speed_hz. The calculation try to get 300 286 * sample_cnt and step_cn 301 287 */ 302 302 - static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk, 303 303 - unsigned int clock_div) 288 288 + static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 289 289 + unsigned int target_speed, 290 290 + unsigned int *timing_step_cnt, 291 291 + unsigned int *timing_sample_cnt) 304 292 { 305 305 - unsigned int clk_src; 306 293 unsigned int step_cnt; 307 294 unsigned int sample_cnt; 308 295 unsigned int max_step_cnt; 309 309 - unsigned int target_speed; 310 296 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 311 297 unsigned int base_step_cnt; 312 298 unsigned int opt_div; 313 299 unsigned int best_mul; 314 300 unsigned int cnt_mul; 315 315 - 316 316 - clk_src = parent_clk / clock_div; 317 317 - target_speed = i2c->speed_hz; 318 301 319 302 if (target_speed > MAX_HS_MODE_SPEED) 320 303 target_speed = MAX_HS_MODE_SPEED; ··· 358 347 return -EINVAL; 359 348 } 360 349 361 361 - step_cnt--; 362 362 - sample_cnt--; 350 350 + *timing_step_cnt = step_cnt - 1; 351 351 + *timing_sample_cnt = sample_cnt - 1; 352 352 + 353 353 + return 0; 354 354 + } 355 355 + 356 356 + static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 357 357 + { 358 358 + unsigned int clk_src; 359 359 + unsigned int step_cnt; 360 360 + unsigned int sample_cnt; 361 361 + unsigned int target_speed; 362 362 + int ret; 363 363 + 364 364 + clk_src = parent_clk / i2c->clk_src_div; 365 365 + target_speed = i2c->speed_hz; 363 366 364 367 if (target_speed > MAX_FS_MODE_SPEED) { 368 368 + /* Set master code speed register */ 369 369 + ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED, 370 370 + &step_cnt, &sample_cnt); 371 371 + if (ret < 0) 372 372 + return ret; 373 373 + 374 374 + i2c->timing_reg = (sample_cnt << 8) | step_cnt; 375 375 + 365 376 /* Set the high speed mode register */ 366 366 - i2c->timing_reg = I2C_FS_TIME_INIT_VALUE; 377 377 + ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, 378 378 + &step_cnt, &sample_cnt); 379 379 + if (ret < 0) 380 380 + return ret; 381 381 + 367 382 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 368 383 (sample_cnt << 12) | (step_cnt << 8); 369 384 } else { 370 370 - i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0); 385 385 + ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, 386 386 + &step_cnt, &sample_cnt); 387 387 + if (ret < 0) 388 388 + return ret; 389 389 + 390 390 + i2c->timing_reg = (sample_cnt << 8) | step_cnt; 391 391 + 371 392 /* Disable the high speed transaction */ 372 393 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 373 394 } ··· 690 647 .functionality = mtk_i2c_functionality, 691 648 }; 692 649 693 693 - static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c, 694 694 - unsigned int *clk_src_div) 650 650 + static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 695 651 { 696 652 int ret; 697 653 ··· 698 656 if (ret < 0) 699 657 i2c->speed_hz = I2C_DEFAULT_SPEED; 700 658 701 701 - ret = of_property_read_u32(np, "clock-div", clk_src_div); 659 659 + ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 702 660 if (ret < 0) 703 661 return ret; 704 662 705 705 - if (*clk_src_div == 0) 663 663 + if (i2c->clk_src_div == 0) 706 664 return -EINVAL; 707 665 708 666 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); ··· 718 676 int ret = 0; 719 677 struct mtk_i2c *i2c; 720 678 struct clk *clk; 721 721 - unsigned int clk_src_div; 722 679 struct resource *res; 723 680 int irq; 724 681 ··· 725 684 if (!i2c) 726 685 return -ENOMEM; 727 686 728 728 - ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div); 687 687 + ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 729 688 if (ret) 730 689 return -EINVAL; 731 690 ··· 786 745 787 746 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 788 747 789 789 - ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div); 748 748 + ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 790 749 if (ret) { 791 750 dev_err(&pdev->dev, "Failed to set the speed.\n"); 792 751 return -EINVAL;

+2 -3

drivers/i2c/busses/i2c-mv64xxx.c

reviewed

··· 820 820 goto out; 821 821 } 822 822 823 823 - drv_data->rstc = devm_reset_control_get_optional(dev, NULL); 823 823 + drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL); 824 824 if (IS_ERR(drv_data->rstc)) { 825 825 rc = PTR_ERR(drv_data->rstc); 826 826 goto out; ··· 975 975 #ifdef CONFIG_PM 976 976 static int mv64xxx_i2c_resume(struct device *dev) 977 977 { 978 978 - struct platform_device *pdev = to_platform_device(dev); 979 979 - struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pdev); 978 978 + struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev); 980 979 981 980 mv64xxx_i2c_hw_init(drv_data); 982 981

+1 -1

drivers/i2c/busses/i2c-nomadik.c

reviewed

··· 1088 1088 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */ 1089 1089 }; 1090 1090 1091 1091 - static struct amba_id nmk_i2c_ids[] = { 1091 1091 + static const struct amba_id nmk_i2c_ids[] = { 1092 1092 { 1093 1093 .id = 0x00180024, 1094 1094 .mask = 0x00ffffff,

+1 -1

drivers/i2c/busses/i2c-ocores.c

reviewed

··· 276 276 .functionality = ocores_func, 277 277 }; 278 278 279 279 - static struct i2c_adapter ocores_adapter = { 279 279 + static const struct i2c_adapter ocores_adapter = { 280 280 .owner = THIS_MODULE, 281 281 .name = "i2c-ocores", 282 282 .class = I2C_CLASS_DEPRECATED,

+1 -1

drivers/i2c/busses/i2c-octeon-platdrv.c

reviewed

··· 126 126 .functionality = octeon_i2c_functionality, 127 127 }; 128 128 129 129 - static struct i2c_adapter octeon_i2c_ops = { 129 129 + static const struct i2c_adapter octeon_i2c_ops = { 130 130 .owner = THIS_MODULE, 131 131 .name = "OCTEON adapter", 132 132 .algo = &octeon_i2c_algo,

+1 -1

drivers/i2c/busses/i2c-opal.c

reviewed

··· 204 204 * For two messages, we basically support simple smbus transactions of a 205 205 * write-then-anything. 206 206 */ 207 207 - static struct i2c_adapter_quirks i2c_opal_quirks = { 207 207 + static const struct i2c_adapter_quirks i2c_opal_quirks = { 208 208 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR, 209 209 .max_comb_1st_msg_len = 4, 210 210 };

+2 -2

drivers/i2c/busses/i2c-pmcmsp.c

reviewed

··· 577 577 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL; 578 578 } 579 579 580 580 - static struct i2c_adapter_quirks pmcmsptwi_i2c_quirks = { 580 580 + static const struct i2c_adapter_quirks pmcmsptwi_i2c_quirks = { 581 581 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 582 582 .max_write_len = MSP_MAX_BYTES_PER_RW, 583 583 .max_read_len = MSP_MAX_BYTES_PER_RW, ··· 587 587 588 588 /* -- Initialization -- */ 589 589 590 590 - static struct i2c_algorithm pmcmsptwi_algo = { 590 590 + static const struct i2c_algorithm pmcmsptwi_algo = { 591 591 .master_xfer = pmcmsptwi_master_xfer, 592 592 .functionality = pmcmsptwi_i2c_func, 593 593 };

+1 -1

drivers/i2c/busses/i2c-pnx.c

reviewed

··· 590 590 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 591 591 } 592 592 593 593 - static struct i2c_algorithm pnx_algorithm = { 593 593 + static const struct i2c_algorithm pnx_algorithm = { 594 594 .master_xfer = i2c_pnx_xfer, 595 595 .functionality = i2c_pnx_func, 596 596 };

+5 -7

drivers/i2c/busses/i2c-powermac.c

reviewed

··· 197 197 .functionality = i2c_powermac_func, 198 198 }; 199 199 200 200 - static struct i2c_adapter_quirks i2c_powermac_quirks = { 200 200 + static const struct i2c_adapter_quirks i2c_powermac_quirks = { 201 201 .max_num_msgs = 1, 202 202 }; 203 203 ··· 234 234 else if (!strcmp(node->name, "deq")) 235 235 return 0x34; 236 236 237 237 - dev_warn(&adap->dev, "No i2c address for %s\n", node->full_name); 237 237 + dev_warn(&adap->dev, "No i2c address for %pOF\n", node); 238 238 239 239 return 0xffffffff; 240 240 } ··· 315 315 } 316 316 } 317 317 318 318 - dev_err(&adap->dev, "i2c-powermac: modalias failure" 319 319 - " on %s\n", node->full_name); 318 318 + dev_err(&adap->dev, "i2c-powermac: modalias failure on %pOF\n", node); 320 319 return false; 321 320 } 322 321 ··· 347 348 if (!pmac_i2c_match_adapter(node, adap)) 348 349 continue; 349 350 350 350 - dev_dbg(&adap->dev, "i2c-powermac: register %s\n", 351 351 - node->full_name); 351 351 + dev_dbg(&adap->dev, "i2c-powermac: register %pOF\n", node); 352 352 353 353 /* 354 354 * Keep track of some device existence to handle ··· 370 372 newdev = i2c_new_device(adap, &info); 371 373 if (!newdev) { 372 374 dev_err(&adap->dev, "i2c-powermac: Failure to register" 373 373 - " %s\n", node->full_name); 375 375 + " %pOF\n", node); 374 376 of_node_put(node); 375 377 /* We do not dispose of the interrupt mapping on 376 378 * purpose. It's not necessary (interrupt cannot be

+1 -1

drivers/i2c/busses/i2c-puv3.c

reviewed

··· 175 175 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 176 176 } 177 177 178 178 - static struct i2c_algorithm puv3_i2c_algorithm = { 178 178 + static const struct i2c_algorithm puv3_i2c_algorithm = { 179 179 .master_xfer = puv3_i2c_xfer, 180 180 .functionality = puv3_i2c_func, 181 181 };

+2 -4

drivers/i2c/busses/i2c-pxa.c

reviewed

··· 1346 1346 #ifdef CONFIG_PM 1347 1347 static int i2c_pxa_suspend_noirq(struct device *dev) 1348 1348 { 1349 1349 - struct platform_device *pdev = to_platform_device(dev); 1350 1350 - struct pxa_i2c *i2c = platform_get_drvdata(pdev); 1349 1349 + struct pxa_i2c *i2c = dev_get_drvdata(dev); 1351 1350 1352 1351 clk_disable(i2c->clk); 1353 1352 ··· 1355 1356 1356 1357 static int i2c_pxa_resume_noirq(struct device *dev) 1357 1358 { 1358 1358 - struct platform_device *pdev = to_platform_device(dev); 1359 1359 - struct pxa_i2c *i2c = platform_get_drvdata(pdev); 1359 1359 + struct pxa_i2c *i2c = dev_get_drvdata(dev); 1360 1360 1361 1361 clk_enable(i2c->clk); 1362 1362 i2c_pxa_reset(i2c);

+1 -1

drivers/i2c/busses/i2c-qup.c

reviewed

··· 1396 1396 * the end of the read, the length of the read is specified as one byte 1397 1397 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes. 1398 1398 */ 1399 1399 - static struct i2c_adapter_quirks qup_i2c_quirks = { 1399 1399 + static const struct i2c_adapter_quirks qup_i2c_quirks = { 1400 1400 .max_read_len = QUP_READ_LIMIT, 1401 1401 }; 1402 1402

+2 -3

drivers/i2c/busses/i2c-rcar.c

reviewed

··· 625 625 626 626 chan = dma_request_chan(dev, chan_name); 627 627 if (IS_ERR(chan)) { 628 628 - ret = PTR_ERR(chan); 629 629 - dev_dbg(dev, "request_channel failed for %s (%d)\n", 630 630 - chan_name, ret); 628 628 + dev_dbg(dev, "request_channel failed for %s (%ld)\n", 629 629 + chan_name, PTR_ERR(chan)); 631 630 return chan; 632 631 } 633 632

+9

drivers/i2c/busses/i2c-rk3x.c

reviewed

··· 1131 1131 .functionality = rk3x_i2c_func, 1132 1132 }; 1133 1133 1134 1134 + static const struct rk3x_i2c_soc_data rv1108_soc_data = { 1135 1135 + .grf_offset = -1, 1136 1136 + .calc_timings = rk3x_i2c_v1_calc_timings, 1137 1137 + }; 1138 1138 + 1134 1139 static const struct rk3x_i2c_soc_data rk3066_soc_data = { 1135 1140 .grf_offset = 0x154, 1136 1141 .calc_timings = rk3x_i2c_v0_calc_timings, ··· 1162 1157 }; 1163 1158 1164 1159 static const struct of_device_id rk3x_i2c_match[] = { 1160 1160 + { 1161 1161 + .compatible = "rockchip,rv1108-i2c", 1162 1162 + .data = (void *)&rv1108_soc_data 1163 1163 + }, 1165 1164 { 1166 1165 .compatible = "rockchip,rk3066-i2c", 1167 1166 .data = (void *)&rk3066_soc_data

+2 -4

drivers/i2c/busses/i2c-s3c2410.c

reviewed

··· 1246 1246 #ifdef CONFIG_PM_SLEEP 1247 1247 static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1248 1248 { 1249 1249 - struct platform_device *pdev = to_platform_device(dev); 1250 1250 - struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1249 1249 + struct s3c24xx_i2c *i2c = dev_get_drvdata(dev); 1251 1250 1252 1251 i2c->suspended = 1; 1253 1252 ··· 1258 1259 1259 1260 static int s3c24xx_i2c_resume_noirq(struct device *dev) 1260 1261 { 1261 1261 - struct platform_device *pdev = to_platform_device(dev); 1262 1262 - struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1262 1262 + struct s3c24xx_i2c *i2c = dev_get_drvdata(dev); 1263 1263 int ret; 1264 1264 1265 1265 if (!IS_ERR(i2c->sysreg))

+2 -2

drivers/i2c/busses/i2c-sh_mobile.c

reviewed

··· 561 561 562 562 chan = dma_request_slave_channel_reason(dev, chan_name); 563 563 if (IS_ERR(chan)) { 564 564 - ret = PTR_ERR(chan); 565 565 - dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret); 564 564 + dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name, 565 565 + PTR_ERR(chan)); 566 566 return chan; 567 567 } 568 568

+2 -4

drivers/i2c/busses/i2c-sirf.c

reviewed

··· 421 421 #ifdef CONFIG_PM 422 422 static int i2c_sirfsoc_suspend(struct device *dev) 423 423 { 424 424 - struct platform_device *pdev = to_platform_device(dev); 425 425 - struct i2c_adapter *adapter = platform_get_drvdata(pdev); 424 424 + struct i2c_adapter *adapter = dev_get_drvdata(dev); 426 425 struct sirfsoc_i2c *siic = adapter->algo_data; 427 426 428 427 clk_enable(siic->clk); ··· 433 434 434 435 static int i2c_sirfsoc_resume(struct device *dev) 435 436 { 436 436 - struct platform_device *pdev = to_platform_device(dev); 437 437 - struct i2c_adapter *adapter = platform_get_drvdata(pdev); 437 437 + struct i2c_adapter *adapter = dev_get_drvdata(dev); 438 438 struct sirfsoc_i2c *siic = adapter->algo_data; 439 439 440 440 clk_enable(siic->clk);

+646

drivers/i2c/busses/i2c-sprd.c

reviewed

··· 1 1 + /* 2 2 + * Copyright (C) 2017 Spreadtrum Communications Inc. 3 3 + * 4 4 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 5 + */ 6 6 + 7 7 + #include <linux/clk.h> 8 8 + #include <linux/delay.h> 9 9 + #include <linux/err.h> 10 10 + #include <linux/io.h> 11 11 + #include <linux/i2c.h> 12 12 + #include <linux/init.h> 13 13 + #include <linux/interrupt.h> 14 14 + #include <linux/kernel.h> 15 15 + #include <linux/of.h> 16 16 + #include <linux/of_device.h> 17 17 + #include <linux/platform_device.h> 18 18 + #include <linux/pm_runtime.h> 19 19 + 20 20 + #define I2C_CTL 0x00 21 21 + #define I2C_ADDR_CFG 0x04 22 22 + #define I2C_COUNT 0x08 23 23 + #define I2C_RX 0x0c 24 24 + #define I2C_TX 0x10 25 25 + #define I2C_STATUS 0x14 26 26 + #define I2C_HSMODE_CFG 0x18 27 27 + #define I2C_VERSION 0x1c 28 28 + #define ADDR_DVD0 0x20 29 29 + #define ADDR_DVD1 0x24 30 30 + #define ADDR_STA0_DVD 0x28 31 31 + #define ADDR_RST 0x2c 32 32 + 33 33 + /* I2C_CTL */ 34 34 + #define STP_EN BIT(20) 35 35 + #define FIFO_AF_LVL_MASK GENMASK(19, 16) 36 36 + #define FIFO_AF_LVL 16 37 37 + #define FIFO_AE_LVL_MASK GENMASK(15, 12) 38 38 + #define FIFO_AE_LVL 12 39 39 + #define I2C_DMA_EN BIT(11) 40 40 + #define FULL_INTEN BIT(10) 41 41 + #define EMPTY_INTEN BIT(9) 42 42 + #define I2C_DVD_OPT BIT(8) 43 43 + #define I2C_OUT_OPT BIT(7) 44 44 + #define I2C_TRIM_OPT BIT(6) 45 45 + #define I2C_HS_MODE BIT(4) 46 46 + #define I2C_MODE BIT(3) 47 47 + #define I2C_EN BIT(2) 48 48 + #define I2C_INT_EN BIT(1) 49 49 + #define I2C_START BIT(0) 50 50 + 51 51 + /* I2C_STATUS */ 52 52 + #define SDA_IN BIT(21) 53 53 + #define SCL_IN BIT(20) 54 54 + #define FIFO_FULL BIT(4) 55 55 + #define FIFO_EMPTY BIT(3) 56 56 + #define I2C_INT BIT(2) 57 57 + #define I2C_RX_ACK BIT(1) 58 58 + #define I2C_BUSY BIT(0) 59 59 + 60 60 + /* ADDR_RST */ 61 61 + #define I2C_RST BIT(0) 62 62 + 63 63 + #define I2C_FIFO_DEEP 12 64 64 + #define I2C_FIFO_FULL_THLD 15 65 65 + #define I2C_FIFO_EMPTY_THLD 4 66 66 + #define I2C_DATA_STEP 8 67 67 + #define I2C_ADDR_DVD0_CALC(high, low) \ 68 68 + ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0))) 69 69 + #define I2C_ADDR_DVD1_CALC(high, low) \ 70 70 + (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16)) 71 71 + 72 72 + /* timeout (ms) for pm runtime autosuspend */ 73 73 + #define SPRD_I2C_PM_TIMEOUT 1000 74 74 + 75 75 + /* SPRD i2c data structure */ 76 76 + struct sprd_i2c { 77 77 + struct i2c_adapter adap; 78 78 + struct device *dev; 79 79 + void __iomem *base; 80 80 + struct i2c_msg *msg; 81 81 + struct clk *clk; 82 82 + u32 src_clk; 83 83 + u32 bus_freq; 84 84 + struct completion complete; 85 85 + u8 *buf; 86 86 + u32 count; 87 87 + int irq; 88 88 + int err; 89 89 + }; 90 90 + 91 91 + static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count) 92 92 + { 93 93 + writel(count, i2c_dev->base + I2C_COUNT); 94 94 + } 95 95 + 96 96 + static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop) 97 97 + { 98 98 + u32 tmp = readl(i2c_dev->base + I2C_CTL); 99 99 + 100 100 + if (stop) 101 101 + writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL); 102 102 + else 103 103 + writel(tmp | STP_EN, i2c_dev->base + I2C_CTL); 104 104 + } 105 105 + 106 106 + static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev) 107 107 + { 108 108 + u32 tmp = readl(i2c_dev->base + I2C_CTL); 109 109 + 110 110 + writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL); 111 111 + } 112 112 + 113 113 + static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev) 114 114 + { 115 115 + u32 tmp = readl(i2c_dev->base + I2C_STATUS); 116 116 + 117 117 + writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS); 118 118 + } 119 119 + 120 120 + static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev) 121 121 + { 122 122 + u32 tmp = readl(i2c_dev->base + I2C_STATUS); 123 123 + 124 124 + writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS); 125 125 + } 126 126 + 127 127 + static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev) 128 128 + { 129 129 + writel(I2C_RST, i2c_dev->base + ADDR_RST); 130 130 + } 131 131 + 132 132 + static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m) 133 133 + { 134 134 + writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG); 135 135 + } 136 136 + 137 137 + static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len) 138 138 + { 139 139 + u32 i; 140 140 + 141 141 + for (i = 0; i < len; i++) 142 142 + writeb(buf[i], i2c_dev->base + I2C_TX); 143 143 + } 144 144 + 145 145 + static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len) 146 146 + { 147 147 + u32 i; 148 148 + 149 149 + for (i = 0; i < len; i++) 150 150 + buf[i] = readb(i2c_dev->base + I2C_RX); 151 151 + } 152 152 + 153 153 + static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld) 154 154 + { 155 155 + u32 tmp = readl(i2c_dev->base + I2C_CTL); 156 156 + 157 157 + tmp &= ~FIFO_AF_LVL_MASK; 158 158 + tmp |= full_thld << FIFO_AF_LVL; 159 159 + writel(tmp, i2c_dev->base + I2C_CTL); 160 160 + }; 161 161 + 162 162 + static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld) 163 163 + { 164 164 + u32 tmp = readl(i2c_dev->base + I2C_CTL); 165 165 + 166 166 + tmp &= ~FIFO_AE_LVL_MASK; 167 167 + tmp |= empty_thld << FIFO_AE_LVL; 168 168 + writel(tmp, i2c_dev->base + I2C_CTL); 169 169 + }; 170 170 + 171 171 + static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable) 172 172 + { 173 173 + u32 tmp = readl(i2c_dev->base + I2C_CTL); 174 174 + 175 175 + if (enable) 176 176 + tmp |= FULL_INTEN; 177 177 + else 178 178 + tmp &= ~FULL_INTEN; 179 179 + 180 180 + writel(tmp, i2c_dev->base + I2C_CTL); 181 181 + }; 182 182 + 183 183 + static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable) 184 184 + { 185 185 + u32 tmp = readl(i2c_dev->base + I2C_CTL); 186 186 + 187 187 + if (enable) 188 188 + tmp |= EMPTY_INTEN; 189 189 + else 190 190 + tmp &= ~EMPTY_INTEN; 191 191 + 192 192 + writel(tmp, i2c_dev->base + I2C_CTL); 193 193 + }; 194 194 + 195 195 + static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev) 196 196 + { 197 197 + u32 tmp = readl(i2c_dev->base + I2C_CTL); 198 198 + 199 199 + writel(tmp | I2C_START, i2c_dev->base + I2C_CTL); 200 200 + } 201 201 + 202 202 + static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw) 203 203 + { 204 204 + u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE; 205 205 + 206 206 + writel(cmd | rw << 3, i2c_dev->base + I2C_CTL); 207 207 + } 208 208 + 209 209 + static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev) 210 210 + { 211 211 + u32 i2c_count = i2c_dev->count; 212 212 + u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP; 213 213 + struct i2c_msg *msg = i2c_dev->msg; 214 214 + 215 215 + if (msg->flags & I2C_M_RD) { 216 216 + sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD); 217 217 + i2c_dev->count -= I2C_FIFO_FULL_THLD; 218 218 + i2c_dev->buf += I2C_FIFO_FULL_THLD; 219 219 + 220 220 + /* 221 221 + * If the read data count is larger than rx fifo full threshold, 222 222 + * we should enable the rx fifo full interrupt to read data 223 223 + * again. 224 224 + */ 225 225 + if (i2c_dev->count >= I2C_FIFO_FULL_THLD) 226 226 + sprd_i2c_set_fifo_full_int(i2c_dev, 1); 227 227 + } else { 228 228 + sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran); 229 229 + i2c_dev->buf += need_tran; 230 230 + i2c_dev->count -= need_tran; 231 231 + 232 232 + /* 233 233 + * If the write data count is arger than tx fifo depth which 234 234 + * means we can not write all data in one time, then we should 235 235 + * enable the tx fifo empty interrupt to write again. 236 236 + */ 237 237 + if (i2c_count > I2C_FIFO_DEEP) 238 238 + sprd_i2c_set_fifo_empty_int(i2c_dev, 1); 239 239 + } 240 240 + } 241 241 + 242 242 + static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap, 243 243 + struct i2c_msg *msg, bool is_last_msg) 244 244 + { 245 245 + struct sprd_i2c *i2c_dev = i2c_adap->algo_data; 246 246 + 247 247 + i2c_dev->msg = msg; 248 248 + i2c_dev->buf = msg->buf; 249 249 + i2c_dev->count = msg->len; 250 250 + 251 251 + reinit_completion(&i2c_dev->complete); 252 252 + sprd_i2c_reset_fifo(i2c_dev); 253 253 + sprd_i2c_set_devaddr(i2c_dev, msg); 254 254 + sprd_i2c_set_count(i2c_dev, msg->len); 255 255 + 256 256 + if (msg->flags & I2C_M_RD) { 257 257 + sprd_i2c_opt_mode(i2c_dev, 1); 258 258 + sprd_i2c_send_stop(i2c_dev, 1); 259 259 + } else { 260 260 + sprd_i2c_opt_mode(i2c_dev, 0); 261 261 + sprd_i2c_send_stop(i2c_dev, !!is_last_msg); 262 262 + } 263 263 + 264 264 + /* 265 265 + * We should enable rx fifo full interrupt to get data when receiving 266 266 + * full data. 267 267 + */ 268 268 + if (msg->flags & I2C_M_RD) 269 269 + sprd_i2c_set_fifo_full_int(i2c_dev, 1); 270 270 + else 271 271 + sprd_i2c_data_transfer(i2c_dev); 272 272 + 273 273 + sprd_i2c_opt_start(i2c_dev); 274 274 + 275 275 + wait_for_completion(&i2c_dev->complete); 276 276 + 277 277 + return i2c_dev->err; 278 278 + } 279 279 + 280 280 + static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap, 281 281 + struct i2c_msg *msgs, int num) 282 282 + { 283 283 + struct sprd_i2c *i2c_dev = i2c_adap->algo_data; 284 284 + int im, ret; 285 285 + 286 286 + ret = pm_runtime_get_sync(i2c_dev->dev); 287 287 + if (ret < 0) 288 288 + return ret; 289 289 + 290 290 + for (im = 0; im < num - 1; im++) { 291 291 + ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0); 292 292 + if (ret) 293 293 + goto err_msg; 294 294 + } 295 295 + 296 296 + ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1); 297 297 + 298 298 + err_msg: 299 299 + pm_runtime_mark_last_busy(i2c_dev->dev); 300 300 + pm_runtime_put_autosuspend(i2c_dev->dev); 301 301 + 302 302 + return ret < 0 ? ret : im; 303 303 + } 304 304 + 305 305 + static u32 sprd_i2c_func(struct i2c_adapter *adap) 306 306 + { 307 307 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 308 308 + } 309 309 + 310 310 + static const struct i2c_algorithm sprd_i2c_algo = { 311 311 + .master_xfer = sprd_i2c_master_xfer, 312 312 + .functionality = sprd_i2c_func, 313 313 + }; 314 314 + 315 315 + static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq) 316 316 + { 317 317 + u32 apb_clk = i2c_dev->src_clk; 318 318 + /* 319 319 + * From I2C databook, the prescale calculation formula: 320 320 + * prescale = freq_i2c / (4 * freq_scl) - 1; 321 321 + */ 322 322 + u32 i2c_dvd = apb_clk / (4 * freq) - 1; 323 323 + /* 324 324 + * From I2C databook, the high period of SCL clock is recommended as 325 325 + * 40% (2/5), and the low period of SCL clock is recommended as 60% 326 326 + * (3/5), then the formula should be: 327 327 + * high = (prescale * 2 * 2) / 5 328 328 + * low = (prescale * 2 * 3) / 5 329 329 + */ 330 330 + u32 high = ((i2c_dvd << 1) * 2) / 5; 331 331 + u32 low = ((i2c_dvd << 1) * 3) / 5; 332 332 + u32 div0 = I2C_ADDR_DVD0_CALC(high, low); 333 333 + u32 div1 = I2C_ADDR_DVD1_CALC(high, low); 334 334 + 335 335 + writel(div0, i2c_dev->base + ADDR_DVD0); 336 336 + writel(div1, i2c_dev->base + ADDR_DVD1); 337 337 + 338 338 + /* Start hold timing = hold time(us) * source clock */ 339 339 + if (freq == 400000) 340 340 + writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD); 341 341 + else if (freq == 100000) 342 342 + writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD); 343 343 + } 344 344 + 345 345 + static void sprd_i2c_enable(struct sprd_i2c *i2c_dev) 346 346 + { 347 347 + u32 tmp = I2C_DVD_OPT; 348 348 + 349 349 + writel(tmp, i2c_dev->base + I2C_CTL); 350 350 + 351 351 + sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD); 352 352 + sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD); 353 353 + 354 354 + sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq); 355 355 + sprd_i2c_reset_fifo(i2c_dev); 356 356 + sprd_i2c_clear_irq(i2c_dev); 357 357 + 358 358 + tmp = readl(i2c_dev->base + I2C_CTL); 359 359 + writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL); 360 360 + } 361 361 + 362 362 + static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id) 363 363 + { 364 364 + struct sprd_i2c *i2c_dev = dev_id; 365 365 + struct i2c_msg *msg = i2c_dev->msg; 366 366 + bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK); 367 367 + u32 i2c_count = readl(i2c_dev->base + I2C_COUNT); 368 368 + u32 i2c_tran; 369 369 + 370 370 + if (msg->flags & I2C_M_RD) 371 371 + i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD; 372 372 + else 373 373 + i2c_tran = i2c_count; 374 374 + 375 375 + /* 376 376 + * If we got one ACK from slave when writing data, and we did not 377 377 + * finish this transmission (i2c_tran is not zero), then we should 378 378 + * continue to write data. 379 379 + * 380 380 + * For reading data, ack is always true, if i2c_tran is not 0 which 381 381 + * means we still need to contine to read data from slave. 382 382 + */ 383 383 + if (i2c_tran && ack) { 384 384 + sprd_i2c_data_transfer(i2c_dev); 385 385 + return IRQ_HANDLED; 386 386 + } 387 387 + 388 388 + i2c_dev->err = 0; 389 389 + 390 390 + /* 391 391 + * If we did not get one ACK from slave when writing data, we should 392 392 + * return -EIO to notify users. 393 393 + */ 394 394 + if (!ack) 395 395 + i2c_dev->err = -EIO; 396 396 + else if (msg->flags & I2C_M_RD && i2c_dev->count) 397 397 + sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count); 398 398 + 399 399 + /* Transmission is done and clear ack and start operation */ 400 400 + sprd_i2c_clear_ack(i2c_dev); 401 401 + sprd_i2c_clear_start(i2c_dev); 402 402 + complete(&i2c_dev->complete); 403 403 + 404 404 + return IRQ_HANDLED; 405 405 + } 406 406 + 407 407 + static irqreturn_t sprd_i2c_isr(int irq, void *dev_id) 408 408 + { 409 409 + struct sprd_i2c *i2c_dev = dev_id; 410 410 + struct i2c_msg *msg = i2c_dev->msg; 411 411 + u32 i2c_count = readl(i2c_dev->base + I2C_COUNT); 412 412 + bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK); 413 413 + u32 i2c_tran; 414 414 + 415 415 + if (msg->flags & I2C_M_RD) 416 416 + i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD; 417 417 + else 418 418 + i2c_tran = i2c_count; 419 419 + 420 420 + /* 421 421 + * If we did not get one ACK from slave when writing data, then we 422 422 + * should finish this transmission since we got some errors. 423 423 + * 424 424 + * When writing data, if i2c_tran == 0 which means we have writen 425 425 + * done all data, then we can finish this transmission. 426 426 + * 427 427 + * When reading data, if conut < rx fifo full threshold, which 428 428 + * means we can read all data in one time, then we can finish this 429 429 + * transmission too. 430 430 + */ 431 431 + if (!i2c_tran || !ack) { 432 432 + sprd_i2c_clear_start(i2c_dev); 433 433 + sprd_i2c_clear_irq(i2c_dev); 434 434 + } 435 435 + 436 436 + sprd_i2c_set_fifo_empty_int(i2c_dev, 0); 437 437 + sprd_i2c_set_fifo_full_int(i2c_dev, 0); 438 438 + 439 439 + return IRQ_WAKE_THREAD; 440 440 + } 441 441 + 442 442 + static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev) 443 443 + { 444 444 + struct clk *clk_i2c, *clk_parent; 445 445 + 446 446 + clk_i2c = devm_clk_get(i2c_dev->dev, "i2c"); 447 447 + if (IS_ERR(clk_i2c)) { 448 448 + dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n", 449 449 + i2c_dev->adap.nr); 450 450 + clk_i2c = NULL; 451 451 + } 452 452 + 453 453 + clk_parent = devm_clk_get(i2c_dev->dev, "source"); 454 454 + if (IS_ERR(clk_parent)) { 455 455 + dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n", 456 456 + i2c_dev->adap.nr); 457 457 + clk_parent = NULL; 458 458 + } 459 459 + 460 460 + if (clk_set_parent(clk_i2c, clk_parent)) 461 461 + i2c_dev->src_clk = clk_get_rate(clk_i2c); 462 462 + else 463 463 + i2c_dev->src_clk = 26000000; 464 464 + 465 465 + dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n", 466 466 + i2c_dev->adap.nr, i2c_dev->src_clk); 467 467 + 468 468 + i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable"); 469 469 + if (IS_ERR(i2c_dev->clk)) { 470 470 + dev_warn(i2c_dev->dev, "i2c%d can't get the enable clock\n", 471 471 + i2c_dev->adap.nr); 472 472 + i2c_dev->clk = NULL; 473 473 + } 474 474 + 475 475 + return 0; 476 476 + } 477 477 + 478 478 + static int sprd_i2c_probe(struct platform_device *pdev) 479 479 + { 480 480 + struct device *dev = &pdev->dev; 481 481 + struct sprd_i2c *i2c_dev; 482 482 + struct resource *res; 483 483 + u32 prop; 484 484 + int ret; 485 485 + 486 486 + pdev->id = of_alias_get_id(dev->of_node, "i2c"); 487 487 + 488 488 + i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL); 489 489 + if (!i2c_dev) 490 490 + return -ENOMEM; 491 491 + 492 492 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 493 493 + i2c_dev->base = devm_ioremap_resource(dev, res); 494 494 + if (IS_ERR(i2c_dev->base)) 495 495 + return PTR_ERR(i2c_dev->base); 496 496 + 497 497 + i2c_dev->irq = platform_get_irq(pdev, 0); 498 498 + if (i2c_dev->irq < 0) { 499 499 + dev_err(&pdev->dev, "failed to get irq resource\n"); 500 500 + return i2c_dev->irq; 501 501 + } 502 502 + 503 503 + i2c_set_adapdata(&i2c_dev->adap, i2c_dev); 504 504 + init_completion(&i2c_dev->complete); 505 505 + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), 506 506 + "%s", "sprd-i2c"); 507 507 + 508 508 + i2c_dev->bus_freq = 100000; 509 509 + i2c_dev->adap.owner = THIS_MODULE; 510 510 + i2c_dev->dev = dev; 511 511 + i2c_dev->adap.retries = 3; 512 512 + i2c_dev->adap.algo = &sprd_i2c_algo; 513 513 + i2c_dev->adap.algo_data = i2c_dev; 514 514 + i2c_dev->adap.dev.parent = dev; 515 515 + i2c_dev->adap.nr = pdev->id; 516 516 + i2c_dev->adap.dev.of_node = dev->of_node; 517 517 + 518 518 + if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop)) 519 519 + i2c_dev->bus_freq = prop; 520 520 + 521 521 + /* We only support 100k and 400k now, otherwise will return error. */ 522 522 + if (i2c_dev->bus_freq != 100000 && i2c_dev->bus_freq != 400000) 523 523 + return -EINVAL; 524 524 + 525 525 + sprd_i2c_clk_init(i2c_dev); 526 526 + platform_set_drvdata(pdev, i2c_dev); 527 527 + 528 528 + ret = clk_prepare_enable(i2c_dev->clk); 529 529 + if (ret) 530 530 + return ret; 531 531 + 532 532 + sprd_i2c_enable(i2c_dev); 533 533 + 534 534 + pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT); 535 535 + pm_runtime_use_autosuspend(i2c_dev->dev); 536 536 + pm_runtime_set_active(i2c_dev->dev); 537 537 + pm_runtime_enable(i2c_dev->dev); 538 538 + 539 539 + ret = pm_runtime_get_sync(i2c_dev->dev); 540 540 + if (ret < 0) 541 541 + goto err_rpm_put; 542 542 + 543 543 + ret = devm_request_threaded_irq(dev, i2c_dev->irq, 544 544 + sprd_i2c_isr, sprd_i2c_isr_thread, 545 545 + IRQF_NO_SUSPEND | IRQF_ONESHOT, 546 546 + pdev->name, i2c_dev); 547 547 + if (ret) { 548 548 + dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq); 549 549 + goto err_rpm_put; 550 550 + } 551 551 + 552 552 + ret = i2c_add_numbered_adapter(&i2c_dev->adap); 553 553 + if (ret) { 554 554 + dev_err(&pdev->dev, "add adapter failed\n"); 555 555 + goto err_rpm_put; 556 556 + } 557 557 + 558 558 + pm_runtime_mark_last_busy(i2c_dev->dev); 559 559 + pm_runtime_put_autosuspend(i2c_dev->dev); 560 560 + return 0; 561 561 + 562 562 + err_rpm_put: 563 563 + pm_runtime_put_noidle(i2c_dev->dev); 564 564 + pm_runtime_disable(i2c_dev->dev); 565 565 + clk_disable_unprepare(i2c_dev->clk); 566 566 + return ret; 567 567 + } 568 568 + 569 569 + static int sprd_i2c_remove(struct platform_device *pdev) 570 570 + { 571 571 + struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev); 572 572 + int ret; 573 573 + 574 574 + ret = pm_runtime_get_sync(i2c_dev->dev); 575 575 + if (ret < 0) 576 576 + return ret; 577 577 + 578 578 + i2c_del_adapter(&i2c_dev->adap); 579 579 + clk_disable_unprepare(i2c_dev->clk); 580 580 + 581 581 + pm_runtime_put_noidle(i2c_dev->dev); 582 582 + pm_runtime_disable(i2c_dev->dev); 583 583 + 584 584 + return 0; 585 585 + } 586 586 + 587 587 + static int __maybe_unused sprd_i2c_suspend_noirq(struct device *pdev) 588 588 + { 589 589 + return pm_runtime_force_suspend(pdev); 590 590 + } 591 591 + 592 592 + static int __maybe_unused sprd_i2c_resume_noirq(struct device *pdev) 593 593 + { 594 594 + return pm_runtime_force_resume(pdev); 595 595 + } 596 596 + 597 597 + static int __maybe_unused sprd_i2c_runtime_suspend(struct device *pdev) 598 598 + { 599 599 + struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev); 600 600 + 601 601 + clk_disable_unprepare(i2c_dev->clk); 602 602 + 603 603 + return 0; 604 604 + } 605 605 + 606 606 + static int __maybe_unused sprd_i2c_runtime_resume(struct device *pdev) 607 607 + { 608 608 + struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev); 609 609 + int ret; 610 610 + 611 611 + ret = clk_prepare_enable(i2c_dev->clk); 612 612 + if (ret) 613 613 + return ret; 614 614 + 615 615 + sprd_i2c_enable(i2c_dev); 616 616 + 617 617 + return 0; 618 618 + } 619 619 + 620 620 + static const struct dev_pm_ops sprd_i2c_pm_ops = { 621 621 + SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend, 622 622 + sprd_i2c_runtime_resume, NULL) 623 623 + 624 624 + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq, 625 625 + sprd_i2c_resume_noirq) 626 626 + }; 627 627 + 628 628 + static const struct of_device_id sprd_i2c_of_match[] = { 629 629 + { .compatible = "sprd,sc9860-i2c", }, 630 630 + }; 631 631 + 632 632 + static struct platform_driver sprd_i2c_driver = { 633 633 + .probe = sprd_i2c_probe, 634 634 + .remove = sprd_i2c_remove, 635 635 + .driver = { 636 636 + .name = "sprd-i2c", 637 637 + .of_match_table = sprd_i2c_of_match, 638 638 + .pm = &sprd_i2c_pm_ops, 639 639 + }, 640 640 + }; 641 641 + 642 642 + static int sprd_i2c_init(void) 643 643 + { 644 644 + return platform_driver_register(&sprd_i2c_driver); 645 645 + } 646 646 + arch_initcall_sync(sprd_i2c_init);

+1 -2

drivers/i2c/busses/i2c-st.c

reviewed

··· 745 745 #ifdef CONFIG_PM_SLEEP 746 746 static int st_i2c_suspend(struct device *dev) 747 747 { 748 748 - struct platform_device *pdev = to_platform_device(dev); 749 749 - struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 748 748 + struct st_i2c_dev *i2c_dev = dev_get_drvdata(dev); 750 749 751 750 if (i2c_dev->busy) 752 751 return -EBUSY;

+2 -2

drivers/i2c/busses/i2c-stm32f4.c

reviewed

··· 751 751 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 752 752 } 753 753 754 754 - static struct i2c_algorithm stm32f4_i2c_algo = { 754 754 + static const struct i2c_algorithm stm32f4_i2c_algo = { 755 755 .master_xfer = stm32f4_i2c_xfer, 756 756 .functionality = stm32f4_i2c_func, 757 757 }; ··· 798 798 return ret; 799 799 } 800 800 801 801 - rst = devm_reset_control_get(&pdev->dev, NULL); 801 801 + rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 802 802 if (IS_ERR(rst)) { 803 803 dev_err(&pdev->dev, "Error: Missing controller reset\n"); 804 804 ret = PTR_ERR(rst);

+3 -3

drivers/i2c/busses/i2c-sun6i-p2wi.c

reviewed

··· 223 223 if (childnp) { 224 224 ret = of_property_read_u32(childnp, "reg", &slave_addr); 225 225 if (ret) { 226 226 - dev_err(dev, "invalid slave address on node %s\n", 227 227 - childnp->full_name); 226 226 + dev_err(dev, "invalid slave address on node %pOF\n", 227 227 + childnp); 228 228 return -EINVAL; 229 229 } 230 230 ··· 258 258 259 259 parent_clk_freq = clk_get_rate(p2wi->clk); 260 260 261 261 - p2wi->rstc = devm_reset_control_get(dev, NULL); 261 261 + p2wi->rstc = devm_reset_control_get_exclusive(dev, NULL); 262 262 if (IS_ERR(p2wi->rstc)) { 263 263 ret = PTR_ERR(p2wi->rstc); 264 264 dev_err(dev, "failed to retrieve reset controller: %d\n", ret);

+1 -1

drivers/i2c/busses/i2c-taos-evm.c

reviewed

··· 291 291 dev_info(&serio->dev, "Disconnected from TAOS EVM\n"); 292 292 } 293 293 294 294 - static struct serio_device_id taos_serio_ids[] = { 294 294 + static const struct serio_device_id taos_serio_ids[] = { 295 295 { 296 296 .type = SERIO_RS232, 297 297 .proto = SERIO_TAOSEVM,

+2 -2

drivers/i2c/busses/i2c-tegra.c

reviewed

··· 793 793 }; 794 794 795 795 /* payload size is only 12 bit */ 796 796 - static struct i2c_adapter_quirks tegra_i2c_quirks = { 796 796 + static const struct i2c_adapter_quirks tegra_i2c_quirks = { 797 797 .max_read_len = 4096, 798 798 .max_write_len = 4096, 799 799 }; ··· 911 911 i2c_dev->cont_id = pdev->id; 912 912 i2c_dev->dev = &pdev->dev; 913 913 914 914 - i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c"); 914 914 + i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); 915 915 if (IS_ERR(i2c_dev->rst)) { 916 916 dev_err(&pdev->dev, "missing controller reset\n"); 917 917 return PTR_ERR(i2c_dev->rst);

+1 -1

drivers/i2c/busses/i2c-thunderx-pcidrv.c

reviewed

··· 75 75 .functionality = thunderx_i2c_functionality, 76 76 }; 77 77 78 78 - static struct i2c_adapter thunderx_i2c_ops = { 78 78 + static const struct i2c_adapter thunderx_i2c_ops = { 79 79 .owner = THIS_MODULE, 80 80 .name = "ThunderX adapter", 81 81 .algo = &thunderx_i2c_algo,

+37 -9

drivers/i2c/busses/i2c-uniphier-f.c

reviewed

··· 97 97 int error; 98 98 unsigned int flags; 99 99 unsigned int busy_cnt; 100 100 + unsigned int clk_cycle; 100 101 }; 101 102 102 103 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv, ··· 462 461 .unprepare_recovery = uniphier_fi2c_unprepare_recovery, 463 462 }; 464 463 465 465 - static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv, 466 466 - u32 bus_speed, unsigned long clk_rate) 464 464 + static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv) 467 465 { 466 466 + unsigned int cyc = priv->clk_cycle; 468 467 u32 tmp; 469 468 470 469 tmp = readl(priv->membase + UNIPHIER_FI2C_CR); ··· 473 472 474 473 uniphier_fi2c_reset(priv); 475 474 476 476 - tmp = clk_rate / bus_speed; 477 477 - 478 478 - writel(tmp, priv->membase + UNIPHIER_FI2C_CYC); 479 479 - writel(tmp / 2, priv->membase + UNIPHIER_FI2C_LCTL); 480 480 - writel(tmp / 2, priv->membase + UNIPHIER_FI2C_SSUT); 481 481 - writel(tmp / 16, priv->membase + UNIPHIER_FI2C_DSUT); 475 475 + writel(cyc, priv->membase + UNIPHIER_FI2C_CYC); 476 476 + writel(cyc / 2, priv->membase + UNIPHIER_FI2C_LCTL); 477 477 + writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT); 478 478 + writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT); 482 479 483 480 uniphier_fi2c_prepare_operation(priv); 484 481 } ··· 530 531 goto disable_clk; 531 532 } 532 533 534 534 + priv->clk_cycle = clk_rate / bus_speed; 533 535 init_completion(&priv->comp); 534 536 priv->adap.owner = THIS_MODULE; 535 537 priv->adap.algo = &uniphier_fi2c_algo; ··· 541 541 i2c_set_adapdata(&priv->adap, priv); 542 542 platform_set_drvdata(pdev, priv); 543 543 544 544 - uniphier_fi2c_hw_init(priv, bus_speed, clk_rate); 544 544 + uniphier_fi2c_hw_init(priv); 545 545 546 546 ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0, 547 547 pdev->name, priv); ··· 568 568 return 0; 569 569 } 570 570 571 571 + static int __maybe_unused uniphier_fi2c_suspend(struct device *dev) 572 572 + { 573 573 + struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 574 574 + 575 575 + clk_disable_unprepare(priv->clk); 576 576 + 577 577 + return 0; 578 578 + } 579 579 + 580 580 + static int __maybe_unused uniphier_fi2c_resume(struct device *dev) 581 581 + { 582 582 + struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 583 583 + int ret; 584 584 + 585 585 + ret = clk_prepare_enable(priv->clk); 586 586 + if (ret) 587 587 + return ret; 588 588 + 589 589 + uniphier_fi2c_hw_init(priv); 590 590 + 591 591 + return 0; 592 592 + } 593 593 + 594 594 + static const struct dev_pm_ops uniphier_fi2c_pm_ops = { 595 595 + SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume) 596 596 + }; 597 597 + 571 598 static const struct of_device_id uniphier_fi2c_match[] = { 572 599 { .compatible = "socionext,uniphier-fi2c" }, 573 600 { /* sentinel */ } ··· 607 580 .driver = { 608 581 .name = "uniphier-fi2c", 609 582 .of_match_table = uniphier_fi2c_match, 583 583 + .pm = &uniphier_fi2c_pm_ops, 610 584 }, 611 585 }; 612 586 module_platform_driver(uniphier_fi2c_drv);

+35 -5

drivers/i2c/busses/i2c-uniphier.c

reviewed

··· 53 53 void __iomem *membase; 54 54 struct clk *clk; 55 55 unsigned int busy_cnt; 56 56 + unsigned int clk_cycle; 56 57 }; 57 58 58 59 static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id) ··· 317 316 .unprepare_recovery = uniphier_i2c_unprepare_recovery, 318 317 }; 319 318 320 320 - static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv, 321 321 - u32 bus_speed, unsigned long clk_rate) 319 319 + static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv) 322 320 { 321 321 + unsigned int cyc = priv->clk_cycle; 322 322 + 323 323 uniphier_i2c_reset(priv, true); 324 324 325 325 - writel((clk_rate / bus_speed / 2 << 16) | (clk_rate / bus_speed), 326 326 - priv->membase + UNIPHIER_I2C_CLK); 325 325 + writel((cyc / 2 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK); 327 326 328 327 uniphier_i2c_reset(priv, false); 329 328 } ··· 377 376 goto disable_clk; 378 377 } 379 378 379 379 + priv->clk_cycle = clk_rate / bus_speed; 380 380 init_completion(&priv->comp); 381 381 priv->adap.owner = THIS_MODULE; 382 382 priv->adap.algo = &uniphier_i2c_algo; ··· 388 386 i2c_set_adapdata(&priv->adap, priv); 389 387 platform_set_drvdata(pdev, priv); 390 388 391 391 - uniphier_i2c_hw_init(priv, bus_speed, clk_rate); 389 389 + uniphier_i2c_hw_init(priv); 392 390 393 391 ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name, 394 392 priv); ··· 415 413 return 0; 416 414 } 417 415 416 416 + static int __maybe_unused uniphier_i2c_suspend(struct device *dev) 417 417 + { 418 418 + struct uniphier_i2c_priv *priv = dev_get_drvdata(dev); 419 419 + 420 420 + clk_disable_unprepare(priv->clk); 421 421 + 422 422 + return 0; 423 423 + } 424 424 + 425 425 + static int __maybe_unused uniphier_i2c_resume(struct device *dev) 426 426 + { 427 427 + struct uniphier_i2c_priv *priv = dev_get_drvdata(dev); 428 428 + int ret; 429 429 + 430 430 + ret = clk_prepare_enable(priv->clk); 431 431 + if (ret) 432 432 + return ret; 433 433 + 434 434 + uniphier_i2c_hw_init(priv); 435 435 + 436 436 + return 0; 437 437 + } 438 438 + 439 439 + static const struct dev_pm_ops uniphier_i2c_pm_ops = { 440 440 + SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume) 441 441 + }; 442 442 + 418 443 static const struct of_device_id uniphier_i2c_match[] = { 419 444 { .compatible = "socionext,uniphier-i2c" }, 420 445 { /* sentinel */ } ··· 454 425 .driver = { 455 426 .name = "uniphier-i2c", 456 427 .of_match_table = uniphier_i2c_match, 428 428 + .pm = &uniphier_i2c_pm_ops, 457 429 }, 458 430 }; 459 431 module_platform_driver(uniphier_i2c_drv);

+1 -1

drivers/i2c/busses/i2c-versatile.c

reviewed

··· 55 55 return !!(readl(i2c->base + I2C_CONTROL) & SCL); 56 56 } 57 57 58 58 - static struct i2c_algo_bit_data i2c_versatile_algo = { 58 58 + static const struct i2c_algo_bit_data i2c_versatile_algo = { 59 59 .setsda = i2c_versatile_setsda, 60 60 .setscl = i2c_versatile_setscl, 61 61 .getsda = i2c_versatile_getsda,

+3 -5

drivers/i2c/busses/i2c-xiic.c

reviewed

··· 721 721 .functionality = xiic_func, 722 722 }; 723 723 724 724 - static struct i2c_adapter xiic_adapter = { 724 724 + static const struct i2c_adapter xiic_adapter = { 725 725 .owner = THIS_MODULE, 726 726 .name = DRIVER_NAME, 727 727 .class = I2C_CLASS_DEPRECATED, ··· 853 853 854 854 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) 855 855 { 856 856 - struct platform_device *pdev = to_platform_device(dev); 857 857 - struct xiic_i2c *i2c = platform_get_drvdata(pdev); 856 856 + struct xiic_i2c *i2c = dev_get_drvdata(dev); 858 857 859 858 clk_disable(i2c->clk); 860 859 ··· 862 863 863 864 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) 864 865 { 865 865 - struct platform_device *pdev = to_platform_device(dev); 866 866 - struct xiic_i2c *i2c = platform_get_drvdata(pdev); 866 866 + struct xiic_i2c *i2c = dev_get_drvdata(dev); 867 867 int ret; 868 868 869 869 ret = clk_enable(i2c->clk);

+11 -13

drivers/i2c/i2c-core-of.c

reviewed

··· 32 32 u32 addr; 33 33 int len; 34 34 35 35 - dev_dbg(&adap->dev, "of_i2c: register %s\n", node->full_name); 35 35 + dev_dbg(&adap->dev, "of_i2c: register %pOF\n", node); 36 36 37 37 if (of_modalias_node(node, info.type, sizeof(info.type)) < 0) { 38 38 - dev_err(&adap->dev, "of_i2c: modalias failure on %s\n", 39 39 - node->full_name); 38 38 + dev_err(&adap->dev, "of_i2c: modalias failure on %pOF\n", 39 39 + node); 40 40 return ERR_PTR(-EINVAL); 41 41 } 42 42 43 43 addr_be = of_get_property(node, "reg", &len); 44 44 if (!addr_be || (len < sizeof(*addr_be))) { 45 45 - dev_err(&adap->dev, "of_i2c: invalid reg on %s\n", 46 46 - node->full_name); 45 45 + dev_err(&adap->dev, "of_i2c: invalid reg on %pOF\n", node); 47 46 return ERR_PTR(-EINVAL); 48 47 } 49 48 ··· 58 59 } 59 60 60 61 if (i2c_check_addr_validity(addr, info.flags)) { 61 61 - dev_err(&adap->dev, "of_i2c: invalid addr=%x on %s\n", 62 62 - addr, node->full_name); 62 62 + dev_err(&adap->dev, "of_i2c: invalid addr=%x on %pOF\n", 63 63 + addr, node); 63 64 return ERR_PTR(-EINVAL); 64 65 } 65 66 ··· 75 76 76 77 result = i2c_new_device(adap, &info); 77 78 if (result == NULL) { 78 78 - dev_err(&adap->dev, "of_i2c: Failure registering %s\n", 79 79 - node->full_name); 79 79 + dev_err(&adap->dev, "of_i2c: Failure registering %pOF\n", node); 80 80 of_node_put(node); 81 81 return ERR_PTR(-EINVAL); 82 82 } ··· 104 106 client = of_i2c_register_device(adap, node); 105 107 if (IS_ERR(client)) { 106 108 dev_warn(&adap->dev, 107 107 - "Failed to create I2C device for %s\n", 108 108 - node->full_name); 109 109 + "Failed to create I2C device for %pOF\n", 110 110 + node); 109 111 of_node_clear_flag(node, OF_POPULATED); 110 112 } 111 113 } ··· 241 243 put_device(&adap->dev); 242 244 243 245 if (IS_ERR(client)) { 244 244 - dev_err(&adap->dev, "failed to create client for '%s'\n", 245 245 - rd->dn->full_name); 246 246 + dev_err(&adap->dev, "failed to create client for '%pOF'\n", 247 247 + rd->dn); 246 248 of_node_clear_flag(rd->dn, OF_POPULATED); 247 249 return notifier_from_errno(PTR_ERR(client)); 248 250 }

+2 -1

drivers/i2c/muxes/Kconfig

reviewed

··· 8 8 config I2C_ARB_GPIO_CHALLENGE 9 9 tristate "GPIO-based I2C arbitration" 10 10 depends on GPIOLIB || COMPILE_TEST 11 11 - depends on OF 11 11 + depends on OF || COMPILE_TEST 12 12 help 13 13 If you say yes to this option, support will be included for an 14 14 I2C multimaster arbitration scheme using GPIOs and a challenge & ··· 76 76 config I2C_MUX_PINCTRL 77 77 tristate "pinctrl-based I2C multiplexer" 78 78 depends on PINCTRL 79 79 + depends on OF || COMPILE_TEST 79 80 help 80 81 If you say yes to this option, support will be included for an I2C 81 82 multiplexer that uses the pinctrl subsystem, i.e. pin multiplexing.

+2 -2

drivers/i2c/muxes/i2c-demux-pinctrl.c

reviewed

··· 167 167 int count = 0, i; 168 168 169 169 for (i = 0; i < priv->num_chan && count < PAGE_SIZE; i++) 170 170 - count += scnprintf(buf + count, PAGE_SIZE - count, "%d:%s%c", 171 171 - i, priv->chan[i].parent_np->full_name, 170 170 + count += scnprintf(buf + count, PAGE_SIZE - count, "%d:%pOF%c", 171 171 + i, priv->chan[i].parent_np, 172 172 i == priv->num_chan - 1 ? '\n' : ' '); 173 173 174 174 return count;

+1 -1

drivers/i2c/muxes/i2c-mux-mlxcpld.c

reviewed

··· 38 38 #include <linux/io.h> 39 39 #include <linux/init.h> 40 40 #include <linux/module.h> 41 41 + #include <linux/platform_data/x86/mlxcpld.h> 41 42 #include <linux/platform_device.h> 42 43 #include <linux/slab.h> 43 43 - #include <linux/i2c/mlxcpld.h> 44 44 45 45 #define CPLD_MUX_MAX_NCHANS 8 46 46

+4 -5

drivers/i2c/muxes/i2c-mux-pca9541.c

reviewed

··· 16 16 * warranty of any kind, whether express or implied. 17 17 */ 18 18 19 19 - #include <linux/module.h> 20 20 - #include <linux/jiffies.h> 21 19 #include <linux/delay.h> 22 22 - #include <linux/slab.h> 23 20 #include <linux/device.h> 24 21 #include <linux/i2c.h> 25 22 #include <linux/i2c-mux.h> 26 26 - 27 27 - #include <linux/i2c/pca954x.h> 23 23 + #include <linux/jiffies.h> 24 24 + #include <linux/module.h> 25 25 + #include <linux/platform_data/pca954x.h> 26 26 + #include <linux/slab.h> 28 27 29 28 /* 30 29 * The PCA9541 is a bus master selector. It supports two I2C masters connected

+1 -1

drivers/i2c/muxes/i2c-mux-pca954x.c

reviewed

··· 39 39 #include <linux/gpio/consumer.h> 40 40 #include <linux/i2c.h> 41 41 #include <linux/i2c-mux.h> 42 42 - #include <linux/i2c/pca954x.h> 43 42 #include <linux/interrupt.h> 44 43 #include <linux/irq.h> 45 44 #include <linux/module.h> 46 45 #include <linux/of.h> 47 46 #include <linux/of_device.h> 48 47 #include <linux/of_irq.h> 48 48 + #include <linux/platform_data/pca954x.h> 49 49 #include <linux/pm.h> 50 50 #include <linux/slab.h> 51 51 #include <linux/spinlock.h>

+72 -153

drivers/i2c/muxes/i2c-mux-pinctrl.c

reviewed

··· 20 20 #include <linux/i2c-mux.h> 21 21 #include <linux/module.h> 22 22 #include <linux/pinctrl/consumer.h> 23 23 - #include <linux/i2c-mux-pinctrl.h> 24 23 #include <linux/platform_device.h> 25 24 #include <linux/slab.h> 26 25 #include <linux/of.h> 27 26 #include "../../pinctrl/core.h" 28 27 29 28 struct i2c_mux_pinctrl { 30 30 - struct i2c_mux_pinctrl_platform_data *pdata; 31 29 struct pinctrl *pinctrl; 32 30 struct pinctrl_state **states; 33 33 - struct pinctrl_state *state_idle; 34 31 }; 35 32 36 33 static int i2c_mux_pinctrl_select(struct i2c_mux_core *muxc, u32 chan) ··· 39 42 40 43 static int i2c_mux_pinctrl_deselect(struct i2c_mux_core *muxc, u32 chan) 41 44 { 42 42 - struct i2c_mux_pinctrl *mux = i2c_mux_priv(muxc); 43 43 - 44 44 - return pinctrl_select_state(mux->pinctrl, mux->state_idle); 45 45 + return i2c_mux_pinctrl_select(muxc, muxc->num_adapters); 45 46 } 46 46 - 47 47 - #ifdef CONFIG_OF 48 48 - static int i2c_mux_pinctrl_parse_dt(struct i2c_mux_pinctrl *mux, 49 49 - struct platform_device *pdev) 50 50 - { 51 51 - struct device_node *np = pdev->dev.of_node; 52 52 - int num_names, i, ret; 53 53 - struct device_node *adapter_np; 54 54 - struct i2c_adapter *adapter; 55 55 - 56 56 - if (!np) 57 57 - return 0; 58 58 - 59 59 - mux->pdata = devm_kzalloc(&pdev->dev, sizeof(*mux->pdata), GFP_KERNEL); 60 60 - if (!mux->pdata) 61 61 - return -ENOMEM; 62 62 - 63 63 - num_names = of_property_count_strings(np, "pinctrl-names"); 64 64 - if (num_names < 0) { 65 65 - dev_err(&pdev->dev, "Cannot parse pinctrl-names: %d\n", 66 66 - num_names); 67 67 - return num_names; 68 68 - } 69 69 - 70 70 - mux->pdata->pinctrl_states = devm_kzalloc(&pdev->dev, 71 71 - sizeof(*mux->pdata->pinctrl_states) * num_names, 72 72 - GFP_KERNEL); 73 73 - if (!mux->pdata->pinctrl_states) 74 74 - return -ENOMEM; 75 75 - 76 76 - for (i = 0; i < num_names; i++) { 77 77 - ret = of_property_read_string_index(np, "pinctrl-names", i, 78 78 - &mux->pdata->pinctrl_states[mux->pdata->bus_count]); 79 79 - if (ret < 0) { 80 80 - dev_err(&pdev->dev, "Cannot parse pinctrl-names: %d\n", 81 81 - ret); 82 82 - return ret; 83 83 - } 84 84 - if (!strcmp(mux->pdata->pinctrl_states[mux->pdata->bus_count], 85 85 - "idle")) { 86 86 - if (i != num_names - 1) { 87 87 - dev_err(&pdev->dev, 88 88 - "idle state must be last\n"); 89 89 - return -EINVAL; 90 90 - } 91 91 - mux->pdata->pinctrl_state_idle = "idle"; 92 92 - } else { 93 93 - mux->pdata->bus_count++; 94 94 - } 95 95 - } 96 96 - 97 97 - adapter_np = of_parse_phandle(np, "i2c-parent", 0); 98 98 - if (!adapter_np) { 99 99 - dev_err(&pdev->dev, "Cannot parse i2c-parent\n"); 100 100 - return -ENODEV; 101 101 - } 102 102 - adapter = of_find_i2c_adapter_by_node(adapter_np); 103 103 - of_node_put(adapter_np); 104 104 - if (!adapter) { 105 105 - dev_err(&pdev->dev, "Cannot find parent bus\n"); 106 106 - return -EPROBE_DEFER; 107 107 - } 108 108 - mux->pdata->parent_bus_num = i2c_adapter_id(adapter); 109 109 - put_device(&adapter->dev); 110 110 - 111 111 - return 0; 112 112 - } 113 113 - #else 114 114 - static inline int i2c_mux_pinctrl_parse_dt(struct i2c_mux_pinctrl *mux, 115 115 - struct platform_device *pdev) 116 116 - { 117 117 - return 0; 118 118 - } 119 119 - #endif 120 47 121 48 static struct i2c_adapter *i2c_mux_pinctrl_root_adapter( 122 49 struct pinctrl_state *state) ··· 62 141 return root; 63 142 } 64 143 144 144 + static struct i2c_adapter *i2c_mux_pinctrl_parent_adapter(struct device *dev) 145 145 + { 146 146 + struct device_node *np = dev->of_node; 147 147 + struct device_node *parent_np; 148 148 + struct i2c_adapter *parent; 149 149 + 150 150 + parent_np = of_parse_phandle(np, "i2c-parent", 0); 151 151 + if (!parent_np) { 152 152 + dev_err(dev, "Cannot parse i2c-parent\n"); 153 153 + return ERR_PTR(-ENODEV); 154 154 + } 155 155 + parent = of_find_i2c_adapter_by_node(parent_np); 156 156 + of_node_put(parent_np); 157 157 + if (!parent) 158 158 + return ERR_PTR(-EPROBE_DEFER); 159 159 + 160 160 + return parent; 161 161 + } 162 162 + 65 163 static int i2c_mux_pinctrl_probe(struct platform_device *pdev) 66 164 { 165 165 + struct device *dev = &pdev->dev; 166 166 + struct device_node *np = dev->of_node; 67 167 struct i2c_mux_core *muxc; 68 168 struct i2c_mux_pinctrl *mux; 169 169 + struct i2c_adapter *parent; 69 170 struct i2c_adapter *root; 70 70 - int i, ret; 171 171 + int num_names, i, ret; 172 172 + const char *name; 71 173 72 72 - mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL); 73 73 - if (!mux) { 74 74 - ret = -ENOMEM; 75 75 - goto err; 174 174 + num_names = of_property_count_strings(np, "pinctrl-names"); 175 175 + if (num_names < 0) { 176 176 + dev_err(dev, "Cannot parse pinctrl-names: %d\n", 177 177 + num_names); 178 178 + return num_names; 76 179 } 77 180 78 78 - mux->pdata = dev_get_platdata(&pdev->dev); 79 79 - if (!mux->pdata) { 80 80 - ret = i2c_mux_pinctrl_parse_dt(mux, pdev); 81 81 - if (ret < 0) 82 82 - goto err; 83 83 - } 84 84 - if (!mux->pdata) { 85 85 - dev_err(&pdev->dev, "Missing platform data\n"); 86 86 - ret = -ENODEV; 87 87 - goto err; 88 88 - } 181 181 + parent = i2c_mux_pinctrl_parent_adapter(dev); 182 182 + if (IS_ERR(parent)) 183 183 + return PTR_ERR(parent); 89 184 90 90 - mux->states = devm_kzalloc(&pdev->dev, 91 91 - sizeof(*mux->states) * mux->pdata->bus_count, 92 92 - GFP_KERNEL); 93 93 - if (!mux->states) { 94 94 - dev_err(&pdev->dev, "Cannot allocate states\n"); 95 95 - ret = -ENOMEM; 96 96 - goto err; 97 97 - } 98 98 - 99 99 - muxc = i2c_mux_alloc(NULL, &pdev->dev, mux->pdata->bus_count, 0, 0, 100 100 - i2c_mux_pinctrl_select, NULL); 185 185 + muxc = i2c_mux_alloc(parent, dev, num_names, 186 186 + sizeof(*mux) + num_names * sizeof(*mux->states), 187 187 + 0, i2c_mux_pinctrl_select, NULL); 101 188 if (!muxc) { 102 189 ret = -ENOMEM; 103 103 - goto err; 190 190 + goto err_put_parent; 104 191 } 105 105 - muxc->priv = mux; 192 192 + mux = i2c_mux_priv(muxc); 193 193 + mux->states = (struct pinctrl_state **)(mux + 1); 106 194 107 195 platform_set_drvdata(pdev, muxc); 108 196 109 109 - mux->pinctrl = devm_pinctrl_get(&pdev->dev); 197 197 + mux->pinctrl = devm_pinctrl_get(dev); 110 198 if (IS_ERR(mux->pinctrl)) { 111 199 ret = PTR_ERR(mux->pinctrl); 112 112 - dev_err(&pdev->dev, "Cannot get pinctrl: %d\n", ret); 113 113 - goto err; 200 200 + dev_err(dev, "Cannot get pinctrl: %d\n", ret); 201 201 + goto err_put_parent; 114 202 } 115 115 - for (i = 0; i < mux->pdata->bus_count; i++) { 116 116 - mux->states[i] = pinctrl_lookup_state(mux->pinctrl, 117 117 - mux->pdata->pinctrl_states[i]); 203 203 + 204 204 + for (i = 0; i < num_names; i++) { 205 205 + ret = of_property_read_string_index(np, "pinctrl-names", i, 206 206 + &name); 207 207 + if (ret < 0) { 208 208 + dev_err(dev, "Cannot parse pinctrl-names: %d\n", ret); 209 209 + goto err_put_parent; 210 210 + } 211 211 + 212 212 + mux->states[i] = pinctrl_lookup_state(mux->pinctrl, name); 118 213 if (IS_ERR(mux->states[i])) { 119 214 ret = PTR_ERR(mux->states[i]); 120 120 - dev_err(&pdev->dev, 121 121 - "Cannot look up pinctrl state %s: %d\n", 122 122 - mux->pdata->pinctrl_states[i], ret); 123 123 - goto err; 124 124 - } 125 125 - } 126 126 - if (mux->pdata->pinctrl_state_idle) { 127 127 - mux->state_idle = pinctrl_lookup_state(mux->pinctrl, 128 128 - mux->pdata->pinctrl_state_idle); 129 129 - if (IS_ERR(mux->state_idle)) { 130 130 - ret = PTR_ERR(mux->state_idle); 131 131 - dev_err(&pdev->dev, 132 132 - "Cannot look up pinctrl state %s: %d\n", 133 133 - mux->pdata->pinctrl_state_idle, ret); 134 134 - goto err; 215 215 + dev_err(dev, "Cannot look up pinctrl state %s: %d\n", 216 216 + name, ret); 217 217 + goto err_put_parent; 135 218 } 136 219 220 220 + if (strcmp(name, "idle")) 221 221 + continue; 222 222 + 223 223 + if (i != num_names - 1) { 224 224 + dev_err(dev, "idle state must be last\n"); 225 225 + ret = -EINVAL; 226 226 + goto err_put_parent; 227 227 + } 137 228 muxc->deselect = i2c_mux_pinctrl_deselect; 138 138 - } 139 139 - 140 140 - muxc->parent = i2c_get_adapter(mux->pdata->parent_bus_num); 141 141 - if (!muxc->parent) { 142 142 - dev_err(&pdev->dev, "Parent adapter (%d) not found\n", 143 143 - mux->pdata->parent_bus_num); 144 144 - ret = -EPROBE_DEFER; 145 145 - goto err; 146 229 } 147 230 148 231 root = i2c_root_adapter(&muxc->parent->dev); 149 232 150 233 muxc->mux_locked = true; 151 151 - for (i = 0; i < mux->pdata->bus_count; i++) { 234 234 + for (i = 0; i < num_names; i++) { 152 235 if (root != i2c_mux_pinctrl_root_adapter(mux->states[i])) { 153 236 muxc->mux_locked = false; 154 237 break; 155 238 } 156 239 } 157 157 - if (muxc->mux_locked && mux->pdata->pinctrl_state_idle && 158 158 - root != i2c_mux_pinctrl_root_adapter(mux->state_idle)) 159 159 - muxc->mux_locked = false; 160 160 - 161 240 if (muxc->mux_locked) 162 162 - dev_info(&pdev->dev, "mux-locked i2c mux\n"); 241 241 + dev_info(dev, "mux-locked i2c mux\n"); 163 242 164 164 - for (i = 0; i < mux->pdata->bus_count; i++) { 165 165 - u32 bus = mux->pdata->base_bus_num ? 166 166 - (mux->pdata->base_bus_num + i) : 0; 167 167 - 168 168 - ret = i2c_mux_add_adapter(muxc, bus, i, 0); 243 243 + /* Do not add any adapter for the idle state (if it's there at all). */ 244 244 + for (i = 0; i < num_names - !!muxc->deselect; i++) { 245 245 + ret = i2c_mux_add_adapter(muxc, 0, i, 0); 169 246 if (ret) 170 247 goto err_del_adapter; 171 248 } ··· 172 253 173 254 err_del_adapter: 174 255 i2c_mux_del_adapters(muxc); 175 175 - i2c_put_adapter(muxc->parent); 176 176 - err: 256 256 + err_put_parent: 257 257 + i2c_put_adapter(parent); 258 258 + 177 259 return ret; 178 260 } 179 261 ··· 184 264 185 265 i2c_mux_del_adapters(muxc); 186 266 i2c_put_adapter(muxc->parent); 267 267 + 187 268 return 0; 188 269 } 189 270 190 190 - #ifdef CONFIG_OF 191 271 static const struct of_device_id i2c_mux_pinctrl_of_match[] = { 192 272 { .compatible = "i2c-mux-pinctrl", }, 193 273 {}, 194 274 }; 195 275 MODULE_DEVICE_TABLE(of, i2c_mux_pinctrl_of_match); 196 196 - #endif 197 276 198 277 static struct platform_driver i2c_mux_pinctrl_driver = { 199 278 .driver = {

-41

include/linux/i2c-mux-pinctrl.h

reviewed

··· 1 1 - /* 2 2 - * i2c-mux-pinctrl platform data 3 3 - * 4 4 - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 5 5 - * 6 6 - * This program is free software; you can redistribute it and/or modify it 7 7 - * under the terms and conditions of the GNU General Public License, 8 8 - * version 2, as published by the Free Software Foundation. 9 9 - * 10 10 - * This program is distributed in the hope it will be useful, but WITHOUT 11 11 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 12 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 13 - * more details. 14 14 - * 15 15 - * You should have received a copy of the GNU General Public License 16 16 - * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 17 - */ 18 18 - 19 19 - #ifndef _LINUX_I2C_MUX_PINCTRL_H 20 20 - #define _LINUX_I2C_MUX_PINCTRL_H 21 21 - 22 22 - /** 23 23 - * struct i2c_mux_pinctrl_platform_data - Platform data for i2c-mux-pinctrl 24 24 - * @parent_bus_num: Parent I2C bus number 25 25 - * @base_bus_num: Base I2C bus number for the child busses. 0 for dynamic. 26 26 - * @bus_count: Number of child busses. Also the number of elements in 27 27 - * @pinctrl_states 28 28 - * @pinctrl_states: The names of the pinctrl state to select for each child bus 29 29 - * @pinctrl_state_idle: The pinctrl state to select when no child bus is being 30 30 - * accessed. If NULL, the most recently used pinctrl state will be left 31 31 - * selected. 32 32 - */ 33 33 - struct i2c_mux_pinctrl_platform_data { 34 34 - int parent_bus_num; 35 35 - int base_bus_num; 36 36 - int bus_count; 37 37 - const char **pinctrl_states; 38 38 - const char *pinctrl_state_idle; 39 39 - }; 40 40 - 41 41 - #endif

-145

include/linux/i2c/bfin_twi.h

reviewed

··· 1 1 - /* 2 2 - * i2c-bfin-twi.h - interface to ADI TWI controller 3 3 - * 4 4 - * Copyright 2005-2014 Analog Devices Inc. 5 5 - * 6 6 - * Licensed under the GPL-2 or later. 7 7 - */ 8 8 - 9 9 - #ifndef __I2C_BFIN_TWI_H__ 10 10 - #define __I2C_BFIN_TWI_H__ 11 11 - 12 12 - #include <linux/types.h> 13 13 - #include <linux/i2c.h> 14 14 - 15 15 - /* 16 16 - * ADI twi registers layout 17 17 - */ 18 18 - struct bfin_twi_regs { 19 19 - u16 clkdiv; 20 20 - u16 dummy1; 21 21 - u16 control; 22 22 - u16 dummy2; 23 23 - u16 slave_ctl; 24 24 - u16 dummy3; 25 25 - u16 slave_stat; 26 26 - u16 dummy4; 27 27 - u16 slave_addr; 28 28 - u16 dummy5; 29 29 - u16 master_ctl; 30 30 - u16 dummy6; 31 31 - u16 master_stat; 32 32 - u16 dummy7; 33 33 - u16 master_addr; 34 34 - u16 dummy8; 35 35 - u16 int_stat; 36 36 - u16 dummy9; 37 37 - u16 int_mask; 38 38 - u16 dummy10; 39 39 - u16 fifo_ctl; 40 40 - u16 dummy11; 41 41 - u16 fifo_stat; 42 42 - u16 dummy12; 43 43 - u32 __pad[20]; 44 44 - u16 xmt_data8; 45 45 - u16 dummy13; 46 46 - u16 xmt_data16; 47 47 - u16 dummy14; 48 48 - u16 rcv_data8; 49 49 - u16 dummy15; 50 50 - u16 rcv_data16; 51 51 - u16 dummy16; 52 52 - }; 53 53 - 54 54 - struct bfin_twi_iface { 55 55 - int irq; 56 56 - spinlock_t lock; 57 57 - char read_write; 58 58 - u8 command; 59 59 - u8 *transPtr; 60 60 - int readNum; 61 61 - int writeNum; 62 62 - int cur_mode; 63 63 - int manual_stop; 64 64 - int result; 65 65 - struct i2c_adapter adap; 66 66 - struct completion complete; 67 67 - struct i2c_msg *pmsg; 68 68 - int msg_num; 69 69 - int cur_msg; 70 70 - u16 saved_clkdiv; 71 71 - u16 saved_control; 72 72 - struct bfin_twi_regs __iomem *regs_base; 73 73 - }; 74 74 - 75 75 - /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/ 76 76 - /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 77 77 - #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ 78 78 - #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 79 79 - 80 80 - /* TWI_PRESCALE Masks */ 81 81 - #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ 82 82 - #define TWI_ENA 0x0080 /* TWI Enable */ 83 83 - #define SCCB 0x0200 /* SCCB Compatibility Enable */ 84 84 - 85 85 - /* TWI_SLAVE_CTL Masks */ 86 86 - #define SEN 0x0001 /* Slave Enable */ 87 87 - #define SADD_LEN 0x0002 /* Slave Address Length */ 88 88 - #define STDVAL 0x0004 /* Slave Transmit Data Valid */ 89 89 - #define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */ 90 90 - #define GEN 0x0010 /* General Call Address Matching Enabled */ 91 91 - 92 92 - /* TWI_SLAVE_STAT Masks */ 93 93 - #define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */ 94 94 - #define GCALL 0x0002 /* General Call Indicator */ 95 95 - 96 96 - /* TWI_MASTER_CTL Masks */ 97 97 - #define MEN 0x0001 /* Master Mode Enable */ 98 98 - #define MADD_LEN 0x0002 /* Master Address Length */ 99 99 - #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 100 100 - #define FAST 0x0008 /* Use Fast Mode Timing Specs */ 101 101 - #define STOP 0x0010 /* Issue Stop Condition */ 102 102 - #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ 103 103 - #define DCNT 0x3FC0 /* Data Bytes To Transfer */ 104 104 - #define SDAOVR 0x4000 /* Serial Data Override */ 105 105 - #define SCLOVR 0x8000 /* Serial Clock Override */ 106 106 - 107 107 - /* TWI_MASTER_STAT Masks */ 108 108 - #define MPROG 0x0001 /* Master Transfer In Progress */ 109 109 - #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ 110 110 - #define ANAK 0x0004 /* Address Not Acknowledged */ 111 111 - #define DNAK 0x0008 /* Data Not Acknowledged */ 112 112 - #define BUFRDERR 0x0010 /* Buffer Read Error */ 113 113 - #define BUFWRERR 0x0020 /* Buffer Write Error */ 114 114 - #define SDASEN 0x0040 /* Serial Data Sense */ 115 115 - #define SCLSEN 0x0080 /* Serial Clock Sense */ 116 116 - #define BUSBUSY 0x0100 /* Bus Busy Indicator */ 117 117 - 118 118 - /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ 119 119 - #define SINIT 0x0001 /* Slave Transfer Initiated */ 120 120 - #define SCOMP 0x0002 /* Slave Transfer Complete */ 121 121 - #define SERR 0x0004 /* Slave Transfer Error */ 122 122 - #define SOVF 0x0008 /* Slave Overflow */ 123 123 - #define MCOMP 0x0010 /* Master Transfer Complete */ 124 124 - #define MERR 0x0020 /* Master Transfer Error */ 125 125 - #define XMTSERV 0x0040 /* Transmit FIFO Service */ 126 126 - #define RCVSERV 0x0080 /* Receive FIFO Service */ 127 127 - 128 128 - /* TWI_FIFO_CTRL Masks */ 129 129 - #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 130 130 - #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 131 131 - #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 132 132 - #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ 133 133 - 134 134 - /* TWI_FIFO_STAT Masks */ 135 135 - #define XMTSTAT 0x0003 /* Transmit FIFO Status */ 136 136 - #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ 137 137 - #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ 138 138 - #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ 139 139 - 140 140 - #define RCVSTAT 0x000C /* Receive FIFO Status */ 141 141 - #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 142 142 - #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 143 143 - #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 144 144 - 145 145 - #endif

include/linux/i2c/mlxcpld.h include/linux/platform_data/x86/mlxcpld.h

reviewed

include/linux/i2c/pca954x.h include/linux/platform_data/pca954x.h

reviewed

include/linux/i2c/tc35876x.h include/linux/platform_data/tc35876x.h

reviewed