+13

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c

reviewed

··· 205 205 msecs_to_jiffies(timeout_ms)); 206 206 } 207 207 208 208 + void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell) 209 209 + { 210 210 + struct xarray *xa = &adev->userq_doorbell_xa; 211 211 + struct amdgpu_usermode_queue *queue; 212 212 + unsigned long flags; 213 213 + 214 214 + xa_lock_irqsave(xa, flags); 215 215 + queue = xa_load(xa, doorbell); 216 216 + if (queue) 217 217 + amdgpu_userq_fence_driver_process(queue->fence_drv); 218 218 + xa_unlock_irqrestore(xa, flags); 219 219 + } 220 220 + 208 221 static void amdgpu_userq_init_hang_detect_work(struct amdgpu_usermode_queue *queue) 209 222 { 210 223 INIT_DELAYED_WORK(&queue->hang_detect_work, amdgpu_userq_hang_detect_work);

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h

reviewed

··· 156 156 void amdgpu_userq_pre_reset(struct amdgpu_device *adev); 157 157 int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); 158 158 void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue); 159 159 + void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell); 159 160 160 161 int amdgpu_userq_input_va_validate(struct amdgpu_device *adev, 161 162 struct amdgpu_usermode_queue *queue,

+1 -9

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

reviewed

··· 6523 6523 DRM_DEBUG("IH: CP EOP\n"); 6524 6524 6525 6525 if (adev->enable_mes && doorbell_offset) { 6526 6526 - struct amdgpu_usermode_queue *queue; 6527 6527 - struct xarray *xa = &adev->userq_doorbell_xa; 6528 6528 - unsigned long flags; 6529 6529 - 6530 6530 - xa_lock_irqsave(xa, flags); 6531 6531 - queue = xa_load(xa, doorbell_offset); 6532 6532 - if (queue) 6533 6533 - amdgpu_userq_fence_driver_process(queue->fence_drv); 6534 6534 - xa_unlock_irqrestore(xa, flags); 6526 6526 + amdgpu_userq_process_fence_irq(adev, doorbell_offset); 6535 6527 } else { 6536 6528 me_id = (entry->ring_id & 0x0c) >> 2; 6537 6529 pipe_id = (entry->ring_id & 0x03) >> 0;

+1 -9

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

reviewed

··· 4854 4854 DRM_DEBUG("IH: CP EOP\n"); 4855 4855 4856 4856 if (adev->enable_mes && doorbell_offset) { 4857 4857 - struct xarray *xa = &adev->userq_doorbell_xa; 4858 4858 - struct amdgpu_usermode_queue *queue; 4859 4859 - unsigned long flags; 4860 4860 - 4861 4861 - xa_lock_irqsave(xa, flags); 4862 4862 - queue = xa_load(xa, doorbell_offset); 4863 4863 - if (queue) 4864 4864 - amdgpu_userq_fence_driver_process(queue->fence_drv); 4865 4865 - xa_unlock_irqrestore(xa, flags); 4857 4857 + amdgpu_userq_process_fence_irq(adev, doorbell_offset); 4866 4858 } else { 4867 4859 me_id = (entry->ring_id & 0x0c) >> 2; 4868 4860 pipe_id = (entry->ring_id & 0x03) >> 0;

+1 -10

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

reviewed

··· 3643 3643 DRM_DEBUG("IH: CP EOP\n"); 3644 3644 3645 3645 if (adev->enable_mes && doorbell_offset) { 3646 3646 - struct xarray *xa = &adev->userq_doorbell_xa; 3647 3647 - struct amdgpu_usermode_queue *queue; 3648 3648 - unsigned long flags; 3649 3649 - 3650 3650 - xa_lock_irqsave(xa, flags); 3651 3651 - queue = xa_load(xa, doorbell_offset); 3652 3652 - if (queue) 3653 3653 - amdgpu_userq_fence_driver_process(queue->fence_drv); 3654 3654 - 3655 3655 - xa_unlock_irqrestore(xa, flags); 3646 3646 + amdgpu_userq_process_fence_irq(adev, doorbell_offset); 3656 3647 } else { 3657 3648 me_id = (entry->ring_id & 0x0c) >> 2; 3658 3649 pipe_id = (entry->ring_id & 0x03) >> 0;

+1 -10

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

reviewed

··· 1662 1662 u32 doorbell_offset = entry->src_data[0]; 1663 1663 1664 1664 if (adev->enable_mes && doorbell_offset) { 1665 1665 - struct amdgpu_usermode_queue *queue; 1666 1666 - struct xarray *xa = &adev->userq_doorbell_xa; 1667 1667 - unsigned long flags; 1668 1668 - 1669 1665 doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 1670 1670 - 1671 1671 - xa_lock_irqsave(xa, flags); 1672 1672 - queue = xa_load(xa, doorbell_offset); 1673 1673 - if (queue) 1674 1674 - amdgpu_userq_fence_driver_process(queue->fence_drv); 1675 1675 - xa_unlock_irqrestore(xa, flags); 1666 1666 + amdgpu_userq_process_fence_irq(adev, doorbell_offset); 1676 1667 } 1677 1668 1678 1669 return 0;

+1 -10

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

reviewed

··· 1594 1594 u32 doorbell_offset = entry->src_data[0]; 1595 1595 1596 1596 if (adev->enable_mes && doorbell_offset) { 1597 1597 - struct xarray *xa = &adev->userq_doorbell_xa; 1598 1598 - struct amdgpu_usermode_queue *queue; 1599 1599 - unsigned long flags; 1600 1600 - 1601 1597 doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 1602 1602 - 1603 1603 - xa_lock_irqsave(xa, flags); 1604 1604 - queue = xa_load(xa, doorbell_offset); 1605 1605 - if (queue) 1606 1606 - amdgpu_userq_fence_driver_process(queue->fence_drv); 1607 1607 - xa_unlock_irqrestore(xa, flags); 1598 1598 + amdgpu_userq_process_fence_irq(adev, doorbell_offset); 1608 1599 } 1609 1600 1610 1601 return 0;