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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge branch 'net-stmmac-cleanups-and-low-priority-fixes'
Russell King says:
====================
net: stmmac: cleanups and low priority fixes
Further cleanups and a few low priority fixes:
- Remove duplicated register definitions from header files
- Fix harmless wrong definition used for PTP message type in
descriptors
- Fix norm_set_tx_desc_len_on_ring() off-by-one error (and make
enh_set_tx_desc_len_on_ring() follow a similar pattern.)
Document the buffer size limits. I believe we never call
norm_set_tx_desc_len_on_ring() with 2KiB lengths.
- use u32 rather than unsigned int for 32-bit quantities in
descriptors
- modernise: convert to use FIELD_PREP() rather than separate mask
and shift definitions.
- Reorganise register and register field definitions: registers
defined in address offset order followed by their register field
definitions.
- Remove lots of unused register definitions.
====================
Link: https://patch.msgid.link/aV_q2Kneinrk3Z-W@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+345
-662
-7
drivers/net/ethernet/stmicro/stmmac/descs.h
-7
drivers/net/ethernet/stmicro/stmmac/descs.h
···
32
32
#define RDES0_DESCRIPTOR_ERROR BIT(14)
33
33
#define RDES0_ERROR_SUMMARY BIT(15)
34
34
#define RDES0_FRAME_LEN_MASK GENMASK(29, 16)
35
-
#define RDES0_FRAME_LEN_SHIFT 16
36
35
#define RDES0_DA_FILTER_FAIL BIT(30)
37
36
#define RDES0_OWN BIT(31)
38
37
/* RDES1 */
39
38
#define RDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
40
39
#define RDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
41
-
#define RDES1_BUFFER2_SIZE_SHIFT 11
42
40
#define RDES1_SECOND_ADDRESS_CHAINED BIT(24)
43
41
#define RDES1_END_RING BIT(25)
44
42
#define RDES1_DISABLE_IC BIT(31)
···
51
53
#define ERDES1_SECOND_ADDRESS_CHAINED BIT(14)
52
54
#define ERDES1_END_RING BIT(15)
53
55
#define ERDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
54
-
#define ERDES1_BUFFER2_SIZE_SHIFT 16
55
56
#define ERDES1_DISABLE_IC BIT(31)
56
57
57
58
/* Normal transmit descriptor defines */
···
74
77
/* TDES1 */
75
78
#define TDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
76
79
#define TDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
77
-
#define TDES1_BUFFER2_SIZE_SHIFT 11
78
80
#define TDES1_TIME_STAMP_ENABLE BIT(22)
79
81
#define TDES1_DISABLE_PADDING BIT(23)
80
82
#define TDES1_SECOND_ADDRESS_CHAINED BIT(24)
81
83
#define TDES1_END_RING BIT(25)
82
84
#define TDES1_CRC_DISABLE BIT(26)
83
85
#define TDES1_CHECKSUM_INSERTION_MASK GENMASK(28, 27)
84
-
#define TDES1_CHECKSUM_INSERTION_SHIFT 27
85
86
#define TDES1_FIRST_SEGMENT BIT(29)
86
87
#define TDES1_LAST_SEGMENT BIT(30)
87
88
#define TDES1_INTERRUPT BIT(31)
···
104
109
#define ETDES0_SECOND_ADDRESS_CHAINED BIT(20)
105
110
#define ETDES0_END_RING BIT(21)
106
111
#define ETDES0_CHECKSUM_INSERTION_MASK GENMASK(23, 22)
107
-
#define ETDES0_CHECKSUM_INSERTION_SHIFT 22
108
112
#define ETDES0_TIME_STAMP_ENABLE BIT(25)
109
113
#define ETDES0_DISABLE_PADDING BIT(26)
110
114
#define ETDES0_CRC_DISABLE BIT(27)
···
114
120
/* TDES1 */
115
121
#define ETDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)
116
122
#define ETDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
117
-
#define ETDES1_BUFFER2_SIZE_SHIFT 16
118
123
119
124
/* Extended Receive descriptor definitions */
120
125
#define ERDES4_IP_PAYLOAD_TYPE_MASK GENMASK(6, 2)
+28
-20
drivers/net/ethernet/stmicro/stmmac/descs_com.h
+28
-20
drivers/net/ethernet/stmicro/stmmac/descs_com.h
···
23
23
int bfsize)
24
24
{
25
25
if (bfsize == BUF_SIZE_16KiB)
26
-
p->des1 |= cpu_to_le32((BUF_SIZE_8KiB
27
-
<< ERDES1_BUFFER2_SIZE_SHIFT)
28
-
& ERDES1_BUFFER2_SIZE_MASK);
26
+
p->des1 |= cpu_to_le32(FIELD_PREP(ERDES1_BUFFER2_SIZE_MASK,
27
+
BUF_SIZE_8KiB));
29
28
30
29
if (end)
31
30
p->des1 |= cpu_to_le32(ERDES1_END_RING);
···
38
39
p->des0 &= cpu_to_le32(~ETDES0_END_RING);
39
40
}
40
41
42
+
/* The maximum buffer 1 size is 8KiB - 1. However, we limit to 4KiB. */
41
43
static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
42
44
{
43
-
if (unlikely(len > BUF_SIZE_4KiB)) {
44
-
p->des1 |= cpu_to_le32((((len - BUF_SIZE_4KiB)
45
-
<< ETDES1_BUFFER2_SIZE_SHIFT)
46
-
& ETDES1_BUFFER2_SIZE_MASK) | (BUF_SIZE_4KiB
47
-
& ETDES1_BUFFER1_SIZE_MASK));
48
-
} else
49
-
p->des1 |= cpu_to_le32((len & ETDES1_BUFFER1_SIZE_MASK));
45
+
unsigned int buffer1_max_length = BUF_SIZE_4KiB;
46
+
47
+
if (unlikely(len > buffer1_max_length)) {
48
+
p->des1 |= cpu_to_le32(FIELD_PREP(ETDES1_BUFFER2_SIZE_MASK,
49
+
len - buffer1_max_length) |
50
+
FIELD_PREP(ETDES1_BUFFER1_SIZE_MASK,
51
+
buffer1_max_length));
52
+
} else {
53
+
p->des1 |= cpu_to_le32(FIELD_PREP(ETDES1_BUFFER1_SIZE_MASK,
54
+
len));
55
+
}
50
56
}
51
57
52
58
/* Normal descriptors */
···
61
57
int bfsize2;
62
58
63
59
bfsize2 = min(bfsize - BUF_SIZE_2KiB + 1, BUF_SIZE_2KiB - 1);
64
-
p->des1 |= cpu_to_le32((bfsize2 << RDES1_BUFFER2_SIZE_SHIFT)
65
-
& RDES1_BUFFER2_SIZE_MASK);
60
+
p->des1 |= cpu_to_le32(FIELD_PREP(RDES1_BUFFER2_SIZE_MASK,
61
+
bfsize2));
66
62
}
67
63
68
64
if (end)
···
77
73
p->des1 &= cpu_to_le32(~TDES1_END_RING);
78
74
}
79
75
76
+
/* The maximum buffer 1 size is 2KiB - 1, limited by the mask width */
80
77
static inline void norm_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
81
78
{
82
-
if (unlikely(len > BUF_SIZE_2KiB)) {
83
-
unsigned int buffer1 = (BUF_SIZE_2KiB - 1)
84
-
& TDES1_BUFFER1_SIZE_MASK;
85
-
p->des1 |= cpu_to_le32((((len - buffer1)
86
-
<< TDES1_BUFFER2_SIZE_SHIFT)
87
-
& TDES1_BUFFER2_SIZE_MASK) | buffer1);
88
-
} else
89
-
p->des1 |= cpu_to_le32((len & TDES1_BUFFER1_SIZE_MASK));
79
+
unsigned int buffer1_max_length = BUF_SIZE_2KiB - 1;
80
+
81
+
if (unlikely(len > buffer1_max_length)) {
82
+
p->des1 |= cpu_to_le32(FIELD_PREP(TDES1_BUFFER2_SIZE_MASK,
83
+
len - buffer1_max_length) |
84
+
FIELD_PREP(TDES1_BUFFER1_SIZE_MASK,
85
+
buffer1_max_length));
86
+
} else {
87
+
p->des1 |= cpu_to_le32(FIELD_PREP(TDES1_BUFFER1_SIZE_MASK,
88
+
len));
89
+
}
90
90
}
91
91
92
92
/* Specific functions used for Chain mode */
+2
-3
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+2
-3
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
···
192
192
value |= DMA_BUS_MODE_MAXPBL;
193
193
194
194
value |= DMA_BUS_MODE_USP;
195
-
value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
196
-
value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
197
-
value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
195
+
value = u32_replace_bits(value, txpbl, DMA_BUS_MODE_PBL_MASK);
196
+
value = u32_replace_bits(value, rxpbl, DMA_BUS_MODE_RPBL_MASK);
198
197
199
198
/* Set the Fixed burst mode */
200
199
if (dma_cfg->fixed_burst)
+2
-3
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+2
-3
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
···
367
367
.use_nsecs = false,
368
368
};
369
369
370
-
num_snapshot = (readl(ioaddr + XGMAC_TIMESTAMP_STATUS) &
371
-
XGMAC_TIMESTAMP_ATSNS_MASK) >>
372
-
XGMAC_TIMESTAMP_ATSNS_SHIFT;
370
+
num_snapshot = FIELD_GET(XGMAC_TIMESTAMP_ATSNS_MASK,
371
+
readl(ioaddr + XGMAC_TIMESTAMP_STATUS));
373
372
374
373
/* Repeat until the timestamps are from the FIFO last segment */
375
374
for (i = 0; i < num_snapshot; i++) {
+2
-34
drivers/net/ethernet/stmicro/stmmac/dwmac100.h
+2
-34
drivers/net/ethernet/stmicro/stmmac/dwmac100.h
···
30
30
#define MAC_VLAN2 0x00000024 /* VLAN2 Tag */
31
31
32
32
/* MAC CTRL defines */
33
-
#define MAC_CONTROL_RA 0x80000000 /* Receive All Mode */
34
-
#define MAC_CONTROL_BLE 0x40000000 /* Endian Mode */
35
33
#define MAC_CONTROL_HBD 0x10000000 /* Heartbeat Disable */
36
34
#define MAC_CONTROL_PS 0x08000000 /* Port Select */
37
-
#define MAC_CONTROL_DRO 0x00800000 /* Disable Receive Own */
38
-
#define MAC_CONTROL_EXT_LOOPBACK 0x00400000 /* Reserved (ext loopback?) */
39
35
#define MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */
40
36
#define MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */
41
37
#define MAC_CONTROL_PM 0x00080000 /* Pass All Multicast */
42
38
#define MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */
43
39
#define MAC_CONTROL_IF 0x00020000 /* Inverse Filtering */
44
-
#define MAC_CONTROL_PB 0x00010000 /* Pass Bad Frames */
45
40
#define MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */
46
41
#define MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */
47
-
#define MAC_CONTROL_LCC 0x00001000 /* Late Collision Control */
48
-
#define MAC_CONTROL_DBF 0x00000800 /* Disable Broadcast Frames */
49
-
#define MAC_CONTROL_DRTY 0x00000400 /* Disable Retry */
50
-
#define MAC_CONTROL_ASTP 0x00000100 /* Automatic Pad Stripping */
51
-
#define MAC_CONTROL_BOLMT_10 0x00000000 /* Back Off Limit 10 */
52
-
#define MAC_CONTROL_BOLMT_8 0x00000040 /* Back Off Limit 8 */
53
-
#define MAC_CONTROL_BOLMT_4 0x00000080 /* Back Off Limit 4 */
54
-
#define MAC_CONTROL_BOLMT_1 0x000000c0 /* Back Off Limit 1 */
55
-
#define MAC_CONTROL_DC 0x00000020 /* Deferral Check */
56
-
#define MAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
57
-
#define MAC_CONTROL_RE 0x00000004 /* Receiver Enable */
58
42
59
43
#define MAC_CORE_INIT (MAC_CONTROL_HBD)
60
44
61
45
/* MAC FLOW CTRL defines */
62
-
#define MAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
63
-
#define MAC_FLOW_CTRL_PT_SHIFT 16
64
-
#define MAC_FLOW_CTRL_PASS 0x00000004 /* Pass Control Frames */
46
+
#define MAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */
65
47
#define MAC_FLOW_CTRL_ENABLE 0x00000002 /* Flow Control Enable */
66
-
#define MAC_FLOW_CTRL_PAUSE 0x00000001 /* Flow Control Busy ... */
67
-
68
-
/* MII ADDR defines */
69
-
#define MAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
70
-
#define MAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
71
48
72
49
/*----------------------------------------------------------------------------
73
50
* DMA BLOCK defines
74
51
*---------------------------------------------------------------------------*/
75
52
76
53
/* DMA Bus Mode register defines */
77
-
#define DMA_BUS_MODE_DBO 0x00100000 /* Descriptor Byte Ordering */
78
-
#define DMA_BUS_MODE_BLE 0x00000080 /* Big Endian/Little Endian */
79
-
#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
80
-
#define DMA_BUS_MODE_PBL_SHIFT 8
81
-
#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
82
-
#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
83
-
#define DMA_BUS_MODE_BAR_BUS 0x00000002 /* Bar-Bus Arbitration */
54
+
#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */
84
55
#define DMA_BUS_MODE_DEFAULT 0x00000000
85
-
86
-
/* DMA Control register defines */
87
-
#define DMA_CONTROL_SF 0x00200000 /* Store And Forward */
88
56
89
57
/* Transmit Threshold Control */
90
58
enum ttc_control {
+3
-65
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+3
-65
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
···
20
20
#define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
21
21
#define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
22
22
#define GMAC_DEBUG 0x00000024 /* GMAC debug register */
23
-
#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
24
23
25
24
#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
26
-
#define GMAC_INT_STATUS_PMT BIT(3)
27
-
#define GMAC_INT_STATUS_MMCIS BIT(4)
28
25
#define GMAC_INT_STATUS_MMCRIS BIT(5)
29
26
#define GMAC_INT_STATUS_MMCTIS BIT(6)
30
27
#define GMAC_INT_STATUS_MMCCSUM BIT(7)
31
-
#define GMAC_INT_STATUS_TSTAMP BIT(9)
32
28
#define GMAC_INT_STATUS_LPIIS BIT(10)
33
29
34
30
/* interrupt mask register */
···
72
76
/* SGMII/RGMII status register */
73
77
#define GMAC_RGSMIIIS_LNKMODE BIT(0)
74
78
#define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
75
-
#define GMAC_RGSMIIIS_SPEED_SHIFT 1
76
79
#define GMAC_RGSMIIIS_LNKSTS BIT(3)
77
80
#define GMAC_RGSMIIIS_JABTO BIT(4)
78
81
#define GMAC_RGSMIIIS_FALSECARDET BIT(5)
···
85
90
86
91
/* GMAC Configuration defines */
87
92
#define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */
88
-
#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
89
-
#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */
90
93
#define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */
91
94
#define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
92
95
#define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
···
96
103
#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */
97
104
#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
98
105
#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
99
-
#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */
100
106
#define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
101
107
#define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */
102
108
#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
103
-
#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */
104
-
#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */
105
-
#define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */
106
-
#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */
107
-
#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
108
-
#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
109
109
110
110
#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | \
111
111
GMAC_CONTROL_BE | GMAC_CONTROL_DCRS)
112
112
113
113
/* GMAC Frame Filter defines */
114
114
#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
115
-
#define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
116
115
#define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
117
-
#define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
118
116
#define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
119
-
#define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
120
117
#define GMAC_FRAME_FILTER_PCF 0x00000080 /* Pass Control frames */
121
-
#define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
122
-
#define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
123
118
#define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
124
119
#define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
125
-
/* GMII ADDR defines */
126
-
#define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
127
-
#define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
128
120
/* GMAC FLOW CTRL defines */
129
-
#define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
130
-
#define GMAC_FLOW_CTRL_PT_SHIFT 16
121
+
#define GMAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */
131
122
#define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */
132
123
#define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
133
124
#define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
134
-
#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
135
125
136
126
/* DEBUG Register defines */
137
127
/* MTL TxStatus FIFO */
···
123
147
#define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
124
148
/* MTL Tx FIFO Read Controller Status */
125
149
#define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20)
126
-
#define GMAC_DEBUG_TRCSTS_SHIFT 20
127
-
#define GMAC_DEBUG_TRCSTS_IDLE 0
128
150
#define GMAC_DEBUG_TRCSTS_READ 1
129
151
#define GMAC_DEBUG_TRCSTS_TXW 2
130
152
#define GMAC_DEBUG_TRCSTS_WRITE 3
131
153
#define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */
132
154
/* MAC Transmit Frame Controller Status */
133
155
#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
134
-
#define GMAC_DEBUG_TFCSTS_SHIFT 17
135
-
#define GMAC_DEBUG_TFCSTS_IDLE 0
136
156
#define GMAC_DEBUG_TFCSTS_WAIT 1
137
157
#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
138
158
#define GMAC_DEBUG_TFCSTS_XFER 3
139
159
/* MAC GMII or MII Transmit Protocol Engine Status */
140
160
#define GMAC_DEBUG_TPESTS BIT(16)
141
161
#define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
142
-
#define GMAC_DEBUG_RXFSTS_SHIFT 8
143
162
#define GMAC_DEBUG_RXFSTS_EMPTY 0
144
163
#define GMAC_DEBUG_RXFSTS_BT 1
145
164
#define GMAC_DEBUG_RXFSTS_AT 2
146
165
#define GMAC_DEBUG_RXFSTS_FULL 3
147
166
#define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */
148
-
#define GMAC_DEBUG_RRCSTS_SHIFT 5
149
167
#define GMAC_DEBUG_RRCSTS_IDLE 0
150
168
#define GMAC_DEBUG_RRCSTS_RDATA 1
151
169
#define GMAC_DEBUG_RRCSTS_RSTAT 2
···
147
177
#define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */
148
178
/* MAC Receive Frame Controller FIFO Status */
149
179
#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
150
-
#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
151
180
/* MAC GMII or MII Receive Protocol Engine Status */
152
181
#define GMAC_DEBUG_RPESTS BIT(0)
153
182
154
183
/*--- DMA BLOCK defines ---*/
155
184
/* DMA Bus Mode register defines */
156
-
#define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */
157
-
#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
158
-
#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
159
185
/* Programmable burst length (passed thorugh platform)*/
160
-
#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
161
-
#define DMA_BUS_MODE_PBL_SHIFT 8
186
+
#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */
162
187
#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
163
188
164
189
enum rx_tx_priority_ratio {
···
164
199
165
200
#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
166
201
#define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */
167
-
#define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */
168
-
#define DMA_BUS_MODE_RPBL_SHIFT 17
202
+
#define DMA_BUS_MODE_RPBL_MASK GENMASK(22, 17) /* Rx-Programmable Burst Len */
169
203
#define DMA_BUS_MODE_USP 0x00800000
170
204
#define DMA_BUS_MODE_MAXPBL 0x01000000
171
205
#define DMA_BUS_MODE_AAL 0x02000000
172
206
173
207
/* DMA CRS Control and Status Register Mapping */
174
-
#define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */
175
-
#define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */
176
-
/* DMA Bus Mode register defines */
177
-
#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
178
-
#define DMA_BUS_PR_RATIO_SHIFT 14
179
-
#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
180
208
181
209
/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
182
210
/* Disable Drop TCP/IP csum error */
183
-
#define DMA_CONTROL_DT 0x04000000
184
211
#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */
185
212
#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */
186
213
/* Threshold for Activating the FC */
···
204
247
#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff
205
248
206
249
#define DMA_CONTROL_EFC 0x00000100
207
-
#define DMA_CONTROL_FEF 0x00000080
208
-
#define DMA_CONTROL_FUF 0x00000040
209
250
210
251
/* Receive flow control activation field
211
252
* RFA field in DMA control register, bits 23,10:9
···
240
285
*/
241
286
242
287
#define RFA_FULL_MINUS_1K 0x00000000
243
-
#define RFA_FULL_MINUS_2K 0x00000200
244
-
#define RFA_FULL_MINUS_3K 0x00000400
245
-
#define RFA_FULL_MINUS_4K 0x00000600
246
-
#define RFA_FULL_MINUS_5K 0x00800000
247
-
#define RFA_FULL_MINUS_6K 0x00800200
248
-
#define RFA_FULL_MINUS_7K 0x00800400
249
288
250
-
#define RFD_FULL_MINUS_1K 0x00000000
251
289
#define RFD_FULL_MINUS_2K 0x00000800
252
-
#define RFD_FULL_MINUS_3K 0x00001000
253
-
#define RFD_FULL_MINUS_4K 0x00001800
254
-
#define RFD_FULL_MINUS_5K 0x00400000
255
-
#define RFD_FULL_MINUS_6K 0x00400800
256
-
#define RFD_FULL_MINUS_7K 0x00401000
257
290
258
291
enum rtc_control {
259
292
DMA_CONTROL_RTC_64 = 0x00000000,
···
254
311
#define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */
255
312
256
313
/* MMC registers offset */
257
-
#define GMAC_MMC_CTRL 0x100
258
-
#define GMAC_MMC_RX_INTR 0x104
259
-
#define GMAC_MMC_TX_INTR 0x108
260
-
#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
261
314
#define GMAC_EXTHASH_BASE 0x500
262
315
263
316
/* PTP and timestamping registers */
264
317
265
318
#define GMAC3_X_ATSNS GENMASK(29, 25)
266
-
#define GMAC3_X_ATSNS_SHIFT 25
267
319
268
320
#define GMAC_PTP_TCR_ATSFC BIT(24)
269
321
#define GMAC_PTP_TCR_ATSEN0 BIT(25)
+9
-12
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+9
-12
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
···
242
242
243
243
if (duplex) {
244
244
pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
245
-
flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
245
+
flow |= FIELD_PREP(GMAC_FLOW_CTRL_PT_MASK, pause_time);
246
246
}
247
247
248
248
writel(flow, ioaddr + GMAC_FLOW_CTRL);
···
378
378
if (value & GMAC_DEBUG_TWCSTS)
379
379
x->mmtl_fifo_ctrl++;
380
380
if (value & GMAC_DEBUG_TRCSTS_MASK) {
381
-
u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
382
-
>> GMAC_DEBUG_TRCSTS_SHIFT;
381
+
u32 trcsts = FIELD_GET(GMAC_DEBUG_TRCSTS_MASK, value);
382
+
383
383
if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
384
384
x->mtl_tx_fifo_read_ctrl_write++;
385
385
else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
···
392
392
if (value & GMAC_DEBUG_TXPAUSED)
393
393
x->mac_tx_in_pause++;
394
394
if (value & GMAC_DEBUG_TFCSTS_MASK) {
395
-
u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
396
-
>> GMAC_DEBUG_TFCSTS_SHIFT;
395
+
u32 tfcsts = FIELD_GET(GMAC_DEBUG_TFCSTS_MASK, value);
397
396
398
397
if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
399
398
x->mac_tx_frame_ctrl_xfer++;
···
406
407
if (value & GMAC_DEBUG_TPESTS)
407
408
x->mac_gmii_tx_proto_engine++;
408
409
if (value & GMAC_DEBUG_RXFSTS_MASK) {
409
-
u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
410
-
>> GMAC_DEBUG_RRCSTS_SHIFT;
410
+
u32 rxfsts = FIELD_GET(GMAC_DEBUG_RXFSTS_MASK, value);
411
411
412
412
if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
413
413
x->mtl_rx_fifo_fill_level_full++;
···
418
420
x->mtl_rx_fifo_fill_level_empty++;
419
421
}
420
422
if (value & GMAC_DEBUG_RRCSTS_MASK) {
421
-
u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
422
-
GMAC_DEBUG_RRCSTS_SHIFT;
423
+
u32 rrcsts = FIELD_GET(GMAC_DEBUG_RRCSTS_MASK, value);
423
424
424
425
if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
425
426
x->mtl_rx_fifo_read_ctrl_flush++;
···
432
435
if (value & GMAC_DEBUG_RWCSTS)
433
436
x->mtl_rx_fifo_ctrl_active++;
434
437
if (value & GMAC_DEBUG_RFCFCSTS_MASK)
435
-
x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
436
-
>> GMAC_DEBUG_RFCFCSTS_SHIFT;
438
+
x->mac_rx_frame_ctrl_fifo = FIELD_GET(GMAC_DEBUG_RFCFCSTS_MASK,
439
+
value);
437
440
if (value & GMAC_DEBUG_RPESTS)
438
441
x->mac_gmii_rx_proto_engine++;
439
442
}
···
531
534
if (!(priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN))
532
535
return;
533
536
534
-
num_snapshot = (ts_status & GMAC3_X_ATSNS) >> GMAC3_X_ATSNS_SHIFT;
537
+
num_snapshot = FIELD_GET(GMAC3_X_ATSNS, ts_status);
535
538
536
539
for (i = 0; i < num_snapshot; i++) {
537
540
read_lock_irqsave(&priv->ptp_lock, flags);
+6
-10
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+6
-10
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
···
28
28
if (axi->axi_xit_frm)
29
29
value |= DMA_AXI_LPI_XIT_FRM;
30
30
31
-
value &= ~DMA_AXI_WR_OSR_LMT;
32
-
value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) <<
33
-
DMA_AXI_WR_OSR_LMT_SHIFT;
34
-
35
-
value &= ~DMA_AXI_RD_OSR_LMT;
36
-
value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) <<
37
-
DMA_AXI_RD_OSR_LMT_SHIFT;
31
+
value = u32_replace_bits(value, axi->axi_wr_osr_lmt,
32
+
DMA_AXI_WR_OSR_LMT);
33
+
value = u32_replace_bits(value, axi->axi_rd_osr_lmt,
34
+
DMA_AXI_RD_OSR_LMT);
38
35
39
36
/* Depending on the UNDEF bit the Master AXI will perform any burst
40
37
* length according to the BLEN programmed (by default all BLEN are
···
61
64
if (dma_cfg->pblx8)
62
65
value |= DMA_BUS_MODE_MAXPBL;
63
66
value |= DMA_BUS_MODE_USP;
64
-
value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
65
-
value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
66
-
value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
67
+
value = u32_replace_bits(value, txpbl, DMA_BUS_MODE_PBL_MASK);
68
+
value = u32_replace_bits(value, rxpbl, DMA_BUS_MODE_RPBL_MASK);
67
69
68
70
/* Set the Fixed burst mode */
69
71
if (dma_cfg->fixed_burst)
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+2
-1
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
+2
-1
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
···
22
22
struct stmmac_dma_cfg *dma_cfg)
23
23
{
24
24
/* Enable Application Access by writing to DMA CSR0 */
25
-
writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
25
+
writel(DMA_BUS_MODE_DEFAULT |
26
+
FIELD_PREP(DMA_BUS_MODE_PBL_MASK, dma_cfg->pbl),
26
27
ioaddr + DMA_BUS_MODE);
27
28
28
29
/* Mask interrupts by writing to CSR7 */
+15
-64
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+15
-64
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
···
95
95
96
96
/* MAC Flow Control TX */
97
97
#define GMAC_TX_FLOW_CTRL_TFE BIT(1)
98
-
#define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
98
+
#define GMAC_TX_FLOW_CTRL_PT_MASK GENMASK(31, 16)
99
99
100
100
/* MAC Interrupt bitmap*/
101
101
#define GMAC_INT_RGSMIIS BIT(0)
···
142
142
143
143
/* MAC Debug bitmap */
144
144
#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
145
-
#define GMAC_DEBUG_TFCSTS_SHIFT 17
146
145
#define GMAC_DEBUG_TFCSTS_IDLE 0
147
146
#define GMAC_DEBUG_TFCSTS_WAIT 1
148
147
#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
149
148
#define GMAC_DEBUG_TFCSTS_XFER 3
150
149
#define GMAC_DEBUG_TPESTS BIT(16)
151
150
#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
152
-
#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
153
151
#define GMAC_DEBUG_RPESTS BIT(0)
154
152
155
153
/* MAC config */
156
154
#define GMAC_CONFIG_ARPEN BIT(31)
157
155
#define GMAC_CONFIG_SARC GENMASK(30, 28)
158
-
#define GMAC_CONFIG_SARC_SHIFT 28
159
156
#define GMAC_CONFIG_IPC BIT(27)
160
157
#define GMAC_CONFIG_IPG GENMASK(26, 24)
161
-
#define GMAC_CONFIG_IPG_SHIFT 24
162
158
#define GMAC_CONFIG_2K BIT(22)
163
159
#define GMAC_CONFIG_ACS BIT(20)
164
160
#define GMAC_CONFIG_BE BIT(18)
···
162
166
#define GMAC_CONFIG_JE BIT(16)
163
167
#define GMAC_CONFIG_PS BIT(15)
164
168
#define GMAC_CONFIG_FES BIT(14)
165
-
#define GMAC_CONFIG_FES_SHIFT 14
166
169
#define GMAC_CONFIG_DM BIT(13)
167
170
#define GMAC_CONFIG_LM BIT(12)
168
171
#define GMAC_CONFIG_DCRS BIT(9)
···
170
175
171
176
/* MAC extended config */
172
177
#define GMAC_CONFIG_EIPG GENMASK(29, 25)
173
-
#define GMAC_CONFIG_EIPG_SHIFT 25
174
178
#define GMAC_CONFIG_EIPG_EN BIT(24)
175
179
#define GMAC_CONFIG_HDSMS GENMASK(22, 20)
176
-
#define GMAC_CONFIG_HDSMS_SHIFT 20
177
-
#define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT)
180
+
#define GMAC_CONFIG_HDSMS_256 FIELD_PREP_CONST(GMAC_CONFIG_HDSMS, 0x2)
178
181
179
182
/* MAC HW features0 bitmap */
180
183
#define GMAC_HW_FEAT_SAVLANINS BIT(27)
···
235
242
236
243
/* MAC HW ADDR regs */
237
244
#define GMAC_HI_DCS GENMASK(18, 16)
238
-
#define GMAC_HI_DCS_SHIFT 16
239
245
#define GMAC_HI_REG_AE BIT(31)
240
246
241
247
/* L3/L4 Filters regs */
···
249
257
#define GMAC_L3SAM0 BIT(2)
250
258
#define GMAC_L3PEN0 BIT(0)
251
259
#define GMAC_L4DP0 GENMASK(31, 16)
252
-
#define GMAC_L4DP0_SHIFT 16
253
260
#define GMAC_L4SP0 GENMASK(15, 0)
254
261
255
262
/* MAC Timestamp Status */
···
305
314
#define MTL_OP_MODE_TSF BIT(1)
306
315
307
316
#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
308
-
#define MTL_OP_MODE_TQS_SHIFT 16
309
317
310
-
#define MTL_OP_MODE_TTC_MASK 0x70
311
-
#define MTL_OP_MODE_TTC_SHIFT 4
312
-
313
-
#define MTL_OP_MODE_TTC_32 0
314
-
#define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
315
-
#define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
316
-
#define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
317
-
#define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
318
-
#define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
319
-
#define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
320
-
#define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
318
+
#define MTL_OP_MODE_TTC_MASK GENMASK(6, 4)
319
+
#define MTL_OP_MODE_TTC_32 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 0)
320
+
#define MTL_OP_MODE_TTC_64 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 1)
321
+
#define MTL_OP_MODE_TTC_96 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 2)
322
+
#define MTL_OP_MODE_TTC_128 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 3)
323
+
#define MTL_OP_MODE_TTC_192 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 4)
324
+
#define MTL_OP_MODE_TTC_256 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 5)
325
+
#define MTL_OP_MODE_TTC_384 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 6)
326
+
#define MTL_OP_MODE_TTC_512 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 7)
321
327
322
328
#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
323
-
#define MTL_OP_MODE_RQS_SHIFT 20
324
329
325
330
#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
326
-
#define MTL_OP_MODE_RFD_SHIFT 14
327
331
328
332
#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
329
-
#define MTL_OP_MODE_RFA_SHIFT 8
330
333
331
334
#define MTL_OP_MODE_EHFC BIT(7)
332
335
#define MTL_OP_MODE_DIS_TCP_EF BIT(6)
333
336
334
337
#define MTL_OP_MODE_RTC_MASK GENMASK(1, 0)
335
-
#define MTL_OP_MODE_RTC_SHIFT 0
336
338
337
-
#define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
338
-
#define MTL_OP_MODE_RTC_64 0
339
-
#define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
340
-
#define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
339
+
#define MTL_OP_MODE_RTC_32 FIELD_PREP(MTL_OP_MODE_RTC_MASK, 1)
340
+
#define MTL_OP_MODE_RTC_64 FIELD_PREP(MTL_OP_MODE_RTC_MASK, 0)
341
+
#define MTL_OP_MODE_RTC_96 FIELD_PREP(MTL_OP_MODE_RTC_MASK, 2)
342
+
#define MTL_OP_MODE_RTC_128 FIELD_PREP(MTL_OP_MODE_RTC_MASK, 3)
341
343
342
344
/* MTL ETS Control register */
343
345
#define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
···
435
451
436
452
/* MTL debug: Tx FIFO Read Controller Status */
437
453
#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
438
-
#define MTL_DEBUG_TRCSTS_SHIFT 1
439
454
#define MTL_DEBUG_TRCSTS_IDLE 0
440
455
#define MTL_DEBUG_TRCSTS_READ 1
441
456
#define MTL_DEBUG_TRCSTS_TXW 2
···
443
460
444
461
/* MAC debug: GMII or MII Transmit Protocol Engine Status */
445
462
#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
446
-
#define MTL_DEBUG_RXFSTS_SHIFT 4
447
463
#define MTL_DEBUG_RXFSTS_EMPTY 0
448
464
#define MTL_DEBUG_RXFSTS_BT 1
449
465
#define MTL_DEBUG_RXFSTS_AT 2
450
466
#define MTL_DEBUG_RXFSTS_FULL 3
451
467
#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
452
-
#define MTL_DEBUG_RRCSTS_SHIFT 1
453
468
#define MTL_DEBUG_RRCSTS_IDLE 0
454
469
#define MTL_DEBUG_RRCSTS_RDATA 1
455
470
#define MTL_DEBUG_RRCSTS_RSTAT 2
···
466
485
/* To dump the core regs excluding the Address Registers */
467
486
#define GMAC_REG_NUM 132
468
487
469
-
/* MTL debug */
470
-
#define MTL_DEBUG_TXSTSFSTS BIT(5)
471
-
#define MTL_DEBUG_TXFSTS BIT(4)
472
-
#define MTL_DEBUG_TWCSTS BIT(3)
473
-
474
-
/* MTL debug: Tx FIFO Read Controller Status */
475
-
#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
476
-
#define MTL_DEBUG_TRCSTS_SHIFT 1
477
-
#define MTL_DEBUG_TRCSTS_IDLE 0
478
-
#define MTL_DEBUG_TRCSTS_READ 1
479
-
#define MTL_DEBUG_TRCSTS_TXW 2
480
-
#define MTL_DEBUG_TRCSTS_WRITE 3
481
-
#define MTL_DEBUG_TXPAUSED BIT(0)
482
-
483
-
/* MAC debug: GMII or MII Transmit Protocol Engine Status */
484
-
#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
485
-
#define MTL_DEBUG_RXFSTS_SHIFT 4
486
-
#define MTL_DEBUG_RXFSTS_EMPTY 0
487
-
#define MTL_DEBUG_RXFSTS_BT 1
488
-
#define MTL_DEBUG_RXFSTS_AT 2
489
-
#define MTL_DEBUG_RXFSTS_FULL 3
490
-
#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
491
-
#define MTL_DEBUG_RRCSTS_SHIFT 1
492
-
#define MTL_DEBUG_RRCSTS_IDLE 0
493
-
#define MTL_DEBUG_RRCSTS_RDATA 1
494
-
#define MTL_DEBUG_RRCSTS_RSTAT 2
495
-
#define MTL_DEBUG_RRCSTS_FLUSH 3
496
-
#define MTL_DEBUG_RWCSTS BIT(0)
497
-
498
488
/* SGMII/RGMII status register */
499
489
#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
500
490
#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
501
491
#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
502
492
#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
503
493
#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
504
-
#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
505
494
#define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
506
495
#define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
507
496
#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
+12
-16
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+12
-16
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
···
572
572
flow = GMAC_TX_FLOW_CTRL_TFE;
573
573
574
574
if (duplex)
575
-
flow |=
576
-
(pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
575
+
flow |= FIELD_PREP(GMAC_TX_FLOW_CTRL_PT_MASK,
576
+
pause_time);
577
577
578
578
writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
579
579
}
···
681
681
if (value & MTL_DEBUG_TWCSTS)
682
682
x->mmtl_fifo_ctrl++;
683
683
if (value & MTL_DEBUG_TRCSTS_MASK) {
684
-
u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
685
-
>> MTL_DEBUG_TRCSTS_SHIFT;
684
+
u32 trcsts = FIELD_GET(MTL_DEBUG_TRCSTS_MASK, value);
685
+
686
686
if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
687
687
x->mtl_tx_fifo_read_ctrl_write++;
688
688
else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
···
700
700
value = readl(ioaddr + MTL_CHAN_RX_DEBUG(dwmac4_addrs, queue));
701
701
702
702
if (value & MTL_DEBUG_RXFSTS_MASK) {
703
-
u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
704
-
>> MTL_DEBUG_RRCSTS_SHIFT;
703
+
u32 rxfsts = FIELD_GET(MTL_DEBUG_RXFSTS_MASK, value);
705
704
706
705
if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
707
706
x->mtl_rx_fifo_fill_level_full++;
···
712
713
x->mtl_rx_fifo_fill_level_empty++;
713
714
}
714
715
if (value & MTL_DEBUG_RRCSTS_MASK) {
715
-
u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
716
-
MTL_DEBUG_RRCSTS_SHIFT;
716
+
u32 rrcsts = FIELD_GET(MTL_DEBUG_RRCSTS_MASK, value);
717
717
718
718
if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
719
719
x->mtl_rx_fifo_read_ctrl_flush++;
···
731
733
value = readl(ioaddr + GMAC_DEBUG);
732
734
733
735
if (value & GMAC_DEBUG_TFCSTS_MASK) {
734
-
u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
735
-
>> GMAC_DEBUG_TFCSTS_SHIFT;
736
+
u32 tfcsts = FIELD_GET(GMAC_DEBUG_TFCSTS_MASK, value);
736
737
737
738
if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
738
739
x->mac_tx_frame_ctrl_xfer++;
···
745
748
if (value & GMAC_DEBUG_TPESTS)
746
749
x->mac_gmii_tx_proto_engine++;
747
750
if (value & GMAC_DEBUG_RFCFCSTS_MASK)
748
-
x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
749
-
>> GMAC_DEBUG_RFCFCSTS_SHIFT;
751
+
x->mac_rx_frame_ctrl_fifo = FIELD_GET(GMAC_DEBUG_RFCFCSTS_MASK,
752
+
value);
750
753
if (value & GMAC_DEBUG_RPESTS)
751
754
x->mac_gmii_rx_proto_engine++;
752
755
}
···
767
770
{
768
771
u32 value = readl(ioaddr + GMAC_CONFIG);
769
772
770
-
value &= ~GMAC_CONFIG_SARC;
771
-
value |= val << GMAC_CONFIG_SARC_SHIFT;
773
+
value = u32_replace_bits(value, val, GMAC_CONFIG_SARC);
772
774
773
775
writel(value, ioaddr + GMAC_CONFIG);
774
776
}
···
875
879
writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
876
880
877
881
if (sa) {
878
-
value = match & GMAC_L4SP0;
882
+
value = FIELD_PREP(GMAC_L4SP0, match);
879
883
} else {
880
-
value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
884
+
value = FIELD_PREP(GMAC_L4DP0, match);
881
885
}
882
886
883
887
writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
+28
-42
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
+28
-42
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
···
17
17
struct dma_desc *p,
18
18
void __iomem *ioaddr)
19
19
{
20
-
unsigned int tdes3;
20
+
u32 tdes3 = le32_to_cpu(p->des3);
21
21
int ret = tx_done;
22
-
23
-
tdes3 = le32_to_cpu(p->des3);
24
22
25
23
/* Get tx owner first */
26
24
if (unlikely(tdes3 & TDES3_OWN))
···
44
46
if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
45
47
(tdes3 & TDES3_EXCESSIVE_COLLISION)))
46
48
x->tx_collision +=
47
-
(tdes3 & TDES3_COLLISION_COUNT_MASK)
48
-
>> TDES3_COLLISION_COUNT_SHIFT;
49
+
FIELD_GET(TDES3_COLLISION_COUNT_MASK, tdes3);
49
50
50
51
if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
51
52
x->tx_deferred++;
···
70
73
static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
71
74
struct dma_desc *p)
72
75
{
73
-
unsigned int rdes1 = le32_to_cpu(p->des1);
74
-
unsigned int rdes2 = le32_to_cpu(p->des2);
75
-
unsigned int rdes3 = le32_to_cpu(p->des3);
76
+
u32 rdes1 = le32_to_cpu(p->des1);
77
+
u32 rdes2 = le32_to_cpu(p->des2);
78
+
u32 rdes3 = le32_to_cpu(p->des3);
76
79
int message_type;
77
80
int ret = good_frame;
78
81
···
105
108
ret = discard_frame;
106
109
}
107
110
108
-
message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
111
+
message_type = FIELD_GET(RDES1_PTP_MSG_TYPE_MASK, rdes1);
109
112
110
113
if (rdes1 & RDES1_IP_HDR_ERROR) {
111
114
x->ip_hdr_err++;
···
165
168
x->l3_filter_match++;
166
169
if (rdes2 & RDES2_L4_FILTER_MATCH)
167
170
x->l4_filter_match++;
168
-
if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
169
-
>> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
171
+
if (rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
170
172
x->l3_l4_filter_no_match++;
171
173
172
174
return ret;
···
251
255
static int dwmac4_rx_check_timestamp(void *desc)
252
256
{
253
257
struct dma_desc *p = (struct dma_desc *)desc;
254
-
unsigned int rdes0 = le32_to_cpu(p->des0);
255
-
unsigned int rdes1 = le32_to_cpu(p->des1);
256
-
unsigned int rdes3 = le32_to_cpu(p->des3);
257
-
u32 own, ctxt;
258
+
u32 rdes0 = le32_to_cpu(p->des0);
259
+
u32 rdes1 = le32_to_cpu(p->des1);
260
+
u32 rdes3 = le32_to_cpu(p->des3);
261
+
bool own, ctxt;
258
262
int ret = 1;
259
263
260
264
own = rdes3 & RDES3_OWN;
261
-
ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
262
-
>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
265
+
ctxt = rdes3 & RDES3_CONTEXT_DESCRIPTOR;
263
266
264
267
if (likely(!own && ctxt)) {
265
268
if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
···
322
327
bool csum_flag, int mode, bool tx_own,
323
328
bool ls, unsigned int tot_pkt_len)
324
329
{
325
-
unsigned int tdes3 = le32_to_cpu(p->des3);
330
+
u32 tdes3 = le32_to_cpu(p->des3);
326
331
327
332
p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
328
333
···
332
337
else
333
338
tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
334
339
335
-
if (likely(csum_flag))
336
-
tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
337
-
else
338
-
tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
340
+
tdes3 = u32_replace_bits(tdes3, csum_flag ? TX_CIC_FULL : 0,
341
+
TDES3_CHECKSUM_INSERTION_MASK);
339
342
340
343
if (ls)
341
344
tdes3 |= TDES3_LAST_DESCRIPTOR;
···
359
366
bool ls, unsigned int tcphdrlen,
360
367
unsigned int tcppayloadlen)
361
368
{
362
-
unsigned int tdes3 = le32_to_cpu(p->des3);
369
+
u32 tdes3 = le32_to_cpu(p->des3);
363
370
364
371
if (len1)
365
-
p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
372
+
p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_BUFFER1_SIZE_MASK,
373
+
len1));
366
374
367
375
if (len2)
368
-
p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
369
-
& TDES2_BUFFER2_SIZE_MASK);
376
+
p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_BUFFER2_SIZE_MASK,
377
+
len2));
370
378
371
379
if (is_fs) {
372
380
tdes3 |= TDES3_FIRST_DESCRIPTOR |
373
381
TDES3_TCP_SEGMENTATION_ENABLE |
374
-
((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
375
-
TDES3_SLOT_NUMBER_MASK) |
376
-
((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
382
+
FIELD_PREP(TDES3_SLOT_NUMBER_MASK, tcphdrlen) |
383
+
FIELD_PREP(TDES3_TCP_PKT_PAYLOAD_MASK, tcppayloadlen);
377
384
} else {
378
385
tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
379
386
}
···
484
491
485
492
static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
486
493
{
487
-
sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
488
-
489
-
p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
494
+
p->des3 |= cpu_to_le32(FIELD_PREP(TDES3_SA_INSERT_CTRL_MASK,
495
+
sarc_type));
490
496
}
491
497
492
498
static int set_16kib_bfsize(int mtu)
···
507
515
508
516
/* Inner VLAN */
509
517
if (inner_type) {
510
-
u32 des = inner_tag << TDES2_IVT_SHIFT;
511
-
512
-
des &= TDES2_IVT_MASK;
513
-
p->des2 = cpu_to_le32(des);
514
-
515
-
des = inner_type << TDES3_IVTIR_SHIFT;
516
-
des &= TDES3_IVTIR_MASK;
517
-
p->des3 = cpu_to_le32(des | TDES3_IVLTV);
518
+
p->des2 = cpu_to_le32(FIELD_PREP(TDES2_IVT_MASK, inner_tag));
519
+
p->des3 = cpu_to_le32(FIELD_PREP(TDES3_IVTIR_MASK, inner_type) |
520
+
TDES3_IVLTV);
518
521
}
519
522
520
523
/* Outer VLAN */
···
521
534
522
535
static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
523
536
{
524
-
type <<= TDES2_VLAN_TAG_SHIFT;
525
-
p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
537
+
p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_VLAN_TAG_MASK, type));
526
538
}
527
539
528
540
static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
-8
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h
-8
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h
···
18
18
/* TDES2 (read format) */
19
19
#define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0)
20
20
#define TDES2_VLAN_TAG_MASK GENMASK(15, 14)
21
-
#define TDES2_VLAN_TAG_SHIFT 14
22
21
#define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16)
23
-
#define TDES2_BUFFER2_SIZE_MASK_SHIFT 16
24
22
#define TDES3_IVTIR_MASK GENMASK(19, 18)
25
-
#define TDES3_IVTIR_SHIFT 18
26
23
#define TDES3_IVLTV BIT(17)
27
24
#define TDES2_TIMESTAMP_ENABLE BIT(30)
28
25
#define TDES2_IVT_MASK GENMASK(31, 16)
29
-
#define TDES2_IVT_SHIFT 16
30
26
#define TDES2_INTERRUPT_ON_COMPLETION BIT(31)
31
27
32
28
/* TDES3 (read format) */
···
30
34
#define TDES3_VLAN_TAG GENMASK(15, 0)
31
35
#define TDES3_VLTV BIT(16)
32
36
#define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16)
33
-
#define TDES3_CHECKSUM_INSERTION_SHIFT 16
34
37
#define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0)
35
38
#define TDES3_TCP_SEGMENTATION_ENABLE BIT(18)
36
-
#define TDES3_HDR_LEN_SHIFT 19
37
39
#define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19)
38
40
#define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23)
39
-
#define TDES3_SA_INSERT_CTRL_SHIFT 23
40
41
#define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26)
41
42
42
43
/* TDES3 (write back format) */
···
42
49
#define TDES3_UNDERFLOW_ERROR BIT(2)
43
50
#define TDES3_EXCESSIVE_DEFERRAL BIT(3)
44
51
#define TDES3_COLLISION_COUNT_MASK GENMASK(7, 4)
45
-
#define TDES3_COLLISION_COUNT_SHIFT 4
46
52
#define TDES3_EXCESSIVE_COLLISION BIT(8)
47
53
#define TDES3_LATE_COLLISION BIT(9)
48
54
#define TDES3_NO_CARRIER BIT(10)
+17
-23
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+17
-23
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
···
27
27
if (axi->axi_xit_frm)
28
28
value |= DMA_AXI_LPI_XIT_FRM;
29
29
30
-
value &= ~DMA_AXI_WR_OSR_LMT;
31
-
value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
32
-
DMA_AXI_WR_OSR_LMT_SHIFT;
33
-
34
-
value &= ~DMA_AXI_RD_OSR_LMT;
35
-
value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
36
-
DMA_AXI_RD_OSR_LMT_SHIFT;
30
+
value = u32_replace_bits(value, axi->axi_wr_osr_lmt,
31
+
DMA_AXI_WR_OSR_LMT);
32
+
value = u32_replace_bits(value, axi->axi_rd_osr_lmt,
33
+
DMA_AXI_RD_OSR_LMT);
37
34
38
35
/* Depending on the UNDEF bit the Master AXI will perform any burst
39
36
* length according to the BLEN programmed (by default all BLEN are
···
52
55
u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
53
56
54
57
value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
55
-
value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
58
+
value = value | FIELD_PREP(DMA_BUS_MODE_RPBL_MASK, rxpbl);
56
59
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
57
60
58
61
if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
···
73
76
u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
74
77
75
78
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
76
-
value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);
79
+
value = value | FIELD_PREP(DMA_BUS_MODE_PBL, txpbl);
77
80
78
81
/* Enable OSP to get best performance */
79
82
value |= DMA_CONTROL_OSP;
···
148
151
149
152
value = readl(ioaddr + DMA_BUS_MODE);
150
153
151
-
if (dma_cfg->multi_msi_en) {
152
-
value &= ~DMA_BUS_MODE_INTM_MASK;
153
-
value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);
154
-
}
154
+
if (dma_cfg->multi_msi_en)
155
+
value = u32_replace_bits(value, DMA_BUS_MODE_INTM_MODE1,
156
+
DMA_BUS_MODE_INTM_MASK);
155
157
156
158
if (dma_cfg->dche)
157
159
value |= DMA_BUS_MODE_DCHE;
···
260
264
}
261
265
262
266
mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
263
-
mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;
267
+
mtl_rx_op |= FIELD_PREP(MTL_OP_MODE_RQS_MASK, rqs);
264
268
265
269
/* Enable flow control only if each channel gets 4 KiB or more FIFO and
266
270
* only if channel is not an AVB channel.
···
291
295
break;
292
296
}
293
297
294
-
mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
295
-
mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;
296
-
297
-
mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
298
-
mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
298
+
mtl_rx_op = u32_replace_bits(mtl_rx_op, rfd,
299
+
MTL_OP_MODE_RFD_MASK);
300
+
mtl_rx_op = u32_replace_bits(mtl_rx_op, rfa,
301
+
MTL_OP_MODE_RFA_MASK);
299
302
}
300
303
301
304
writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));
···
349
354
mtl_tx_op |= MTL_OP_MODE_TXQEN;
350
355
else
351
356
mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
352
-
mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
353
-
mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;
357
+
358
+
mtl_tx_op = u32_replace_bits(mtl_tx_op, tqs, MTL_OP_MODE_TQS_MASK);
354
359
355
360
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
356
361
}
···
491
496
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
492
497
u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
493
498
494
-
value &= ~DMA_RBSZ_MASK;
495
-
value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
499
+
value = u32_replace_bits(value, bfsize, DMA_RBSZ_MASK);
496
500
497
501
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
498
502
}
+53
-107
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
+53
-107
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
···
16
16
#define DMA_CHANNEL_NB_MAX 1
17
17
18
18
#define DMA_BUS_MODE 0x00001000
19
-
#define DMA_SYS_BUS_MODE 0x00001004
20
-
#define DMA_STATUS 0x00001008
21
-
#define DMA_DEBUG_STATUS_0 0x0000100c
22
-
#define DMA_DEBUG_STATUS_1 0x00001010
23
-
#define DMA_DEBUG_STATUS_2 0x00001014
24
-
#define DMA_AXI_BUS_MODE 0x00001028
25
-
#define DMA_TBS_CTRL 0x00001050
26
19
27
-
/* DMA Bus Mode bitmap */
28
20
#define DMA_BUS_MODE_DCHE BIT(19)
29
21
#define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16)
30
-
#define DMA_BUS_MODE_INTM_SHIFT 16
31
22
#define DMA_BUS_MODE_INTM_MODE1 0x1
32
23
#define DMA_BUS_MODE_SFT_RESET BIT(0)
33
24
34
-
/* DMA SYS Bus Mode bitmap */
35
-
#define DMA_BUS_MODE_SPH BIT(24)
25
+
#define DMA_SYS_BUS_MODE 0x00001004
26
+
36
27
#define DMA_BUS_MODE_PBL BIT(16)
37
-
#define DMA_BUS_MODE_PBL_SHIFT 16
38
-
#define DMA_BUS_MODE_RPBL_SHIFT 16
28
+
#define DMA_BUS_MODE_RPBL_MASK GENMASK(21, 16)
39
29
#define DMA_BUS_MODE_MB BIT(14)
40
30
#define DMA_BUS_MODE_FB BIT(0)
41
31
42
-
/* DMA Interrupt top status */
43
-
#define DMA_STATUS_MAC BIT(17)
44
-
#define DMA_STATUS_MTL BIT(16)
45
-
#define DMA_STATUS_CHAN7 BIT(7)
46
-
#define DMA_STATUS_CHAN6 BIT(6)
47
-
#define DMA_STATUS_CHAN5 BIT(5)
48
-
#define DMA_STATUS_CHAN4 BIT(4)
49
-
#define DMA_STATUS_CHAN3 BIT(3)
50
-
#define DMA_STATUS_CHAN2 BIT(2)
51
-
#define DMA_STATUS_CHAN1 BIT(1)
52
-
#define DMA_STATUS_CHAN0 BIT(0)
32
+
#define DMA_STATUS 0x00001008
53
33
54
-
/* DMA debug status bitmap */
55
-
#define DMA_DEBUG_STATUS_TS_MASK 0xf
56
-
#define DMA_DEBUG_STATUS_RS_MASK 0xf
34
+
#define DMA_AXI_BUS_MODE 0x00001028
57
35
58
-
/* DMA AXI bitmap */
59
36
#define DMA_AXI_EN_LPI BIT(31)
60
37
#define DMA_AXI_LPI_XIT_FRM BIT(30)
61
38
#define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)
62
-
#define DMA_AXI_WR_OSR_LMT_SHIFT 24
63
39
#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
64
-
#define DMA_AXI_RD_OSR_LMT_SHIFT 16
65
-
66
-
#define DMA_AXI_OSR_MAX 0xf
67
-
#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
68
-
(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
69
40
70
41
#define DMA_SYS_BUS_MB BIT(14)
71
-
#define DMA_AXI_1KBBE BIT(13)
72
42
#define DMA_SYS_BUS_AAL DMA_AXI_AAL
73
43
#define DMA_SYS_BUS_EAME BIT(11)
74
44
#define DMA_SYS_BUS_FB BIT(0)
75
45
76
-
#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
77
-
DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
78
-
DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
79
-
DMA_AXI_BLEN4)
46
+
#define DMA_TBS_CTRL 0x00001050
80
47
81
-
/* DMA TBS Control */
82
48
#define DMA_TBS_FTOS GENMASK(31, 8)
83
49
#define DMA_TBS_FTOV BIT(0)
84
50
#define DMA_TBS_DEF_FTOS (DMA_TBS_FTOS | DMA_TBS_FTOV)
···
66
100
return addr;
67
101
}
68
102
69
-
#define DMA_CHAN_REG_NUMBER 17
70
-
71
103
#define DMA_CHAN_CONTROL(addrs, x) dma_chanx_base_addr(addrs, x)
104
+
105
+
#define DMA_CONTROL_SPH BIT(24)
106
+
72
107
#define DMA_CHAN_TX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4)
108
+
109
+
#define DMA_CONTROL_EDSE BIT(28)
110
+
#define DMA_CONTROL_TSE BIT(12)
111
+
#define DMA_CONTROL_OSP BIT(4)
112
+
#define DMA_CONTROL_ST BIT(0)
113
+
73
114
#define DMA_CHAN_RX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x8)
115
+
116
+
#define DMA_CONTROL_SR BIT(0)
117
+
#define DMA_RBSZ_MASK GENMASK(14, 1)
118
+
74
119
#define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x10)
75
120
#define DMA_CHAN_TX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x14)
76
121
#define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x18)
···
90
113
#define DMA_CHAN_RX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x28)
91
114
#define DMA_CHAN_TX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x2c)
92
115
#define DMA_CHAN_RX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x30)
116
+
93
117
#define DMA_CHAN_INTR_ENA(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x34)
118
+
119
+
#define DMA_CHAN_INTR_ENA_NIE BIT(16)
120
+
#define DMA_CHAN_INTR_ENA_AIE BIT(15)
121
+
#define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
122
+
#define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14)
123
+
#define DMA_CHAN_INTR_ENA_FBE BIT(12)
124
+
#define DMA_CHAN_INTR_ENA_RIE BIT(6)
125
+
#define DMA_CHAN_INTR_ENA_TIE BIT(0)
126
+
127
+
#define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \
128
+
DMA_CHAN_INTR_ENA_RIE | \
129
+
DMA_CHAN_INTR_ENA_TIE)
130
+
131
+
#define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \
132
+
DMA_CHAN_INTR_ENA_FBE)
133
+
/* DMA default interrupt mask for 4.00 */
134
+
#define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \
135
+
DMA_CHAN_INTR_ABNORMAL)
136
+
#define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE)
137
+
#define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE)
138
+
139
+
#define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \
140
+
DMA_CHAN_INTR_ENA_RIE | \
141
+
DMA_CHAN_INTR_ENA_TIE)
142
+
143
+
#define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \
144
+
DMA_CHAN_INTR_ENA_FBE)
145
+
/* DMA default interrupt mask for 4.10a */
146
+
#define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
147
+
DMA_CHAN_INTR_ABNORMAL_4_10)
148
+
#define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE)
149
+
#define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE)
150
+
94
151
#define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38)
95
152
#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c)
96
153
#define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x44)
···
135
124
#define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x5c)
136
125
#define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60)
137
126
138
-
/* DMA Control X */
139
-
#define DMA_CONTROL_SPH BIT(24)
140
-
#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
141
-
142
-
/* DMA Tx Channel X Control register defines */
143
-
#define DMA_CONTROL_EDSE BIT(28)
144
-
#define DMA_CONTROL_TSE BIT(12)
145
-
#define DMA_CONTROL_OSP BIT(4)
146
-
#define DMA_CONTROL_ST BIT(0)
147
-
148
-
/* DMA Rx Channel X Control register defines */
149
-
#define DMA_CONTROL_SR BIT(0)
150
-
#define DMA_RBSZ_MASK GENMASK(14, 1)
151
-
#define DMA_RBSZ_SHIFT 1
152
-
153
127
/* Interrupt status per channel */
154
128
#define DMA_CHAN_STATUS_REB GENMASK(21, 19)
155
-
#define DMA_CHAN_STATUS_REB_SHIFT 19
156
-
#define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
157
-
#define DMA_CHAN_STATUS_TEB_SHIFT 16
158
129
#define DMA_CHAN_STATUS_NIS BIT(15)
159
130
#define DMA_CHAN_STATUS_AIS BIT(14)
160
131
#define DMA_CHAN_STATUS_CDE BIT(13)
···
169
176
DMA_CHAN_STATUS_TPS | \
170
177
DMA_CHAN_STATUS_TI | \
171
178
DMA_CHAN_STATUS_MSK_COMMON)
172
-
173
-
/* Interrupt enable bits per channel */
174
-
#define DMA_CHAN_INTR_ENA_NIE BIT(16)
175
-
#define DMA_CHAN_INTR_ENA_AIE BIT(15)
176
-
#define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
177
-
#define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14)
178
-
#define DMA_CHAN_INTR_ENA_CDE BIT(13)
179
-
#define DMA_CHAN_INTR_ENA_FBE BIT(12)
180
-
#define DMA_CHAN_INTR_ENA_ERE BIT(11)
181
-
#define DMA_CHAN_INTR_ENA_ETE BIT(10)
182
-
#define DMA_CHAN_INTR_ENA_RWE BIT(9)
183
-
#define DMA_CHAN_INTR_ENA_RSE BIT(8)
184
-
#define DMA_CHAN_INTR_ENA_RBUE BIT(7)
185
-
#define DMA_CHAN_INTR_ENA_RIE BIT(6)
186
-
#define DMA_CHAN_INTR_ENA_TBUE BIT(2)
187
-
#define DMA_CHAN_INTR_ENA_TSE BIT(1)
188
-
#define DMA_CHAN_INTR_ENA_TIE BIT(0)
189
-
190
-
#define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \
191
-
DMA_CHAN_INTR_ENA_RIE | \
192
-
DMA_CHAN_INTR_ENA_TIE)
193
-
194
-
#define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \
195
-
DMA_CHAN_INTR_ENA_FBE)
196
-
/* DMA default interrupt mask for 4.00 */
197
-
#define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \
198
-
DMA_CHAN_INTR_ABNORMAL)
199
-
#define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE)
200
-
#define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE)
201
-
202
-
#define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \
203
-
DMA_CHAN_INTR_ENA_RIE | \
204
-
DMA_CHAN_INTR_ENA_TIE)
205
-
206
-
#define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \
207
-
DMA_CHAN_INTR_ENA_FBE)
208
-
/* DMA default interrupt mask for 4.10a */
209
-
#define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
210
-
DMA_CHAN_INTR_ABNORMAL_4_10)
211
-
#define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE)
212
-
#define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE)
213
-
214
-
/* channel 0 specific fields */
215
-
#define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12)
216
-
#define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12
217
-
#define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
218
-
#define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
219
179
220
180
int dwmac4_dma_reset(void __iomem *ioaddr);
221
181
void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
···
234
234
* bit that has no effect on the High Reg 0 where the bit 31 (MO)
235
235
* is RO.
236
236
*/
237
-
data |= (STMMAC_CHAN0 << GMAC_HI_DCS_SHIFT);
237
+
data |= FIELD_PREP(GMAC_HI_DCS, STMMAC_CHAN0);
238
238
writel(data | GMAC_HI_REG_AE, ioaddr + high);
239
239
data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
240
240
writel(data, ioaddr + low);
+73
-99
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
+73
-99
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
···
13
13
14
14
/* DMA CRS Control and Status Register Mapping */
15
15
#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
16
+
17
+
#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
18
+
16
19
#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
17
20
#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
18
21
#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
19
22
#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
23
+
20
24
#define DMA_STATUS 0x00001014 /* Status Register */
25
+
#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
26
+
#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
27
+
#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
28
+
#define DMA_STATUS_TS_MASK GENMASK(22, 20) /* Transmit Process State */
29
+
#define DMA_STATUS_RS_MASK GENMASK(19, 17) /* Receive Process State */
30
+
#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
31
+
#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
32
+
#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
33
+
#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
34
+
#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
35
+
#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
36
+
#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
37
+
#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
38
+
#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
39
+
#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
40
+
#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
41
+
#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
42
+
#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
43
+
#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
44
+
#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
45
+
46
+
#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
47
+
DMA_STATUS_AIS | \
48
+
DMA_STATUS_FBI)
49
+
50
+
#define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
51
+
DMA_STATUS_RWT | \
52
+
DMA_STATUS_RPS | \
53
+
DMA_STATUS_RU | \
54
+
DMA_STATUS_RI | \
55
+
DMA_STATUS_OVF | \
56
+
DMA_STATUS_MSK_COMMON)
57
+
58
+
#define DMA_STATUS_MSK_TX (DMA_STATUS_ETI | \
59
+
DMA_STATUS_UNF | \
60
+
DMA_STATUS_TJT | \
61
+
DMA_STATUS_TU | \
62
+
DMA_STATUS_TPS | \
63
+
DMA_STATUS_TI | \
64
+
DMA_STATUS_MSK_COMMON)
65
+
21
66
#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
67
+
68
+
/* DMA Control register defines */
69
+
#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
70
+
#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
71
+
#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
72
+
22
73
#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
74
+
75
+
/* DMA Normal interrupt */
76
+
#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
77
+
#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
78
+
#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
79
+
80
+
#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
81
+
DMA_INTR_ENA_TIE)
82
+
83
+
/* DMA Abnormal interrupt */
84
+
#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
85
+
#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
86
+
#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
87
+
88
+
#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
89
+
DMA_INTR_ENA_UNE)
90
+
91
+
/* DMA default interrupt mask */
92
+
#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
93
+
#define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE)
94
+
#define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE)
95
+
23
96
#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
24
97
25
98
/* Following DMA defines are channels oriented */
···
115
42
#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
116
43
#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
117
44
#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
118
-
#define DMA_CHAN_MISSED_FRAME_CTR(chan) \
119
-
dma_chan_base_addr(DMA_MISSED_FRAME_CTR, chan)
120
45
#define DMA_CHAN_RX_WATCHDOG(chan) \
121
46
dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
122
47
123
-
/* SW Reset */
124
-
#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
125
48
126
49
/* Rx watchdog register */
127
50
#define DMA_RX_WATCHDOG 0x00001024
···
128
59
#define DMA_AXI_EN_LPI BIT(31)
129
60
#define DMA_AXI_LPI_XIT_FRM BIT(30)
130
61
#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)
131
-
#define DMA_AXI_WR_OSR_LMT_SHIFT 20
132
-
#define DMA_AXI_WR_OSR_LMT_MASK 0xf
133
62
#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
134
-
#define DMA_AXI_RD_OSR_LMT_SHIFT 16
135
-
#define DMA_AXI_RD_OSR_LMT_MASK 0xf
136
-
137
-
#define DMA_AXI_OSR_MAX 0xf
138
-
#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
139
-
(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
140
-
#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
141
-
DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
142
-
DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
143
-
DMA_AXI_BLEN4)
144
63
145
64
#define DMA_AXI_1KBBE BIT(13)
146
65
···
137
80
#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
138
81
#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
139
82
#define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */
140
-
141
-
/* DMA Control register defines */
142
-
#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
143
-
#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
144
-
145
-
/* DMA Normal interrupt */
146
-
#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
147
-
#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
148
-
#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
149
-
#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
150
-
#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
151
-
152
-
#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
153
-
DMA_INTR_ENA_TIE)
154
-
155
-
/* DMA Abnormal interrupt */
156
-
#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
157
-
#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
158
-
#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
159
-
#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
160
-
#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
161
-
#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
162
-
#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
163
-
#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
164
-
#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
165
-
#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
166
-
167
-
#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
168
-
DMA_INTR_ENA_UNE)
169
-
170
-
/* DMA default interrupt mask */
171
-
#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
172
-
#define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE)
173
-
#define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE)
174
-
175
-
/* DMA Status register defines */
176
-
#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */
177
-
#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
178
-
#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
179
-
#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
180
-
#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
181
-
#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
182
-
#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
183
-
#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
184
-
#define DMA_STATUS_TS_SHIFT 20
185
-
#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
186
-
#define DMA_STATUS_RS_SHIFT 17
187
-
#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
188
-
#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
189
-
#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
190
-
#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
191
-
#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
192
-
#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
193
-
#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
194
-
#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
195
-
#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
196
-
#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
197
-
#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
198
-
#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
199
-
#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
200
-
#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
201
-
#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
202
-
#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
203
-
204
-
#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
205
-
DMA_STATUS_AIS | \
206
-
DMA_STATUS_FBI)
207
-
208
-
#define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
209
-
DMA_STATUS_RWT | \
210
-
DMA_STATUS_RPS | \
211
-
DMA_STATUS_RU | \
212
-
DMA_STATUS_RI | \
213
-
DMA_STATUS_OVF | \
214
-
DMA_STATUS_MSK_COMMON)
215
-
216
-
#define DMA_STATUS_MSK_TX (DMA_STATUS_ETI | \
217
-
DMA_STATUS_UNF | \
218
-
DMA_STATUS_TJT | \
219
-
DMA_STATUS_TU | \
220
-
DMA_STATUS_TPS | \
221
-
DMA_STATUS_TI | \
222
-
DMA_STATUS_MSK_COMMON)
223
83
224
84
#define NUM_DWMAC100_DMA_REGS 9
225
85
#define NUM_DWMAC1000_DMA_REGS 23
+2
-8
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+2
-8
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
···
97
97
#ifdef DWMAC_DMA_DEBUG
98
98
static void show_tx_process_state(unsigned int status)
99
99
{
100
-
unsigned int state;
101
-
state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
102
-
103
-
switch (state) {
100
+
switch (FIELD_GET(DMA_STATUS_TS_MASK, status)) {
104
101
case 0:
105
102
pr_debug("- TX (Stopped): Reset or Stop command\n");
106
103
break;
···
125
128
126
129
static void show_rx_process_state(unsigned int status)
127
130
{
128
-
unsigned int state;
129
-
state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
130
-
131
-
switch (state) {
131
+
switch (FIELD_GET(DMA_STATUS_RS_MASK, status)) {
132
132
case 0:
133
133
pr_debug("- RX (Stopped): Reset or Stop command\n");
134
134
break;
+7
-33
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+7
-33
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
···
24
24
#define XGMAC_CONFIG_SS_2500 (0x6 << XGMAC_CONFIG_SS_OFF)
25
25
#define XGMAC_CONFIG_SS_10_MII (0x7 << XGMAC_CONFIG_SS_OFF)
26
26
#define XGMAC_CONFIG_SARC GENMASK(22, 20)
27
-
#define XGMAC_CONFIG_SARC_SHIFT 20
28
27
#define XGMAC_CONFIG_JD BIT(16)
29
28
#define XGMAC_CONFIG_TE BIT(0)
30
29
#define XGMAC_CORE_INIT_TX (XGMAC_CONFIG_JD)
31
30
#define XGMAC_RX_CONFIG 0x00000004
32
31
#define XGMAC_CONFIG_ARPEN BIT(31)
33
32
#define XGMAC_CONFIG_GPSL GENMASK(29, 16)
34
-
#define XGMAC_CONFIG_GPSL_SHIFT 16
35
33
#define XGMAC_CONFIG_HDSMS GENMASK(14, 12)
36
34
#define XGMAC_CONFIG_HDSMS_SHIFT 12
37
-
#define XGMAC_CONFIG_HDSMS_256 (0x2 << XGMAC_CONFIG_HDSMS_SHIFT)
35
+
#define XGMAC_CONFIG_HDSMS_256 FIELD_PREP(XGMAC_CONFIG_HDSMS, 0x2)
38
36
#define XGMAC_CONFIG_S2KP BIT(11)
39
37
#define XGMAC_CONFIG_LM BIT(10)
40
38
#define XGMAC_CONFIG_IPC BIT(9)
···
42
44
#define XGMAC_CONFIG_CST BIT(2)
43
45
#define XGMAC_CONFIG_ACS BIT(1)
44
46
#define XGMAC_CONFIG_RE BIT(0)
45
-
#define XGMAC_CORE_INIT_RX (XGMAC_CONFIG_GPSLCE | XGMAC_CONFIG_WD | \
46
-
(XGMAC_JUMBO_LEN << XGMAC_CONFIG_GPSL_SHIFT))
47
+
#define XGMAC_CORE_INIT_RX (XGMAC_CONFIG_GPSLCE | \
48
+
XGMAC_CONFIG_WD | \
49
+
FIELD_PREP(XGMAC_CONFIG_GPSL, \
50
+
XGMAC_JUMBO_LEN))
47
51
#define XGMAC_PACKET_FILTER 0x00000008
48
52
#define XGMAC_FILTER_RA BIT(31)
49
53
#define XGMAC_FILTER_IPFE BIT(20)
···
90
90
#define XGMAC_INT_DEFAULT_EN (XGMAC_LPIIE | XGMAC_PMTIE)
91
91
#define XGMAC_Qx_TX_FLOW_CTRL(x) (0x00000070 + (x) * 4)
92
92
#define XGMAC_PT GENMASK(31, 16)
93
-
#define XGMAC_PT_SHIFT 16
94
93
#define XGMAC_TFE BIT(1)
95
94
#define XGMAC_RX_FLOW_CTRL 0x00000090
96
95
#define XGMAC_RFE BIT(0)
···
179
180
#define XGMAC_ADDR_MAX 32
180
181
#define XGMAC_AE BIT(31)
181
182
#define XGMAC_DCS GENMASK(19, 16)
182
-
#define XGMAC_DCS_SHIFT 16
183
183
#define XGMAC_ADDRx_LOW(x) (0x00000304 + (x) * 0x8)
184
184
#define XGMAC_L3L4_ADDR_CTRL 0x00000c00
185
185
#define XGMAC_IDDR GENMASK(16, 8)
186
-
#define XGMAC_IDDR_SHIFT 8
187
-
#define XGMAC_IDDR_FNUM 4
186
+
#define XGMAC_IDDR_FNUM_MASK GENMASK(7, 4) /* FNUM within IDDR */
187
+
#define XGMAC_IDDR_REG_MASK GENMASK(3, 0) /* REG within IDDR */
188
188
#define XGMAC_TT BIT(1)
189
189
#define XGMAC_XB BIT(0)
190
190
#define XGMAC_L3L4_DATA 0x00000c04
···
202
204
#define XGMAC_L3PEN0 BIT(0)
203
205
#define XGMAC_L4_ADDR 0x1
204
206
#define XGMAC_L4DP0 GENMASK(31, 16)
205
-
#define XGMAC_L4DP0_SHIFT 16
206
207
#define XGMAC_L4SP0 GENMASK(15, 0)
207
208
#define XGMAC_L3_ADDR0 0x4
208
209
#define XGMAC_L3_ADDR1 0x5
···
221
224
#define XGMAC_RSS_DATA 0x00000c8c
222
225
#define XGMAC_TIMESTAMP_STATUS 0x00000d20
223
226
#define XGMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25)
224
-
#define XGMAC_TIMESTAMP_ATSNS_SHIFT 25
225
227
#define XGMAC_TXTSC BIT(15)
226
228
#define XGMAC_TXTIMESTAMP_NSEC 0x00000d30
227
229
#define XGMAC_TXTSSTSLO GENMASK(30, 0)
···
286
290
#define XGMAC_DPP_DISABLE BIT(0)
287
291
#define XGMAC_MTL_TXQ_OPMODE(x) (0x00001100 + (0x80 * (x)))
288
292
#define XGMAC_TQS GENMASK(25, 16)
289
-
#define XGMAC_TQS_SHIFT 16
290
293
#define XGMAC_Q2TCMAP GENMASK(10, 8)
291
-
#define XGMAC_Q2TCMAP_SHIFT 8
292
294
#define XGMAC_TTC GENMASK(6, 4)
293
-
#define XGMAC_TTC_SHIFT 4
294
295
#define XGMAC_TXQEN GENMASK(3, 2)
295
-
#define XGMAC_TXQEN_SHIFT 2
296
296
#define XGMAC_TSF BIT(1)
297
297
#define XGMAC_MTL_TCx_ETS_CONTROL(x) (0x00001110 + (0x80 * (x)))
298
298
#define XGMAC_MTL_TCx_QUANTUM_WEIGHT(x) (0x00001118 + (0x80 * (x)))
···
302
310
#define XGMAC_ETS (0x2 << 0)
303
311
#define XGMAC_MTL_RXQ_OPMODE(x) (0x00001140 + (0x80 * (x)))
304
312
#define XGMAC_RQS GENMASK(25, 16)
305
-
#define XGMAC_RQS_SHIFT 16
306
313
#define XGMAC_EHFC BIT(7)
307
314
#define XGMAC_RSF BIT(5)
308
315
#define XGMAC_RTC GENMASK(1, 0)
309
-
#define XGMAC_RTC_SHIFT 0
310
316
#define XGMAC_MTL_RXQ_FLOW_CONTROL(x) (0x00001150 + (0x80 * (x)))
311
317
#define XGMAC_RFD GENMASK(31, 17)
312
-
#define XGMAC_RFD_SHIFT 17
313
318
#define XGMAC_RFA GENMASK(15, 1)
314
-
#define XGMAC_RFA_SHIFT 1
315
319
#define XGMAC_MTL_QINTEN(x) (0x00001170 + (0x80 * (x)))
316
320
#define XGMAC_RXOIE BIT(16)
317
321
#define XGMAC_MTL_QINT_STATUS(x) (0x00001174 + (0x80 * (x)))
···
321
333
#define XGMAC_SWR BIT(0)
322
334
#define XGMAC_DMA_SYSBUS_MODE 0x00003004
323
335
#define XGMAC_WR_OSR_LMT GENMASK(29, 24)
324
-
#define XGMAC_WR_OSR_LMT_SHIFT 24
325
336
#define XGMAC_RD_OSR_LMT GENMASK(21, 16)
326
-
#define XGMAC_RD_OSR_LMT_SHIFT 16
327
337
#define XGMAC_EN_LPI BIT(15)
328
338
#define XGMAC_LPI_XIT_PKT BIT(14)
329
339
#define XGMAC_AAL DMA_AXI_AAL
···
356
370
#define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x)))
357
371
#define XGMAC_EDSE BIT(28)
358
372
#define XGMAC_TxPBL GENMASK(21, 16)
359
-
#define XGMAC_TxPBL_SHIFT 16
360
373
#define XGMAC_TSE BIT(12)
361
374
#define XGMAC_OSP BIT(4)
362
375
#define XGMAC_TXST BIT(0)
363
376
#define XGMAC_DMA_CH_RX_CONTROL(x) (0x00003108 + (0x80 * (x)))
364
377
#define XGMAC_RxPBL GENMASK(21, 16)
365
-
#define XGMAC_RxPBL_SHIFT 16
366
378
#define XGMAC_RBSZ GENMASK(14, 1)
367
-
#define XGMAC_RBSZ_SHIFT 1
368
379
#define XGMAC_RXST BIT(0)
369
380
#define XGMAC_DMA_CH_TxDESC_HADDR(x) (0x00003110 + (0x80 * (x)))
370
381
#define XGMAC_DMA_CH_TxDESC_LADDR(x) (0x00003114 + (0x80 * (x)))
···
406
423
#define XGMAC_TDES0_LT GENMASK(7, 0)
407
424
#define XGMAC_TDES1_LT GENMASK(31, 8)
408
425
#define XGMAC_TDES2_IVT GENMASK(31, 16)
409
-
#define XGMAC_TDES2_IVT_SHIFT 16
410
426
#define XGMAC_TDES2_IOC BIT(31)
411
427
#define XGMAC_TDES2_TTSE BIT(30)
412
428
#define XGMAC_TDES2_B2L GENMASK(29, 16)
413
-
#define XGMAC_TDES2_B2L_SHIFT 16
414
429
#define XGMAC_TDES2_VTIR GENMASK(15, 14)
415
-
#define XGMAC_TDES2_VTIR_SHIFT 14
416
430
#define XGMAC_TDES2_B1L GENMASK(13, 0)
417
431
#define XGMAC_TDES3_OWN BIT(31)
418
432
#define XGMAC_TDES3_CTXT BIT(30)
419
433
#define XGMAC_TDES3_FD BIT(29)
420
434
#define XGMAC_TDES3_LD BIT(28)
421
435
#define XGMAC_TDES3_CPC GENMASK(27, 26)
422
-
#define XGMAC_TDES3_CPC_SHIFT 26
423
436
#define XGMAC_TDES3_TCMSSV BIT(26)
424
437
#define XGMAC_TDES3_SAIC GENMASK(25, 23)
425
-
#define XGMAC_TDES3_SAIC_SHIFT 23
426
438
#define XGMAC_TDES3_TBSV BIT(24)
427
439
#define XGMAC_TDES3_THL GENMASK(22, 19)
428
-
#define XGMAC_TDES3_THL_SHIFT 19
429
440
#define XGMAC_TDES3_IVTIR GENMASK(19, 18)
430
-
#define XGMAC_TDES3_IVTIR_SHIFT 18
431
441
#define XGMAC_TDES3_TSE BIT(18)
432
442
#define XGMAC_TDES3_IVLTV BIT(17)
433
443
#define XGMAC_TDES3_CIC GENMASK(17, 16)
434
-
#define XGMAC_TDES3_CIC_SHIFT 16
435
444
#define XGMAC_TDES3_TPL GENMASK(17, 0)
436
445
#define XGMAC_TDES3_VLTV BIT(16)
437
446
#define XGMAC_TDES3_VT GENMASK(15, 0)
···
436
461
#define XGMAC_RDES3_CDA BIT(27)
437
462
#define XGMAC_RDES3_RSV BIT(26)
438
463
#define XGMAC_RDES3_L34T GENMASK(23, 20)
439
-
#define XGMAC_RDES3_L34T_SHIFT 20
440
464
#define XGMAC_RDES3_ET_LT GENMASK(19, 16)
441
465
#define XGMAC_L34T_IP4TCP 0x1
442
466
#define XGMAC_L34T_IP4UDP 0x2
+12
-9
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+12
-9
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
···
369
369
u32 value = XGMAC_TFE;
370
370
371
371
if (duplex)
372
-
value |= pause_time << XGMAC_PT_SHIFT;
372
+
value |= FIELD_PREP(XGMAC_PT, pause_time);
373
373
374
374
writel(value, ioaddr + XGMAC_Qx_TX_FLOW_CTRL(i));
375
375
}
···
1226
1226
{
1227
1227
u32 value = readl(ioaddr + XGMAC_TX_CONFIG);
1228
1228
1229
-
value &= ~XGMAC_CONFIG_SARC;
1230
-
value |= val << XGMAC_CONFIG_SARC_SHIFT;
1229
+
value = u32_replace_bits(value, val, XGMAC_CONFIG_SARC);
1231
1230
1232
1231
writel(value, ioaddr + XGMAC_TX_CONFIG);
1233
1232
}
···
1246
1247
u8 reg, u32 *data)
1247
1248
{
1248
1249
void __iomem *ioaddr = hw->pcsr;
1249
-
u32 value;
1250
+
u32 value, iddr;
1250
1251
int ret;
1251
1252
1252
1253
ret = dwxgmac2_filter_wait(hw);
1253
1254
if (ret)
1254
1255
return ret;
1255
1256
1256
-
value = ((filter_no << XGMAC_IDDR_FNUM) | reg) << XGMAC_IDDR_SHIFT;
1257
+
iddr = FIELD_PREP(XGMAC_IDDR_FNUM_MASK, filter_no) |
1258
+
FIELD_PREP(XGMAC_IDDR_REG_MASK, reg);
1259
+
value = FIELD_PREP(XGMAC_IDDR, iddr);
1257
1260
value |= XGMAC_TT | XGMAC_XB;
1258
1261
writel(value, ioaddr + XGMAC_L3L4_ADDR_CTRL);
1259
1262
···
1271
1270
u8 reg, u32 data)
1272
1271
{
1273
1272
void __iomem *ioaddr = hw->pcsr;
1274
-
u32 value;
1273
+
u32 value, iddr;
1275
1274
int ret;
1276
1275
1277
1276
ret = dwxgmac2_filter_wait(hw);
···
1280
1279
1281
1280
writel(data, ioaddr + XGMAC_L3L4_DATA);
1282
1281
1283
-
value = ((filter_no << XGMAC_IDDR_FNUM) | reg) << XGMAC_IDDR_SHIFT;
1282
+
iddr = FIELD_PREP(XGMAC_IDDR_FNUM_MASK, filter_no) |
1283
+
FIELD_PREP(XGMAC_IDDR_REG_MASK, reg);
1284
+
value = FIELD_PREP(XGMAC_IDDR, iddr);
1284
1285
value |= XGMAC_XB;
1285
1286
writel(value, ioaddr + XGMAC_L3L4_ADDR_CTRL);
1286
1287
···
1391
1388
return ret;
1392
1389
1393
1390
if (sa) {
1394
-
value = match & XGMAC_L4SP0;
1391
+
value = FIELD_PREP(XGMAC_L4SP0, match);
1395
1392
1396
1393
ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);
1397
1394
if (ret)
1398
1395
return ret;
1399
1396
} else {
1400
-
value = (match << XGMAC_L4DP0_SHIFT) & XGMAC_L4DP0;
1397
+
value = FIELD_PREP(XGMAC_L4DP0, match);
1401
1398
1402
1399
ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);
1403
1400
if (ret)
+16
-23
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
+16
-23
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
···
12
12
static int dwxgmac2_get_tx_status(struct stmmac_extra_stats *x,
13
13
struct dma_desc *p, void __iomem *ioaddr)
14
14
{
15
-
unsigned int tdes3 = le32_to_cpu(p->des3);
15
+
u32 tdes3 = le32_to_cpu(p->des3);
16
16
int ret = tx_done;
17
17
18
18
if (unlikely(tdes3 & XGMAC_TDES3_OWN))
···
26
26
static int dwxgmac2_get_rx_status(struct stmmac_extra_stats *x,
27
27
struct dma_desc *p)
28
28
{
29
-
unsigned int rdes3 = le32_to_cpu(p->des3);
29
+
u32 rdes3 = le32_to_cpu(p->des3);
30
30
31
31
if (unlikely(rdes3 & XGMAC_RDES3_OWN))
32
32
return dma_own;
···
114
114
static int dwxgmac2_rx_check_timestamp(void *desc)
115
115
{
116
116
struct dma_desc *p = (struct dma_desc *)desc;
117
-
unsigned int rdes3 = le32_to_cpu(p->des3);
117
+
u32 rdes3 = le32_to_cpu(p->des3);
118
118
bool desc_valid, ts_valid;
119
119
120
120
dma_rmb();
···
135
135
u32 ats)
136
136
{
137
137
struct dma_desc *p = (struct dma_desc *)desc;
138
-
unsigned int rdes3 = le32_to_cpu(p->des3);
138
+
u32 rdes3 = le32_to_cpu(p->des3);
139
139
int ret = -EBUSY;
140
140
141
141
if (likely(rdes3 & XGMAC_RDES3_CDA))
···
162
162
bool csum_flag, int mode, bool tx_own,
163
163
bool ls, unsigned int tot_pkt_len)
164
164
{
165
-
unsigned int tdes3 = le32_to_cpu(p->des3);
165
+
u32 tdes3 = le32_to_cpu(p->des3);
166
166
167
167
p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L);
168
168
···
173
173
tdes3 &= ~XGMAC_TDES3_FD;
174
174
175
175
if (csum_flag)
176
-
tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT;
176
+
tdes3 |= FIELD_PREP(XGMAC_TDES3_CIC, 0x3);
177
177
else
178
178
tdes3 &= ~XGMAC_TDES3_CIC;
179
179
···
201
201
bool ls, unsigned int tcphdrlen,
202
202
unsigned int tcppayloadlen)
203
203
{
204
-
unsigned int tdes3 = le32_to_cpu(p->des3);
204
+
u32 tdes3 = le32_to_cpu(p->des3);
205
205
206
206
if (len1)
207
207
p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L);
208
208
if (len2)
209
-
p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) &
210
-
XGMAC_TDES2_B2L);
209
+
p->des2 |= cpu_to_le32(FIELD_PREP(XGMAC_TDES2_B2L, len2));
211
210
if (is_fs) {
212
211
tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE;
213
-
tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) &
214
-
XGMAC_TDES3_THL;
215
-
tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL;
212
+
tdes3 |= FIELD_PREP(XGMAC_TDES3_THL, tcphdrlen);
213
+
tdes3 |= FIELD_PREP(XGMAC_TDES3_TPL, tcppayloadlen);
216
214
} else {
217
215
tdes3 &= ~XGMAC_TDES3_FD;
218
216
}
···
272
274
static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,
273
275
enum pkt_hash_types *type)
274
276
{
275
-
unsigned int rdes3 = le32_to_cpu(p->des3);
277
+
u32 rdes3 = le32_to_cpu(p->des3);
276
278
u32 ptype;
277
279
278
280
if (rdes3 & XGMAC_RDES3_RSV) {
279
-
ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT;
281
+
ptype = FIELD_GET(XGMAC_RDES3_L34T, rdes3);
280
282
281
283
switch (ptype) {
282
284
case XGMAC_L34T_IP4TCP:
···
311
313
312
314
static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)
313
315
{
314
-
sarc_type <<= XGMAC_TDES3_SAIC_SHIFT;
315
-
316
-
p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC);
316
+
p->des3 |= cpu_to_le32(FIELD_PREP(XGMAC_TDES3_SAIC, sarc_type));
317
317
}
318
318
319
319
static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
···
324
328
325
329
/* Inner VLAN */
326
330
if (inner_type) {
327
-
u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT;
331
+
u32 des = FIELD_PREP(XGMAC_TDES2_IVT, inner_tag);
328
332
329
-
des &= XGMAC_TDES2_IVT;
330
333
p->des2 = cpu_to_le32(des);
331
334
332
-
des = inner_type << XGMAC_TDES3_IVTIR_SHIFT;
333
-
des &= XGMAC_TDES3_IVTIR;
335
+
des = FIELD_PREP(XGMAC_TDES3_IVTIR, inner_type);
334
336
p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV);
335
337
}
336
338
···
341
347
342
348
static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)
343
349
{
344
-
type <<= XGMAC_TDES2_VTIR_SHIFT;
345
-
p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);
350
+
p->des2 |= cpu_to_le32(FIELD_PREP(XGMAC_TDES2_VTIR, type));
346
351
}
347
352
348
353
static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
+33
-42
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+33
-42
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
···
55
55
u32 value;
56
56
57
57
value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
58
-
value &= ~XGMAC_RxPBL;
59
-
value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
58
+
value = u32_replace_bits(value, rxpbl, XGMAC_RxPBL);
60
59
writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
61
60
62
61
writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
···
71
72
u32 value;
72
73
73
74
value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
74
-
value &= ~XGMAC_TxPBL;
75
-
value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
76
-
value |= XGMAC_OSP;
75
+
value = u32_replace_bits(value, txpbl, XGMAC_TxPBL);
77
76
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
78
77
79
78
writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
···
87
90
if (axi->axi_xit_frm)
88
91
value |= XGMAC_LPI_XIT_PKT;
89
92
90
-
value &= ~XGMAC_WR_OSR_LMT;
91
-
value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
92
-
XGMAC_WR_OSR_LMT;
93
-
94
-
value &= ~XGMAC_RD_OSR_LMT;
95
-
value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
96
-
XGMAC_RD_OSR_LMT;
93
+
value = u32_replace_bits(value, axi->axi_wr_osr_lmt, XGMAC_WR_OSR_LMT);
94
+
value = u32_replace_bits(value, axi->axi_rd_osr_lmt, XGMAC_RD_OSR_LMT);
97
95
98
96
if (!axi->axi_fb)
99
97
value |= XGMAC_UNDEF;
···
119
127
{
120
128
u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
121
129
unsigned int rqs = fifosz / 256 - 1;
130
+
unsigned int rtc;
122
131
123
132
if (mode == SF_DMA_MODE) {
124
133
value |= XGMAC_RSF;
125
134
} else {
126
135
value &= ~XGMAC_RSF;
127
-
value &= ~XGMAC_RTC;
128
136
129
137
if (mode <= 64)
130
-
value |= 0x0 << XGMAC_RTC_SHIFT;
138
+
rtc = 0x0;
131
139
else if (mode <= 96)
132
-
value |= 0x2 << XGMAC_RTC_SHIFT;
140
+
rtc = 0x2;
133
141
else
134
-
value |= 0x3 << XGMAC_RTC_SHIFT;
142
+
rtc = 0x3;
143
+
144
+
value = u32_replace_bits(value, rtc, XGMAC_RTC);
135
145
}
136
146
137
-
value &= ~XGMAC_RQS;
138
-
value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
147
+
value = u32_replace_bits(value, rqs, XGMAC_RQS);
139
148
140
149
if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
141
150
u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
···
165
172
break;
166
173
}
167
174
168
-
flow &= ~XGMAC_RFD;
169
-
flow |= rfd << XGMAC_RFD_SHIFT;
170
-
171
-
flow &= ~XGMAC_RFA;
172
-
flow |= rfa << XGMAC_RFA_SHIFT;
175
+
flow = u32_replace_bits(flow, rfd, XGMAC_RFD);
176
+
flow = u32_replace_bits(flow, rfa, XGMAC_RFA);
173
177
174
178
writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
175
179
}
···
179
189
{
180
190
u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
181
191
unsigned int tqs = fifosz / 256 - 1;
192
+
unsigned int ttc, txqen;
182
193
183
194
if (mode == SF_DMA_MODE) {
184
195
value |= XGMAC_TSF;
185
196
} else {
186
197
value &= ~XGMAC_TSF;
187
-
value &= ~XGMAC_TTC;
188
198
189
199
if (mode <= 64)
190
-
value |= 0x0 << XGMAC_TTC_SHIFT;
200
+
ttc = 0x0;
191
201
else if (mode <= 96)
192
-
value |= 0x2 << XGMAC_TTC_SHIFT;
202
+
ttc = 0x2;
193
203
else if (mode <= 128)
194
-
value |= 0x3 << XGMAC_TTC_SHIFT;
204
+
ttc = 0x3;
195
205
else if (mode <= 192)
196
-
value |= 0x4 << XGMAC_TTC_SHIFT;
206
+
ttc = 0x4;
197
207
else if (mode <= 256)
198
-
value |= 0x5 << XGMAC_TTC_SHIFT;
208
+
ttc = 0x5;
199
209
else if (mode <= 384)
200
-
value |= 0x6 << XGMAC_TTC_SHIFT;
210
+
ttc = 0x6;
201
211
else
202
-
value |= 0x7 << XGMAC_TTC_SHIFT;
212
+
ttc = 0x7;
213
+
214
+
value = u32_replace_bits(value, ttc, XGMAC_TTC);
203
215
}
204
216
205
217
/* Use static TC to Queue mapping */
206
-
value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
218
+
value |= FIELD_PREP(XGMAC_Q2TCMAP, channel);
207
219
208
-
value &= ~XGMAC_TXQEN;
209
220
if (qmode != MTL_QUEUE_AVB)
210
-
value |= 0x2 << XGMAC_TXQEN_SHIFT;
221
+
txqen = 0x2;
211
222
else
212
-
value |= 0x1 << XGMAC_TXQEN_SHIFT;
223
+
txqen = 0x1;
213
224
214
-
value &= ~XGMAC_TQS;
215
-
value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
225
+
value = u32_replace_bits(value, txqen, XGMAC_TXQEN);
226
+
value = u32_replace_bits(value, tqs, XGMAC_TQS);
216
227
217
228
writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
218
229
}
···
517
526
{
518
527
u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
519
528
u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL);
529
+
unsigned int txqen;
520
530
521
-
value &= ~XGMAC_TXQEN;
522
531
if (qmode != MTL_QUEUE_AVB) {
523
-
value |= 0x2 << XGMAC_TXQEN_SHIFT;
532
+
txqen = 0x2;
524
533
writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
525
534
} else {
526
-
value |= 0x1 << XGMAC_TXQEN_SHIFT;
535
+
txqen = 0x1;
527
536
writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL);
528
537
}
529
538
539
+
value = u32_replace_bits(value, txqen, XGMAC_TXQEN);
530
540
writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
531
541
}
532
542
···
537
545
u32 value;
538
546
539
547
value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
540
-
value &= ~XGMAC_RBSZ;
541
-
value |= bfsize << XGMAC_RBSZ_SHIFT;
548
+
value = u32_replace_bits(value, bfsize, XGMAC_RBSZ);
542
549
writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
543
550
}
544
551
+12
-15
drivers/net/ethernet/stmicro/stmmac/enh_desc.c
+12
-15
drivers/net/ethernet/stmicro/stmmac/enh_desc.c
···
15
15
static int enh_desc_get_tx_status(struct stmmac_extra_stats *x,
16
16
struct dma_desc *p, void __iomem *ioaddr)
17
17
{
18
-
unsigned int tdes0 = le32_to_cpu(p->des0);
18
+
u32 tdes0 = le32_to_cpu(p->des0);
19
19
int ret = tx_done;
20
20
21
21
/* Get tx owner first */
···
44
44
if (unlikely((tdes0 & ETDES0_LATE_COLLISION) ||
45
45
(tdes0 & ETDES0_EXCESSIVE_COLLISIONS)))
46
46
x->tx_collision +=
47
-
(tdes0 & ETDES0_COLLISION_COUNT_MASK) >> 3;
47
+
FIELD_GET(ETDES0_COLLISION_COUNT_MASK, tdes0);
48
48
49
49
if (unlikely(tdes0 & ETDES0_EXCESSIVE_DEFERRAL))
50
50
x->tx_deferred++;
···
117
117
static void enh_desc_get_ext_status(struct stmmac_extra_stats *x,
118
118
struct dma_extended_desc *p)
119
119
{
120
-
unsigned int rdes0 = le32_to_cpu(p->basic.des0);
121
-
unsigned int rdes4 = le32_to_cpu(p->des4);
120
+
u32 rdes0 = le32_to_cpu(p->basic.des0);
121
+
u32 rdes4 = le32_to_cpu(p->des4);
122
122
123
123
if (unlikely(rdes0 & ERDES0_RX_MAC_ADDR)) {
124
-
int message_type = (rdes4 & ERDES4_MSG_TYPE_MASK) >> 8;
124
+
int message_type = FIELD_GET(ERDES4_MSG_TYPE_MASK, rdes4);
125
125
126
126
if (rdes4 & ERDES4_IP_HDR_ERR)
127
127
x->ip_hdr_err++;
···
167
167
x->av_pkt_rcvd++;
168
168
if (rdes4 & ERDES4_AV_TAGGED_PKT_RCVD)
169
169
x->av_tagged_pkt_rcvd++;
170
-
if ((rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK) >> 18)
170
+
if (rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK)
171
171
x->vlan_tag_priority_val++;
172
172
if (rdes4 & ERDES4_L3_FILTER_MATCH)
173
173
x->l3_filter_match++;
174
174
if (rdes4 & ERDES4_L4_FILTER_MATCH)
175
175
x->l4_filter_match++;
176
-
if ((rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK) >> 26)
176
+
if (rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK)
177
177
x->l3_l4_filter_no_match++;
178
178
}
179
179
}
···
181
181
static int enh_desc_get_rx_status(struct stmmac_extra_stats *x,
182
182
struct dma_desc *p)
183
183
{
184
-
unsigned int rdes0 = le32_to_cpu(p->des0);
184
+
u32 rdes0 = le32_to_cpu(p->des0);
185
185
int ret = good_frame;
186
186
187
187
if (unlikely(rdes0 & RDES0_OWN))
···
312
312
bool csum_flag, int mode, bool tx_own,
313
313
bool ls, unsigned int tot_pkt_len)
314
314
{
315
-
unsigned int tdes0 = le32_to_cpu(p->des0);
315
+
u32 tdes0 = le32_to_cpu(p->des0);
316
316
317
317
if (mode == STMMAC_CHAIN_MODE)
318
318
enh_set_tx_desc_len_on_chain(p, len);
···
324
324
else
325
325
tdes0 &= ~ETDES0_FIRST_SEGMENT;
326
326
327
-
if (likely(csum_flag))
328
-
tdes0 |= (TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
329
-
else
330
-
tdes0 &= ~(TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
327
+
tdes0 = u32_replace_bits(tdes0, csum_flag ? TX_CIC_FULL : 0,
328
+
ETDES0_CHECKSUM_INSERTION_MASK);
331
329
332
330
if (ls)
333
331
tdes0 |= ETDES0_LAST_SEGMENT;
···
361
363
if (rx_coe_type == STMMAC_RX_COE_TYPE1)
362
364
csum = 2;
363
365
364
-
return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)
365
-
>> RDES0_FRAME_LEN_SHIFT) - csum);
366
+
return FIELD_GET(RDES0_FRAME_LEN_MASK, le32_to_cpu(p->des0)) - csum;
366
367
}
367
368
368
369
static void enh_desc_enable_tx_timestamp(struct dma_desc *p)
+9
-16
drivers/net/ethernet/stmicro/stmmac/norm_desc.c
+9
-16
drivers/net/ethernet/stmicro/stmmac/norm_desc.c
···
15
15
static int ndesc_get_tx_status(struct stmmac_extra_stats *x,
16
16
struct dma_desc *p, void __iomem *ioaddr)
17
17
{
18
-
unsigned int tdes0 = le32_to_cpu(p->des0);
19
-
unsigned int tdes1 = le32_to_cpu(p->des1);
18
+
u32 tdes0 = le32_to_cpu(p->des0);
19
+
u32 tdes1 = le32_to_cpu(p->des1);
20
20
int ret = tx_done;
21
21
22
22
/* Get tx owner first */
···
40
40
if (unlikely((tdes0 & TDES0_EXCESSIVE_DEFERRAL) ||
41
41
(tdes0 & TDES0_EXCESSIVE_COLLISIONS) ||
42
42
(tdes0 & TDES0_LATE_COLLISION))) {
43
-
unsigned int collisions;
44
-
45
-
collisions = (tdes0 & TDES0_COLLISION_COUNT_MASK) >> 3;
46
-
x->tx_collision += collisions;
43
+
x->tx_collision +=
44
+
FIELD_GET(TDES0_COLLISION_COUNT_MASK, tdes0);
47
45
}
48
46
ret = tx_err;
49
47
}
···
67
69
static int ndesc_get_rx_status(struct stmmac_extra_stats *x,
68
70
struct dma_desc *p)
69
71
{
72
+
u32 rdes0 = le32_to_cpu(p->des0);
70
73
int ret = good_frame;
71
-
unsigned int rdes0 = le32_to_cpu(p->des0);
72
74
73
75
if (unlikely(rdes0 & RDES0_OWN))
74
76
return dma_own;
···
176
178
bool csum_flag, int mode, bool tx_own,
177
179
bool ls, unsigned int tot_pkt_len)
178
180
{
179
-
unsigned int tdes1 = le32_to_cpu(p->des1);
181
+
u32 tdes1 = le32_to_cpu(p->des1);
180
182
181
183
if (is_fs)
182
184
tdes1 |= TDES1_FIRST_SEGMENT;
183
185
else
184
186
tdes1 &= ~TDES1_FIRST_SEGMENT;
185
187
186
-
if (likely(csum_flag))
187
-
tdes1 |= (TX_CIC_FULL) << TDES1_CHECKSUM_INSERTION_SHIFT;
188
-
else
189
-
tdes1 &= ~(TX_CIC_FULL << TDES1_CHECKSUM_INSERTION_SHIFT);
188
+
tdes1 = u32_replace_bits(tdes1, csum_flag ? TX_CIC_FULL : 0,
189
+
TDES1_CHECKSUM_INSERTION_MASK);
190
190
191
191
if (ls)
192
192
tdes1 |= TDES1_LAST_SEGMENT;
···
218
222
if (rx_coe_type == STMMAC_RX_COE_TYPE1)
219
223
csum = 2;
220
224
221
-
return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)
222
-
>> RDES0_FRAME_LEN_SHIFT) -
223
-
csum);
224
-
225
+
return FIELD_GET(RDES0_FRAME_LEN_MASK, le32_to_cpu(p->des0)) - csum;
225
226
}
226
227
227
228
static void ndesc_enable_tx_timestamp(struct dma_desc *p)