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arm: perf: Convert remaining fields to use GENMASK

Convert the remaining fields to use either GENMASK or be built from
other fields. These all already started at bit 0 so don't need a code
change for the lack of _SHIFT.

Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20231211161331.1277825-5-james.clark@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

authored by

James Clark and committed by
Will Deacon d30f09b6 2f6a00f3

+14 -6
+1 -1
drivers/perf/arm_pmuv3.c
··· 675 675 value = read_pmovsclr(); 676 676 677 677 /* Write to clear flags */ 678 - value &= ARMV8_PMU_OVSR_MASK; 678 + value &= ARMV8_PMU_OVERFLOWED_MASK; 679 679 write_pmovsclr(value); 680 680 681 681 return value;
+13 -5
include/linux/perf/arm_pmuv3.h
··· 216 216 #define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */ 217 217 #define ARMV8_PMU_PMCR_LP (1 << 7) /* Long event counter enable */ 218 218 #define ARMV8_PMU_PMCR_N GENMASK(15, 11) /* Number of counters supported */ 219 - #define ARMV8_PMU_PMCR_MASK 0xff /* Mask for writable bits */ 219 + /* Mask for writable bits */ 220 + #define ARMV8_PMU_PMCR_MASK (ARMV8_PMU_PMCR_E | ARMV8_PMU_PMCR_P | \ 221 + ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_D | \ 222 + ARMV8_PMU_PMCR_X | ARMV8_PMU_PMCR_DP | \ 223 + ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP) 220 224 221 225 /* 222 226 * PMOVSR: counters overflow flag status reg 223 227 */ 224 - #define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */ 225 - #define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK 228 + #define ARMV8_PMU_OVSR_P GENMASK(30, 0) 229 + #define ARMV8_PMU_OVSR_C BIT(31) 230 + /* Mask for writable bits is both P and C fields */ 231 + #define ARMV8_PMU_OVERFLOWED_MASK (ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C) 226 232 227 233 /* 228 234 * PMXEVTYPER: Event selection reg 229 235 */ 230 236 #define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */ 231 - #define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */ 237 + #define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0) /* Mask for EVENT bits */ 232 238 233 239 /* 234 240 * Event filters for PMUv3 ··· 249 243 /* 250 244 * PMUSERENR: user enable reg 251 245 */ 252 - #define ARMV8_PMU_USERENR_MASK 0xf /* Mask for writable bits */ 253 246 #define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */ 254 247 #define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */ 255 248 #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ 256 249 #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ 250 + /* Mask for writable bits */ 251 + #define ARMV8_PMU_USERENR_MASK (ARMV8_PMU_USERENR_EN | ARMV8_PMU_USERENR_SW | \ 252 + ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_ER) 257 253 258 254 /* PMMIR_EL1.SLOTS mask */ 259 255 #define ARMV8_PMU_SLOTS GENMASK(7, 0)