Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
platform/x86/intel/pmc: Add Panther Lake support to intel_pmc_core
Add Panther Lake support to intel_pmc_core driver
Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com>
Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
Link: https://lore.kernel.org/r/20250214214416.10150-2-xi.pardee@linux.intel.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
authored by
Xi Pardee
and committed by
Ilpo Järvinen
d31feed7
8d5316c6
+561
-1
+1
-1
drivers/platform/x86/intel/pmc/Makefile
+1
-1
drivers/platform/x86/intel/pmc/Makefile
···
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#
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intel_pmc_core-y := core.o core_ssram.o spt.o cnp.o \
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-
icl.o tgl.o adl.o mtl.o arl.o lnl.o
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+
icl.o tgl.o adl.o mtl.o arl.o lnl.o ptl.o
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obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
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intel_pmc_core_pltdrv-y := pltdrv.o
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obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o
+1
drivers/platform/x86/intel/pmc/core.c
+1
drivers/platform/x86/intel/pmc/core.c
+9
drivers/platform/x86/intel/pmc/core.h
+9
drivers/platform/x86/intel/pmc/core.h
···
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285
#define LNL_PPFEAR_NUM_ENTRIES 12
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#define LNL_S0IX_BLOCKER_OFFSET 0x2004
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/* Panther Lake Power Management Controller register offsets */
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#define PTL_LPM_NUM_MAPS 14
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#define PTL_PMC_LTR_SATA2 0x1B90
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#define PTL_PMC_LTR_PMC 0x1BA8
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#define PTL_PMC_LTR_CUR_ASLT 0x1C28
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#define PTL_PMC_LTR_CUR_PLT 0x1C2C
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#define PTL_PCD_PMC_MMIO_REG_LEN 0x31A8
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+
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extern const char *pmc_lpm_modes[];
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struct pmc_bit_map {
···
634
626
extern struct pmc_dev_info arl_pmc_dev;
635
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extern struct pmc_dev_info arl_h_pmc_dev;
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extern struct pmc_dev_info lnl_pmc_dev;
629
+
extern struct pmc_dev_info ptl_pmc_dev;
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void cnl_suspend(struct pmc_dev *pmcdev);
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int cnl_resume(struct pmc_dev *pmcdev);
+550
drivers/platform/x86/intel/pmc/ptl.c
+550
drivers/platform/x86/intel/pmc/ptl.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
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+
/*
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+
* This file contains platform specific structure definitions
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* and init function used by Panther Lake PCH.
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+
*
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* Copyright (c) 2025, Intel Corporation.
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+
*/
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+
9
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#include <linux/pci.h>
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+
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#include "core.h"
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+
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static const struct pmc_bit_map ptl_pcdp_pfear_map[] = {
14
+
{"PMC_0", BIT(0)},
15
+
{"FUSE_OSSE", BIT(1)},
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+
{"ESPISPI", BIT(2)},
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+
{"XHCI", BIT(3)},
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+
{"SPA", BIT(4)},
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{"SPB", BIT(5)},
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+
{"MPFPW2", BIT(6)},
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+
{"GBE", BIT(7)},
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+
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{"SBR16B20", BIT(0)},
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{"SBR8B20", BIT(1)},
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+
{"SBR16B21", BIT(2)},
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{"DBG_SBR16B", BIT(3)},
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+
{"OSSE_HOTHAM", BIT(4)},
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+
{"D2D_DISP_1", BIT(5)},
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+
{"LPSS", BIT(6)},
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{"LPC", BIT(7)},
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+
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{"SMB", BIT(0)},
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{"ISH", BIT(1)},
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+
{"SBR16B2", BIT(2)},
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+
{"NPK_0", BIT(3)},
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+
{"D2D_NOC_1", BIT(4)},
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+
{"SBR8B2", BIT(5)},
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+
{"FUSE", BIT(6)},
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+
{"SBR16B0", BIT(7)},
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+
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{"PSF0", BIT(0)},
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{"XDCI", BIT(1)},
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{"EXI", BIT(2)},
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{"CSE", BIT(3)},
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{"KVMCC", BIT(4)},
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{"PMT", BIT(5)},
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{"CLINK", BIT(6)},
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{"PTIO", BIT(7)},
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+
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{"USBR0", BIT(0)},
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{"SUSRAM", BIT(1)},
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{"SMT1", BIT(2)},
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{"MPFPW1", BIT(3)},
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+
{"SMS2", BIT(4)},
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+
{"SMS1", BIT(5)},
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+
{"CSMERTC", BIT(6)},
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{"CSMEPSF", BIT(7)},
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+
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{"D2D_NOC_0", BIT(0)},
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{"ESE", BIT(1)},
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{"P2SB8B", BIT(2)},
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{"SBR16B7", BIT(3)},
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{"SBR16B3", BIT(4)},
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+
{"OSSE_SMT1", BIT(5)},
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{"D2D_DISP", BIT(6)},
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{"DBG_SBR", BIT(7)},
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+
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{"U3FPW1", BIT(0)},
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+
{"FIA_X", BIT(1)},
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{"PSF4", BIT(2)},
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{"CNVI", BIT(3)},
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+
{"UFSX2", BIT(4)},
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{"ENDBG", BIT(5)},
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{"DBC", BIT(6)},
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{"FIA_PG", BIT(7)},
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+
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{"D2D_IPU", BIT(0)},
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+
{"NPK1", BIT(1)},
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+
{"FIACPCB_X", BIT(2)},
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+
{"SBR8B4", BIT(3)},
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+
{"DBG_PSF", BIT(4)},
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+
{"PSF6", BIT(5)},
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{"UFSPW1", BIT(6)},
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+
{"FIA_U", BIT(7)},
85
+
86
+
{"PSF8", BIT(0)},
87
+
{"SBR16B4", BIT(1)},
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{"SBR16B5", BIT(2)},
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+
{"FIACPCB_U", BIT(3)},
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+
{"TAM", BIT(4)},
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+
{"D2D_NOC_2", BIT(5)},
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+
{"TBTLSX", BIT(6)},
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+
{"THC0", BIT(7)},
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+
95
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{"THC1", BIT(0)},
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+
{"PMC_1", BIT(1)},
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+
{"SBR8B1", BIT(2)},
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{"TCSS", BIT(3)},
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+
{"DISP_PGA", BIT(4)},
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+
{"SBR16B1", BIT(5)},
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+
{"SBRG", BIT(6)},
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+
{"PSF5", BIT(7)},
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+
104
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{"P2SB16B", BIT(0)},
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+
{"ACE_0", BIT(1)},
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+
{"ACE_1", BIT(2)},
107
+
{"ACE_2", BIT(3)},
108
+
{"ACE_3", BIT(4)},
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+
{"ACE_4", BIT(5)},
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+
{"ACE_5", BIT(6)},
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+
{"ACE_6", BIT(7)},
112
+
113
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{"ACE_7", BIT(0)},
114
+
{"ACE_8", BIT(1)},
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+
{"ACE_9", BIT(2)},
116
+
{"ACE_10", BIT(3)},
117
+
{"FIACPCB_PG", BIT(4)},
118
+
{"SBR16B6", BIT(5)},
119
+
{"OSSE", BIT(6)},
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{"SBR8B0", BIT(7)},
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{}
122
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};
123
+
124
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static const struct pmc_bit_map *ext_ptl_pcdp_pfear_map[] = {
125
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ptl_pcdp_pfear_map,
126
+
NULL
127
+
};
128
+
129
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static const struct pmc_bit_map ptl_pcdp_ltr_show_map[] = {
130
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{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
131
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{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
132
+
{"SATA", CNP_PMC_LTR_SATA},
133
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{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
134
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{"XHCI", CNP_PMC_LTR_XHCI},
135
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{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
136
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{"ME", CNP_PMC_LTR_ME},
137
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{"SATA1", CNP_PMC_LTR_EVA},
138
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{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
139
+
{"HD_AUDIO", CNP_PMC_LTR_AZ},
140
+
{"CNV", CNP_PMC_LTR_CNV},
141
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{"LPSS", CNP_PMC_LTR_LPSS},
142
+
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
143
+
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
144
+
{"SATA2", PTL_PMC_LTR_SATA2},
145
+
{"ESPI", CNP_PMC_LTR_ESPI},
146
+
{"SCC", CNP_PMC_LTR_SCC},
147
+
{"ISH", CNP_PMC_LTR_ISH},
148
+
{"UFSX2", CNP_PMC_LTR_UFSX2},
149
+
{"EMMC", CNP_PMC_LTR_EMMC},
150
+
{"WIGIG", ICL_PMC_LTR_WIGIG},
151
+
{"THC0", TGL_PMC_LTR_THC0},
152
+
{"THC1", TGL_PMC_LTR_THC1},
153
+
{"SOUTHPORT_G", MTL_PMC_LTR_SPG},
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+
{"ESE", MTL_PMC_LTR_ESE},
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+
{"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
156
+
{"DMI3", ARL_PMC_LTR_DMI3},
157
+
{"OSSE", LNL_PMC_LTR_OSSE},
158
+
159
+
/* Below two cannot be used for LTR_IGNORE */
160
+
{"CURRENT_PLATFORM", PTL_PMC_LTR_CUR_PLT},
161
+
{"AGGREGATED_SYSTEM", PTL_PMC_LTR_CUR_ASLT},
162
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{}
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+
};
164
+
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static const struct pmc_bit_map ptl_pcdp_clocksource_status_map[] = {
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{"AON2_OFF_STS", BIT(0), 1},
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{"AON3_OFF_STS", BIT(1), 0},
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+
{"AON4_OFF_STS", BIT(2), 1},
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+
{"AON5_OFF_STS", BIT(3), 1},
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+
{"AON1_OFF_STS", BIT(4), 0},
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{"XTAL_LVM_OFF_STS", BIT(5), 0},
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+
{"MPFPW1_0_PLL_OFF_STS", BIT(6), 1},
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+
{"USB3_PLL_OFF_STS", BIT(8), 1},
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+
{"AON3_SPL_OFF_STS", BIT(9), 1},
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+
{"MPFPW2_0_PLL_OFF_STS", BIT(12), 1},
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+
{"XTAL_AGGR_OFF_STS", BIT(17), 1},
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+
{"USB2_PLL_OFF_STS", BIT(18), 0},
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+
{"SAF_PLL_OFF_STS", BIT(19), 1},
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+
{"SE_TCSS_PLL_OFF_STS", BIT(20), 1},
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+
{"DDI_PLL_OFF_STS", BIT(21), 1},
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{"FILTER_PLL_OFF_STS", BIT(22), 1},
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+
{"ACE_PLL_OFF_STS", BIT(24), 0},
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+
{"FABRIC_PLL_OFF_STS", BIT(25), 1},
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+
{"SOC_PLL_OFF_STS", BIT(26), 1},
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+
{"REF_PLL_OFF_STS", BIT(28), 1},
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+
{"IMG_PLL_OFF_STS", BIT(29), 1},
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{"RTC_PLL_OFF_STS", BIT(31), 0},
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{}
189
+
};
190
+
191
+
static const struct pmc_bit_map ptl_pcdp_power_gating_status_0_map[] = {
192
+
{"PMC_PGD0_PG_STS", BIT(0), 0},
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{"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0},
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+
{"ESPISPI_PGD0_PG_STS", BIT(2), 0},
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+
{"XHCI_PGD0_PG_STS", BIT(3), 1},
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+
{"SPA_PGD0_PG_STS", BIT(4), 1},
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+
{"SPB_PGD0_PG_STS", BIT(5), 1},
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{"MPFPW2_PGD0_PG_STS", BIT(6), 0},
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{"GBE_PGD0_PG_STS", BIT(7), 1},
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{"SBR16B20_PGD0_PG_STS", BIT(8), 0},
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+
{"SBR8B20_PGD0_PG_STS", BIT(9), 0},
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{"SBR16B21_PGD0_PG_STS", BIT(10), 0},
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{"DBG_PGD0_PG_STS", BIT(11), 0},
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+
{"OSSE_HOTHAM_PGD0_PG_STS", BIT(12), 1},
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{"D2D_DISP_PGD1_PG_STS", BIT(13), 1},
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{"LPSS_PGD0_PG_STS", BIT(14), 1},
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{"LPC_PGD0_PG_STS", BIT(15), 0},
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+
{"SMB_PGD0_PG_STS", BIT(16), 0},
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{"ISH_PGD0_PG_STS", BIT(17), 0},
210
+
{"SBR16B2_PGD0_PG_STS", BIT(18), 0},
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+
{"NPK_PGD0_PG_STS", BIT(19), 0},
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+
{"D2D_NOC_PGD1_PG_STS", BIT(20), 1},
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+
{"SBR8B2_PGD0_PG_STS", BIT(21), 0},
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+
{"FUSE_PGD0_PG_STS", BIT(22), 0},
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{"SBR16B0_PGD0_PG_STS", BIT(23), 0},
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{"PSF0_PGD0_PG_STS", BIT(24), 0},
217
+
{"XDCI_PGD0_PG_STS", BIT(25), 1},
218
+
{"EXI_PGD0_PG_STS", BIT(26), 0},
219
+
{"CSE_PGD0_PG_STS", BIT(27), 1},
220
+
{"KVMCC_PGD0_PG_STS", BIT(28), 1},
221
+
{"PMT_PGD0_PG_STS", BIT(29), 1},
222
+
{"CLINK_PGD0_PG_STS", BIT(30), 1},
223
+
{"PTIO_PGD0_PG_STS", BIT(31), 1},
224
+
{}
225
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};
226
+
227
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static const struct pmc_bit_map ptl_pcdp_power_gating_status_1_map[] = {
228
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{"USBR0_PGD0_PG_STS", BIT(0), 1},
229
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{"SUSRAM_PGD0_PG_STS", BIT(1), 1},
230
+
{"SMT1_PGD0_PG_STS", BIT(2), 1},
231
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{"MPFPW1_PGD0_PG_STS", BIT(3), 0},
232
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{"SMS2_PGD0_PG_STS", BIT(4), 1},
233
+
{"SMS1_PGD0_PG_STS", BIT(5), 1},
234
+
{"CSMERTC_PGD0_PG_STS", BIT(6), 0},
235
+
{"CSMEPSF_PGD0_PG_STS", BIT(7), 0},
236
+
{"D2D_NOC_PGD0_PG_STS", BIT(8), 0},
237
+
{"ESE_PGD0_PG_STS", BIT(9), 1},
238
+
{"P2SB8B_PGD0_PG_STS", BIT(10), 1},
239
+
{"SBR16B7_PGD0_PG_STS", BIT(11), 0},
240
+
{"SBR16B3_PGD0_PG_STS", BIT(12), 0},
241
+
{"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1},
242
+
{"D2D_DISP_PGD0_PG_STS", BIT(14), 1},
243
+
{"DBG_SBR_PGD0_PG_STS", BIT(15), 0},
244
+
{"U3FPW1_PGD0_PG_STS", BIT(16), 0},
245
+
{"FIA_X_PGD0_PG_STS", BIT(17), 0},
246
+
{"PSF4_PGD0_PG_STS", BIT(18), 0},
247
+
{"CNVI_PGD0_PG_STS", BIT(19), 0},
248
+
{"UFSX2_PGD0_PG_STS", BIT(20), 1},
249
+
{"ENDBG_PGD0_PG_STS", BIT(21), 0},
250
+
{"DBC_PGD0_PG_STS", BIT(22), 0},
251
+
{"FIA_PG_PGD0_PG_STS", BIT(23), 0},
252
+
{"D2D_IPU_PGD0_PG_STS", BIT(24), 1},
253
+
{"NPK_PGD1_PG_STS", BIT(25), 0},
254
+
{"FIACPCB_X_PGD0_PG_STS", BIT(26), 0},
255
+
{"SBR8B4_PGD0_PG_STS", BIT(27), 0},
256
+
{"DBG_PSF_PGD0_PG_STS", BIT(28), 0},
257
+
{"PSF6_PGD0_PG_STS", BIT(29), 0},
258
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{"UFSPW1_PGD0_PG_STS", BIT(30), 0},
259
+
{"FIA_U_PGD0_PG_STS", BIT(31), 0},
260
+
{}
261
+
};
262
+
263
+
static const struct pmc_bit_map ptl_pcdp_power_gating_status_2_map[] = {
264
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{"PSF8_PGD0_PG_STS", BIT(0), 0},
265
+
{"SBR16B4_PGD0_PG_STS", BIT(1), 0},
266
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{"SBR16B5_PGD0_PG_STS", BIT(2), 0},
267
+
{"FIACPCB_U_PGD0_PG_STS", BIT(3), 0},
268
+
{"TAM_PGD0_PG_STS", BIT(4), 1},
269
+
{"D2D_NOC_PGD0_PG_STS", BIT(5), 1},
270
+
{"TBTLSX_PGD0_PG_STS", BIT(6), 1},
271
+
{"THC0_PGD0_PG_STS", BIT(7), 1},
272
+
{"THC1_PGD0_PG_STS", BIT(8), 1},
273
+
{"PMC_PGD1_PG_STS", BIT(9), 0},
274
+
{"SBR8B1_PGD0_PG_STS", BIT(10), 0},
275
+
{"TCSS_PGD0_PG_STS", BIT(11), 0},
276
+
{"DISP_PGA_PGD0_PG_STS", BIT(12), 0},
277
+
{"SBR16B1_PGD0_PG_STS", BIT(13), 0},
278
+
{"SBRG_PGD0_PG_STS", BIT(14), 0},
279
+
{"PSF5_PGD0_PG_STS", BIT(15), 0},
280
+
{"P2SB16B_PGD0_PG_STS", BIT(16), 1},
281
+
{"ACE_PGD0_PG_STS", BIT(17), 0},
282
+
{"ACE_PGD1_PG_STS", BIT(18), 0},
283
+
{"ACE_PGD2_PG_STS", BIT(19), 0},
284
+
{"ACE_PGD3_PG_STS", BIT(20), 0},
285
+
{"ACE_PGD4_PG_STS", BIT(21), 0},
286
+
{"ACE_PGD5_PG_STS", BIT(22), 0},
287
+
{"ACE_PGD6_PG_STS", BIT(23), 0},
288
+
{"ACE_PGD7_PG_STS", BIT(24), 0},
289
+
{"ACE_PGD8_PG_STS", BIT(25), 0},
290
+
{"ACE_PGD9_PG_STS", BIT(26), 0},
291
+
{"ACE_PGD10_PG_STS", BIT(27), 0},
292
+
{"FIACPCB_PG_PGD0_PG_STS", BIT(28), 0},
293
+
{"SBR16B6_PGD0_PG_STS", BIT(29), 0},
294
+
{"OSSE_PGD0_PG_STS", BIT(30), 1},
295
+
{"SBR8B0_PGD0_PG_STS", BIT(31), 0},
296
+
{}
297
+
};
298
+
299
+
static const struct pmc_bit_map ptl_pcdp_d3_status_0_map[] = {
300
+
{"LPSS_D3_STS", BIT(3), 1},
301
+
{"XDCI_D3_STS", BIT(4), 1},
302
+
{"XHCI_D3_STS", BIT(5), 1},
303
+
{"OSSE_D3_STS", BIT(6), 0},
304
+
{"SPA_D3_STS", BIT(12), 0},
305
+
{"SPB_D3_STS", BIT(13), 0},
306
+
{"ESPISPI_D3_STS", BIT(18), 0},
307
+
{"PSTH_D3_STS", BIT(21), 0},
308
+
{"OSSE_SMT1_D3_STS", BIT(30), 0},
309
+
{}
310
+
};
311
+
312
+
static const struct pmc_bit_map ptl_pcdp_d3_status_1_map[] = {
313
+
{"GBE_D3_STS", BIT(19), 0},
314
+
{"ITSS_D3_STS", BIT(23), 0},
315
+
{"CNVI_D3_STS", BIT(27), 0},
316
+
{"UFSX2_D3_STS", BIT(28), 1},
317
+
{"OSSE_HOTHAM_D3_STS", BIT(29), 0},
318
+
{"ESE_D3_STS", BIT(30), 0},
319
+
{}
320
+
};
321
+
322
+
static const struct pmc_bit_map ptl_pcdp_d3_status_2_map[] = {
323
+
{"CSMERTC_D3_STS", BIT(1), 0},
324
+
{"SUSRAM_D3_STS", BIT(2), 0},
325
+
{"CSE_D3_STS", BIT(4), 0},
326
+
{"KVMCC_D3_STS", BIT(5), 0},
327
+
{"USBR0_D3_STS", BIT(6), 0},
328
+
{"ISH_D3_STS", BIT(7), 0},
329
+
{"SMT1_D3_STS", BIT(8), 0},
330
+
{"SMT2_D3_STS", BIT(9), 0},
331
+
{"SMT3_D3_STS", BIT(10), 0},
332
+
{"OSSE_SMT2_D3_STS", BIT(12), 0},
333
+
{"CLINK_D3_STS", BIT(14), 0},
334
+
{"PTIO_D3_STS", BIT(16), 0},
335
+
{"PMT_D3_STS", BIT(17), 0},
336
+
{"SMS1_D3_STS", BIT(18), 0},
337
+
{"SMS2_D3_STS", BIT(19), 0},
338
+
{}
339
+
};
340
+
341
+
static const struct pmc_bit_map ptl_pcdp_d3_status_3_map[] = {
342
+
{"THC0_D3_STS", BIT(14), 1},
343
+
{"THC1_D3_STS", BIT(15), 1},
344
+
{"OSSE_SMT3_D3_STS", BIT(18), 0},
345
+
{"ACE_D3_STS", BIT(23), 0},
346
+
{}
347
+
};
348
+
349
+
static const struct pmc_bit_map ptl_pcdp_vnn_req_status_0_map[] = {
350
+
{"LPSS_VNN_REQ_STS", BIT(3), 1},
351
+
{"OSSE_VNN_REQ_STS", BIT(6), 1},
352
+
{"ESPISPI_VNN_REQ_STS", BIT(18), 1},
353
+
{"OSSE_SMT1_VNN_REQ_STS", BIT(30), 1},
354
+
{}
355
+
};
356
+
357
+
static const struct pmc_bit_map ptl_pcdp_vnn_req_status_1_map[] = {
358
+
{"NPK_VNN_REQ_STS", BIT(4), 1},
359
+
{"DFXAGG_VNN_REQ_STS", BIT(8), 0},
360
+
{"EXI_VNN_REQ_STS", BIT(9), 1},
361
+
{"P2D_VNN_REQ_STS", BIT(18), 1},
362
+
{"GBE_VNN_REQ_STS", BIT(19), 1},
363
+
{"SMB_VNN_REQ_STS", BIT(25), 1},
364
+
{"LPC_VNN_REQ_STS", BIT(26), 0},
365
+
{"ESE_VNN_REQ_STS", BIT(30), 1},
366
+
{}
367
+
};
368
+
369
+
static const struct pmc_bit_map ptl_pcdp_vnn_req_status_2_map[] = {
370
+
{"CSMERTC_VNN_REQ_STS", BIT(1), 1},
371
+
{"CSE_VNN_REQ_STS", BIT(4), 1},
372
+
{"ISH_VNN_REQ_STS", BIT(7), 1},
373
+
{"SMT1_VNN_REQ_STS", BIT(8), 1},
374
+
{"CLINK_VNN_REQ_STS", BIT(14), 1},
375
+
{"SMS1_VNN_REQ_STS", BIT(18), 1},
376
+
{"SMS2_VNN_REQ_STS", BIT(19), 1},
377
+
{"GPIOCOM4_VNN_REQ_STS", BIT(20), 1},
378
+
{"GPIOCOM3_VNN_REQ_STS", BIT(21), 1},
379
+
{"GPIOCOM1_VNN_REQ_STS", BIT(23), 1},
380
+
{"GPIOCOM0_VNN_REQ_STS", BIT(24), 1},
381
+
{"DISP_SHIM_VNN_REQ_STS", BIT(26), 1},
382
+
{}
383
+
};
384
+
385
+
static const struct pmc_bit_map ptl_pcdp_vnn_req_status_3_map[] = {
386
+
{"DTS0_VNN_REQ_STS", BIT(7), 0},
387
+
{"GPIOCOM5_VNN_REQ_STS", BIT(11), 1},
388
+
{}
389
+
};
390
+
391
+
static const struct pmc_bit_map ptl_pcdp_vnn_misc_status_map[] = {
392
+
{"CPU_C10_REQ_STS", BIT(0), 0},
393
+
{"TS_OFF_REQ_STS", BIT(1), 0},
394
+
{"PNDE_MET_REQ_STS", BIT(2), 1},
395
+
{"PG5_PMA0_REQ_STS", BIT(3), 0},
396
+
{"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0},
397
+
{"VNN_SOC_REQ_STS", BIT(6), 1},
398
+
{"ISH_VNNAON_REQ_STS", BIT(7), 0},
399
+
{"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1},
400
+
{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1},
401
+
{"D2D_IPU_QACTIVE_REQ_STS", BIT(10), 1},
402
+
{"PLT_GREATER_REQ_STS", BIT(11), 1},
403
+
{"ALL_SBR_IDLE_REQ_STS", BIT(12), 0},
404
+
{"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0},
405
+
{"PM_SYNC_STATES_REQ_STS", BIT(14), 0},
406
+
{"EA_REQ_STS", BIT(15), 0},
407
+
{"MPHY_CORE_OFF_REQ_STS", BIT(16), 0},
408
+
{"BRK_EV_EN_REQ_STS", BIT(17), 0},
409
+
{"AUTO_DEMO_EN_REQ_STS", BIT(18), 0},
410
+
{"ITSS_CLK_SRC_REQ_STS", BIT(19), 1},
411
+
{"ARC_IDLE_REQ_STS", BIT(21), 0},
412
+
{"PG5_PMA1_REQ_STS", BIT(22), 0},
413
+
{"FIA_DEEP_PM_REQ_STS", BIT(23), 0},
414
+
{"XDCI_ATTACHED_REQ_STS", BIT(24), 1},
415
+
{"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0},
416
+
{"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1},
417
+
{"PRE_WAKE0_REQ_STS", BIT(27), 1},
418
+
{"PRE_WAKE1_REQ_STS", BIT(28), 1},
419
+
{"PRE_WAKE2_REQ_STS", BIT(29), 1},
420
+
{"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31), 1},
421
+
{}
422
+
};
423
+
424
+
static const struct pmc_bit_map ptl_pcdp_signal_status_map[] = {
425
+
{"LSX_Wake0_STS", BIT(0), 0},
426
+
{"LSX_Wake1_STS", BIT(1), 0},
427
+
{"LSX_Wake2_STS", BIT(2), 0},
428
+
{"LSX_Wake3_STS", BIT(3), 0},
429
+
{"LSX_Wake4_STS", BIT(4), 0},
430
+
{"LSX_Wake5_STS", BIT(5), 0},
431
+
{"LSX_Wake6_STS", BIT(6), 0},
432
+
{"LSX_Wake7_STS", BIT(7), 0},
433
+
{"LPSS_Wake0_STS", BIT(8), 1},
434
+
{"LPSS_Wake1_STS", BIT(9), 1},
435
+
{"Int_Timer_SS_Wake0_STS", BIT(10), 1},
436
+
{"Int_Timer_SS_Wake1_STS", BIT(11), 1},
437
+
{"Int_Timer_SS_Wake2_STS", BIT(12), 1},
438
+
{"Int_Timer_SS_Wake3_STS", BIT(13), 1},
439
+
{"Int_Timer_SS_Wake4_STS", BIT(14), 1},
440
+
{"Int_Timer_SS_Wake5_STS", BIT(15), 1},
441
+
{}
442
+
};
443
+
444
+
static const struct pmc_bit_map ptl_pcdp_rsc_status_map[] = {
445
+
{"Memory", 0, 1},
446
+
{"PSF0", 0, 1},
447
+
{"PSF4", 0, 1},
448
+
{"PSF5", 0, 1},
449
+
{"PSF6", 0, 1},
450
+
{"PSF8", 0, 1},
451
+
{"SAF_CFI_LINK", 0, 1},
452
+
{"SB", 0, 1},
453
+
{}
454
+
};
455
+
456
+
static const struct pmc_bit_map *ptl_pcdp_lpm_maps[] = {
457
+
ptl_pcdp_clocksource_status_map,
458
+
ptl_pcdp_power_gating_status_0_map,
459
+
ptl_pcdp_power_gating_status_1_map,
460
+
ptl_pcdp_power_gating_status_2_map,
461
+
ptl_pcdp_d3_status_0_map,
462
+
ptl_pcdp_d3_status_1_map,
463
+
ptl_pcdp_d3_status_2_map,
464
+
ptl_pcdp_d3_status_3_map,
465
+
ptl_pcdp_vnn_req_status_0_map,
466
+
ptl_pcdp_vnn_req_status_1_map,
467
+
ptl_pcdp_vnn_req_status_2_map,
468
+
ptl_pcdp_vnn_req_status_3_map,
469
+
ptl_pcdp_vnn_misc_status_map,
470
+
ptl_pcdp_signal_status_map,
471
+
NULL
472
+
};
473
+
474
+
static const struct pmc_bit_map *ptl_pcdp_blk_maps[] = {
475
+
ptl_pcdp_power_gating_status_0_map,
476
+
ptl_pcdp_power_gating_status_1_map,
477
+
ptl_pcdp_power_gating_status_2_map,
478
+
ptl_pcdp_rsc_status_map,
479
+
ptl_pcdp_vnn_req_status_0_map,
480
+
ptl_pcdp_vnn_req_status_1_map,
481
+
ptl_pcdp_vnn_req_status_2_map,
482
+
ptl_pcdp_vnn_req_status_3_map,
483
+
ptl_pcdp_d3_status_0_map,
484
+
ptl_pcdp_d3_status_1_map,
485
+
ptl_pcdp_d3_status_2_map,
486
+
ptl_pcdp_d3_status_3_map,
487
+
ptl_pcdp_clocksource_status_map,
488
+
ptl_pcdp_vnn_misc_status_map,
489
+
ptl_pcdp_signal_status_map,
490
+
NULL
491
+
};
492
+
493
+
static const struct pmc_reg_map ptl_pcdp_reg_map = {
494
+
.pfear_sts = ext_ptl_pcdp_pfear_map,
495
+
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
496
+
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
497
+
.ltr_show_sts = ptl_pcdp_ltr_show_map,
498
+
.msr_sts = msr_map,
499
+
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
500
+
.regmap_length = PTL_PCD_PMC_MMIO_REG_LEN,
501
+
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
502
+
.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
503
+
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
504
+
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
505
+
.lpm_num_maps = PTL_LPM_NUM_MAPS,
506
+
.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
507
+
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
508
+
.etr3_offset = ETR3_OFFSET,
509
+
.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
510
+
.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
511
+
.lpm_en_offset = MTL_LPM_EN_OFFSET,
512
+
.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
513
+
.lpm_sts = ptl_pcdp_lpm_maps,
514
+
.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
515
+
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
516
+
.s0ix_blocker_maps = ptl_pcdp_blk_maps,
517
+
.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
518
+
};
519
+
520
+
#define PTL_NPU_PCI_DEV 0xb03e
521
+
#define PTL_IPU_PCI_DEV 0xb05d
522
+
523
+
/*
524
+
* Set power state of select devices that do not have drivers to D3
525
+
* so that they do not block Package C entry.
526
+
*/
527
+
static void ptl_d3_fixup(void)
528
+
{
529
+
pmc_core_set_device_d3(PTL_IPU_PCI_DEV);
530
+
pmc_core_set_device_d3(PTL_NPU_PCI_DEV);
531
+
}
532
+
533
+
static int ptl_resume(struct pmc_dev *pmcdev)
534
+
{
535
+
ptl_d3_fixup();
536
+
return cnl_resume(pmcdev);
537
+
}
538
+
539
+
static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
540
+
{
541
+
ptl_d3_fixup();
542
+
return generic_core_init(pmcdev, pmc_dev_info);
543
+
}
544
+
545
+
struct pmc_dev_info ptl_pmc_dev = {
546
+
.map = &ptl_pcdp_reg_map,
547
+
.suspend = cnl_suspend,
548
+
.resume = ptl_resume,
549
+
.init = ptl_core_init,
550
+
};