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drm/amd/ras: Support physical address convert

Support physical address convert to current NPS
pages in uniras.

Signed-off-by: Jinzhou Su <jinzhou.su@amd.com>
Reviewed-by: YiPeng Chai <YiPeng.Chai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jinzhou Su and committed by
Alex Deucher
d3336c93 364f168f

+68 -11
+15
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
··· 671 671 amdgpu_ras_process_post_reset(adev); 672 672 return 0; 673 673 } 674 + 675 + int amdgpu_ras_mgr_lookup_bad_pages_in_a_row(struct amdgpu_device *adev, 676 + uint64_t addr, uint64_t *nps_page_addr, uint32_t max_page_count) 677 + { 678 + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 679 + 680 + if (!amdgpu_ras_mgr_is_ready(adev)) 681 + return -EPERM; 682 + 683 + if (!nps_page_addr || !max_page_count) 684 + return -EINVAL; 685 + 686 + return ras_core_convert_soc_pa_to_cur_nps_pages(ras_mgr->ras_core, 687 + addr, nps_page_addr, max_page_count); 688 + }
+2
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h
··· 81 81 void *output, uint32_t out_size); 82 82 int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev); 83 83 int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev); 84 + int amdgpu_ras_mgr_lookup_bad_pages_in_a_row(struct amdgpu_device *adev, 85 + uint64_t addr, uint64_t *nps_page_addr, uint32_t max_page_count); 84 86 #endif
+2
drivers/gpu/drm/amd/ras/rascore/ras.h
··· 367 367 enum ras_notify_event event_id, void *data); 368 368 int ras_core_get_device_system_info(struct ras_core_context *ras_core, 369 369 struct device_system_info *dev_info); 370 + int ras_core_convert_soc_pa_to_cur_nps_pages(struct ras_core_context *ras_core, 371 + uint64_t soc_pa, uint64_t *page_pfn, uint32_t max_pages); 370 372 #endif
+23
drivers/gpu/drm/amd/ras/rascore/ras_core.c
··· 601 601 602 602 return -RAS_CORE_NOT_SUPPORTED; 603 603 } 604 + 605 + int ras_core_convert_soc_pa_to_cur_nps_pages(struct ras_core_context *ras_core, 606 + uint64_t soc_pa, uint64_t *page_pfn, uint32_t max_pages) 607 + { 608 + struct eeprom_umc_record record; 609 + uint32_t cur_nps_mode; 610 + int count = 0; 611 + 612 + if (!ras_core || !page_pfn || !max_pages) 613 + return -EINVAL; 614 + 615 + cur_nps_mode = ras_core_get_curr_nps_mode(ras_core); 616 + if (!cur_nps_mode || cur_nps_mode > AMDGPU_NPS8_PARTITION_MODE) 617 + return -EINVAL; 618 + 619 + memset(&record, 0, sizeof(record)); 620 + record.cur_nps_retired_row_pfn = RAS_ADDR_TO_PFN(soc_pa); 621 + 622 + count = ras_umc_convert_record_to_nps_pages(ras_core, 623 + &record, cur_nps_mode, page_pfn, max_pages); 624 + 625 + return count; 626 + }
+23 -11
drivers/gpu/drm/amd/ras/rascore/ras_umc.c
··· 154 154 return 0; 155 155 } 156 156 157 + int ras_umc_convert_record_to_nps_pages(struct ras_core_context *ras_core, 158 + struct eeprom_umc_record *record, uint32_t nps, 159 + uint64_t *page_pfn, uint32_t max_pages) 160 + { 161 + int count = 0; 162 + struct ras_umc *ras_umc = &ras_core->ras_umc; 163 + 164 + if (!page_pfn || !max_pages) 165 + return -EINVAL; 166 + 167 + if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_pages) 168 + count = ras_umc->ip_func->eeprom_record_to_nps_pages(ras_core, 169 + record, nps, page_pfn, max_pages); 170 + 171 + return count; 172 + } 173 + 157 174 static void ras_umc_reserve_eeprom_record(struct ras_core_context *ras_core, 158 175 struct eeprom_umc_record *record) 159 176 { 160 - struct ras_umc *ras_umc = &ras_core->ras_umc; 161 177 uint64_t page_pfn[16]; 162 178 int count = 0, i; 163 179 164 180 memset(page_pfn, 0, sizeof(page_pfn)); 165 - if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_pages) { 166 - count = ras_umc->ip_func->eeprom_record_to_nps_pages(ras_core, 181 + count = ras_umc_convert_record_to_nps_pages(ras_core, 167 182 record, record->cur_nps, page_pfn, ARRAY_SIZE(page_pfn)); 168 - if (count <= 0) { 169 - RAS_DEV_ERR(ras_core->dev, 170 - "Fail to convert error address! count:%d\n", count); 171 - return; 172 - } 183 + if (count <= 0) { 184 + RAS_DEV_ERR(ras_core->dev, 185 + "Fail to convert error address! count:%d\n", count); 186 + return; 173 187 } 174 188 175 189 /* Reserve memory */ ··· 381 367 } 382 368 383 369 memset(page_pfn, 0, sizeof(page_pfn)); 384 - if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_pages) 385 - count = ras_umc->ip_func->eeprom_record_to_nps_pages(ras_core, 370 + count = ras_umc_convert_record_to_nps_pages(ras_core, 386 371 bps, bps->cur_nps, page_pfn, ARRAY_SIZE(page_pfn)); 387 - 388 372 if (count > 0) { 389 373 for (j = 0; j < count; j++) { 390 374 bps->cur_nps_retired_row_pfn = page_pfn[j];
+3
drivers/gpu/drm/amd/ras/rascore/ras_umc.h
··· 163 163 bool ras_umc_check_retired_addr(struct ras_core_context *ras_core, uint64_t addr); 164 164 int ras_umc_translate_soc_pa_and_bank(struct ras_core_context *ras_core, 165 165 uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa); 166 + int ras_umc_convert_record_to_nps_pages(struct ras_core_context *ras_core, 167 + struct eeprom_umc_record *record, uint32_t nps, 168 + uint64_t *page_pfn, uint32_t max_pages); 166 169 #endif