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reset: th1520: add resets for display pipeline

The VO subsystem of TH1520 contains a few resets for the display
pipeline -- display, MIPI DSI and HDMI controllers.

Add support for them to the reset-th1520 driver.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20250813081716.2181843-3-uwu@icenowy.me
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

authored by

Icenowy Zheng and committed by
Philipp Zabel
d342031a f443d7c9

+39 -1
+39 -1
drivers/reset/reset-th1520.c
··· 14 14 /* register offset in VOSYS_REGMAP */ 15 15 #define TH1520_GPU_RST_CFG 0x0 16 16 #define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) 17 + #define TH1520_DPU_RST_CFG 0x4 18 + #define TH1520_DSI0_RST_CFG 0x8 19 + #define TH1520_DSI1_RST_CFG 0xc 20 + #define TH1520_HDMI_RST_CFG 0x14 17 21 18 22 /* register values */ 19 23 #define TH1520_GPU_SW_GPU_RST BIT(0) 20 24 #define TH1520_GPU_SW_CLKGEN_RST BIT(1) 25 + #define TH1520_DPU_SW_DPU_HRST BIT(0) 26 + #define TH1520_DPU_SW_DPU_ARST BIT(1) 27 + #define TH1520_DPU_SW_DPU_CRST BIT(2) 28 + #define TH1520_DSI_SW_DSI_PRST BIT(0) 29 + #define TH1520_HDMI_SW_MAIN_RST BIT(0) 30 + #define TH1520_HDMI_SW_PRST BIT(1) 21 31 22 32 struct th1520_reset_priv { 23 33 struct reset_controller_dev rcdev; ··· 47 37 [TH1520_RESET_ID_GPU_CLKGEN] = { 48 38 .bit = TH1520_GPU_SW_CLKGEN_RST, 49 39 .reg = TH1520_GPU_RST_CFG, 50 - } 40 + }, 41 + [TH1520_RESET_ID_DPU_AHB] = { 42 + .bit = TH1520_DPU_SW_DPU_HRST, 43 + .reg = TH1520_DPU_RST_CFG, 44 + }, 45 + [TH1520_RESET_ID_DPU_AXI] = { 46 + .bit = TH1520_DPU_SW_DPU_ARST, 47 + .reg = TH1520_DPU_RST_CFG, 48 + }, 49 + [TH1520_RESET_ID_DPU_CORE] = { 50 + .bit = TH1520_DPU_SW_DPU_CRST, 51 + .reg = TH1520_DPU_RST_CFG, 52 + }, 53 + [TH1520_RESET_ID_DSI0_APB] = { 54 + .bit = TH1520_DSI_SW_DSI_PRST, 55 + .reg = TH1520_DSI0_RST_CFG, 56 + }, 57 + [TH1520_RESET_ID_DSI1_APB] = { 58 + .bit = TH1520_DSI_SW_DSI_PRST, 59 + .reg = TH1520_DSI1_RST_CFG, 60 + }, 61 + [TH1520_RESET_ID_HDMI] = { 62 + .bit = TH1520_HDMI_SW_MAIN_RST, 63 + .reg = TH1520_HDMI_RST_CFG, 64 + }, 65 + [TH1520_RESET_ID_HDMI_APB] = { 66 + .bit = TH1520_HDMI_SW_PRST, 67 + .reg = TH1520_HDMI_RST_CFG, 68 + }, 51 69 }; 52 70 53 71 static inline struct th1520_reset_priv *