+8 -1

arch/mips/include/asm/mipsregs.h

reviewed

··· 135 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 136 136 137 137 /* 138 138 + * Bits 18 - 20 of the FPU Status Register will be read as 0, 139 139 + * and should be written as zero. 140 140 + */ 141 141 + #define FPU_CSR_RSVD 0x001c0000 142 142 + 143 143 + /* 138 144 * X the exception cause indicator 139 145 * E the exception enable 140 146 * S the sticky/flag bit ··· 167 161 #define FPU_CSR_UDF_S 0x00000008 168 162 #define FPU_CSR_INE_S 0x00000004 169 163 170 170 - /* rounding mode */ 164 164 + /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 165 165 + #define FPU_CSR_RM 0x00000003 171 166 #define FPU_CSR_RN 0x0 /* nearest */ 172 167 #define FPU_CSR_RZ 0x1 /* towards zero */ 173 168 #define FPU_CSR_RU 0x2 /* towards +Infinity */

+1 -1

arch/mips/kernel/scall64-n32.S

reviewed

··· 385 385 PTR sys_fchmodat 386 386 PTR sys_faccessat 387 387 PTR compat_sys_pselect6 388 388 - PTR sys_ppoll /* 6265 */ 388 388 + PTR compat_sys_ppoll /* 6265 */ 389 389 PTR sys_unshare 390 390 PTR sys_splice 391 391 PTR sys_sync_file_range

+11 -4

arch/mips/math-emu/cp1emu.c

reviewed

··· 78 78 #define FPCREG_RID 0 /* $0 = revision id */ 79 79 #define FPCREG_CSR 31 /* $31 = csr */ 80 80 81 81 + /* Determine rounding mode from the RM bits of the FCSR */ 82 82 + #define modeindex(v) ((v) & FPU_CSR_RM) 83 83 + 81 84 /* Convert Mips rounding mode (0..3) to IEEE library modes. */ 82 85 static const unsigned char ieee_rm[4] = { 83 86 [FPU_CSR_RN] = IEEE754_RN, ··· 387 384 (void *) (xcp->cp0_epc), 388 385 MIPSInst_RT(ir), value); 389 386 #endif 390 390 - value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); 391 391 - ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); 392 392 - /* convert to ieee library modes */ 393 393 - ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3]; 387 387 + 388 388 + /* 389 389 + * Don't write reserved bits, 390 390 + * and convert to ieee library modes 391 391 + */ 392 392 + ctx->fcr31 = (value & 393 393 + ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 394 394 + ieee_rm[modeindex(value)]; 394 395 } 395 396 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 396 397 return SIGFPE;

+1 -1

arch/mips/oprofile/op_model_loongson2.c

reviewed

··· 122 122 */ 123 123 124 124 /* Check whether the irq belongs to me */ 125 125 - enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; 125 125 + enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN; 126 126 if (!enabled) 127 127 return IRQ_NONE; 128 128 enabled = reg.cnt1_enabled | reg.cnt2_enabled;