powerpc/perf: Fix to update radix_scope_qual in power10

power10 uses bit 9 of the raw event code as RADIX_SCOPE_QUAL.
This bit is used for enabling the radix process events.
Patch fixes the PMU counter support functions to program bit
18 of MMCR1 ( Monitor Mode Control Register1 ) with the
RADIX_SCOPE_QUAL bit value. Since this field is not per-pmc,
add this to PMU group constraints to make sure events in a
group will have same bit value for this field. Use bit 21 as
constraint bit field for radix_scope_qual. Patch also updates
the power10 raw event encoding layout information, format field
and constraints bit layout to include the radix_scope_qual bit.

Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-2-git-send-email-atrajeev@linux.vnet.ibm.com

authored by

Athira Rajeev and committed by

Michael Ellerman 5 years ago d3afd28c ec0f9b98

+29 -7

3 changed files

expand all

arch

powerpc

perf

isa207-common.c

isa207-common.h

power10-pmu.c

+12

arch/powerpc/perf/isa207-common.c

··· 339 339 value |= CNST_L1_QUAL_VAL(cache); 340 340 } 341 341 342 + if (cpu_has_feature(CPU_FTR_ARCH_31)) { 343 + mask |= CNST_RADIX_SCOPE_GROUP_MASK; 344 + value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT); 345 + } 346 + 342 347 if (is_event_marked(event)) { 343 348 mask |= CNST_SAMPLE_MASK; 344 349 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); ··· 459 454 cache = dc_ic_rld_quad_l1_sel(event[i]); 460 455 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 461 456 } 457 + } 458 + 459 + /* Set RADIX_SCOPE_QUAL bit */ 460 + if (cpu_has_feature(CPU_FTR_ARCH_31)) { 461 + val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) & 462 + p10_EVENT_RADIX_SCOPE_QUAL_MASK; 463 + mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT; 462 464 } 463 465 464 466 if (is_event_marked(event[i])) {

+10 -3

arch/powerpc/perf/isa207-common.h

··· 101 101 #define p10_EVENT_CACHE_SEL_MASK 0x3ull 102 102 #define p10_EVENT_MMCR3_MASK 0x7fffull 103 103 #define p10_EVENT_MMCR3_SHIFT 45 104 + #define p10_EVENT_RADIX_SCOPE_QUAL_SHIFT 9 105 + #define p10_EVENT_RADIX_SCOPE_QUAL_MASK 0x1 106 + #define p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT 45 104 107 105 108 #define p10_EVENT_VALID_MASK \ 106 109 ((p10_SDAR_MODE_MASK << p10_SDAR_MODE_SHIFT | \ ··· 115 112 (p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT) | \ 116 113 (p10_EVENT_MMCR3_MASK << p10_EVENT_MMCR3_SHIFT) | \ 117 114 (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \ 115 + (p10_EVENT_RADIX_SCOPE_QUAL_MASK << p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) | \ 118 116 EVENT_LINUX_MASK | \ 119 117 EVENT_PSEL_MASK)) 120 118 /* ··· 129 125 * 130 126 * 28 24 20 16 12 8 4 0 131 127 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 132 - * [ ] | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1] 133 - * | | | | 134 - * BHRB IFM -* | | | Count of events for each PMC. 128 + * [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1] 129 + * | | | | | 130 + * BHRB IFM -* | | |*radix_scope | Count of events for each PMC. 135 131 * EBB -* | | p1, p2, p3, p4, p5, p6. 136 132 * L1 I/D qualifier -* | 137 133 * nc - number of counters -* ··· 168 164 169 165 #define CNST_L2L3_GROUP_VAL(v) (((v) & 0x1full) << 55) 170 166 #define CNST_L2L3_GROUP_MASK CNST_L2L3_GROUP_VAL(0x1f) 167 + 168 + #define CNST_RADIX_SCOPE_GROUP_VAL(v) (((v) & 0x1ull) << 21) 169 + #define CNST_RADIX_SCOPE_GROUP_MASK CNST_RADIX_SCOPE_GROUP_VAL(1) 171 170 172 171 /* 173 172 * For NC we are counting up to 4 events. This requires three bits, and we need

+7 -4

arch/powerpc/perf/power10-pmu.c

··· 23 23 * 24 24 * 28 24 20 16 12 8 4 0 25 25 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 26 - * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] m [ pmcxsel ] 27 - * | | | | | | 28 - * | | | | | *- mark 29 - * | | | *- L1/L2/L3 cache_sel | 26 + * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] | m [ pmcxsel ] 27 + * | | | | | | | 28 + * | | | | | | *- mark 29 + * | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual 30 30 * | | sdar_mode | 31 31 * | *- sampling mode for marked events *- combine 32 32 * | ··· 59 59 * 60 60 * MMCR1[16] = cache_sel[0] 61 61 * MMCR1[17] = cache_sel[1] 62 + * MMCR1[18] = radix_scope_qual 62 63 * 63 64 * if mark: 64 65 * MMCRA[63] = 1 (SAMPLE_ENABLE) ··· 176 175 PMU_FORMAT_ATTR(invert_bit, "config:47"); 177 176 PMU_FORMAT_ATTR(src_mask, "config:48-53"); 178 177 PMU_FORMAT_ATTR(src_match, "config:54-59"); 178 + PMU_FORMAT_ATTR(radix_scope, "config:9"); 179 179 180 180 static struct attribute *power10_pmu_format_attr[] = { 181 181 &format_attr_event.attr, ··· 196 194 &format_attr_invert_bit.attr, 197 195 &format_attr_src_mask.attr, 198 196 &format_attr_src_match.attr, 197 + &format_attr_radix_scope.attr, 199 198 NULL, 200 199 }; 201 200

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