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PM / devfreq: rockchip-dfi: Clean up DDR type register defines

Use the HIWORD_UPDATE() define known from other rockchip drivers to
make the defines look less odd to the readers who've seen other
rockchip drivers.

The HIWORD registers have their functional bits in the lower 16 bits
whereas the upper 16 bits contain a mask. Only the functional bits that
have the corresponding mask bit set are modified during a write. Although
the register writes look different, the end result should be the same,
at least there's no functional change intended with this patch.

Link: https://lore.kernel.org/all/20231018061714.3553817-10-s.hauer@pengutronix.de/
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>

authored by

Sascha Hauer and committed by
Chanwoo Choi d3b0f6ab 74002e66

+21 -12
+21 -12
drivers/devfreq/event/rockchip-dfi.c
··· 26 26 27 27 #define DMC_MAX_CHANNELS 2 28 28 29 + #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) 30 + 29 31 /* DDRMON_CTRL */ 30 32 #define DDRMON_CTRL 0x04 31 - #define CLR_DDRMON_CTRL (0x1f0000 << 0) 32 - #define LPDDR4_EN (0x10001 << 4) 33 - #define HARDWARE_EN (0x10001 << 3) 34 - #define LPDDR3_EN (0x10001 << 2) 35 - #define SOFTWARE_EN (0x10001 << 1) 36 - #define SOFTWARE_DIS (0x10000 << 1) 37 - #define TIME_CNT_EN (0x10001 << 0) 33 + #define DDRMON_CTRL_DDR4 BIT(5) 34 + #define DDRMON_CTRL_LPDDR4 BIT(4) 35 + #define DDRMON_CTRL_HARDWARE_EN BIT(3) 36 + #define DDRMON_CTRL_LPDDR23 BIT(2) 37 + #define DDRMON_CTRL_SOFTWARE_EN BIT(1) 38 + #define DDRMON_CTRL_TIMER_CNT_EN BIT(0) 39 + #define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \ 40 + DDRMON_CTRL_LPDDR4 | \ 41 + DDRMON_CTRL_LPDDR23) 38 42 39 43 #define DDRMON_CH0_COUNT_NUM 0x28 40 44 #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c ··· 78 74 void __iomem *dfi_regs = dfi->regs; 79 75 80 76 /* clear DDRMON_CTRL setting */ 81 - writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); 77 + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN | 78 + DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL); 82 79 83 80 /* set ddr type to dfi */ 84 81 if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) 85 - writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); 82 + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), 83 + dfi_regs + DDRMON_CTRL); 86 84 else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) 87 - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); 85 + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), 86 + dfi_regs + DDRMON_CTRL); 88 87 89 88 /* enable count, use software mode */ 90 - writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); 89 + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), 90 + dfi_regs + DDRMON_CTRL); 91 91 } 92 92 93 93 static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) ··· 99 91 struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); 100 92 void __iomem *dfi_regs = dfi->regs; 101 93 102 - writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL); 94 + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), 95 + dfi_regs + DDRMON_CTRL); 103 96 } 104 97 105 98 static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)