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dt-bindings: tpm: Convert Google Cr50 bindings to DT schema

Convert the devicetree bindings for the Google Security Chip H1 running
Cr50 firmware to DT schema.

The chip can be attached to SPI or I²C. Existing devicetrees use the
same "google,cr50" compatible string for both cases without additionally
specifying a generic "tcg,tpm_tis-spi" or "tcg,tpm-tis-i2c" compatible.

The chip therefore cannot be documented in the tcg,tpm_tis-spi.yaml and
tcg,tpm-tis-i2c.yaml schemas: The validator would select both of them
and complain about SPI properties when the chip is an I²C peripheral.

So document the chip in a schema of its own which includes both, SPI and
I²C properties by reference.

Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/52635205818ab201cacb0c0f37c7fa48149c7f8e.1702806810.git.lukas@wunner.de
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Lukas Wunner and committed by
Rob Herring d3b8b085 26c9d152

+65 -19
-19
Documentation/devicetree/bindings/security/tpm/google,cr50.txt
··· 1 - * H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. 2 - 3 - H1 Secure Microcontroller running Cr50 firmware provides several 4 - functions, including TPM-like functionality. It communicates over 5 - SPI using the FIFO protocol described in the PTP Spec, section 6. 6 - 7 - Required properties: 8 - - compatible: Should be "google,cr50". 9 - - spi-max-frequency: Maximum SPI frequency. 10 - 11 - Example: 12 - 13 - &spi0 { 14 - tpm@0 { 15 - compatible = "google,cr50"; 16 - reg = <0>; 17 - spi-max-frequency = <800000>; 18 - }; 19 - };
+65
Documentation/devicetree/bindings/tpm/google,cr50.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/tpm/google,cr50.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Google Security Chip H1 (running Cr50 firmware) 8 + 9 + maintainers: 10 + - Andrey Pronin <apronin@chromium.org> 11 + 12 + description: | 13 + Google has designed a family of security chips called "Titan". 14 + One member is the H1 built into Chromebooks and running Cr50 firmware: 15 + https://www.osfc.io/2018/talks/google-secure-microcontroller-and-ccd-closed-case-debugging/ 16 + 17 + The chip provides several functions, including TPM 2.0 like functionality. 18 + It communicates over SPI or I²C using the FIFO protocol described in the 19 + TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP), sec 6: 20 + https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/ 21 + 22 + properties: 23 + compatible: 24 + const: google,cr50 25 + 26 + allOf: 27 + - $ref: tpm-common.yaml# 28 + 29 + anyOf: 30 + - $ref: /schemas/spi/spi-peripheral-props.yaml# 31 + - $ref: tcg,tpm-tis-i2c.yaml#/properties/reg 32 + 33 + required: 34 + - compatible 35 + - reg 36 + 37 + unevaluatedProperties: false 38 + 39 + examples: 40 + - | 41 + spi { 42 + #address-cells = <1>; 43 + #size-cells = <0>; 44 + 45 + tpm@0 { 46 + reg = <0>; 47 + compatible = "google,cr50"; 48 + spi-max-frequency = <800000>; 49 + }; 50 + }; 51 + 52 + - | 53 + #include <dt-bindings/interrupt-controller/irq.h> 54 + i2c { 55 + #address-cells = <1>; 56 + #size-cells = <0>; 57 + 58 + tpm@50 { 59 + compatible = "google,cr50"; 60 + reg = <0x50>; 61 + interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 62 + pinctrl-names = "default"; 63 + pinctrl-0 = <&cr50_int>; 64 + }; 65 + };