Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull more drm fixes from Dave Airlie:
"Just some intel and nouveau ones this time, intel has more edp panel
fixes for macbooks and nouveau has a suspend/resume regression fix in
there."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/i915: Apply post-sync write for pipe control invalidates
drm/i915: reorder edp disabling to fix ivb MacBook Air
drm/nv86/fifo: suspend fix
drm/nouveau: disable copy engine on NVAF
nouveau: fixup scanout enable in nvc0_pm
drm/nouveau/aux: mask off higher bits of auxch index in i2c table entry
drm/nvd0/disp: mask off high 16 bit of negative cursor x-coordinate
drm/i915: ensure i2c adapter is all set before adding it
drm/i915: ignore eDP bpc settings from vbt
drm/i915: Fix blank panel at reopening lid
drm/nve0/fifo: add support for the flip completion swmthd
+88
-51
-11
drivers/gpu/drm/i915/intel_display.c
-11
drivers/gpu/drm/i915/intel_display.c
···
3754
3754
continue;
3755
3755
}
3756
3756
3757
-
if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3758
-
/* Use VBT settings if we have an eDP panel */
3759
-
unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3760
-
3761
-
if (edp_bpc < display_bpc) {
3762
-
DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3763
-
display_bpc = edp_bpc;
3764
-
}
3765
-
continue;
3766
-
}
3767
-
3768
3757
/* Not one of the known troublemakers, check the EDID */
3769
3758
list_for_each_entry(connector, &dev->mode_config.connector_list,
3770
3759
head) {
+7
-7
drivers/gpu/drm/i915/intel_dp.c
+7
-7
drivers/gpu/drm/i915/intel_dp.c
···
1174
1174
WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1175
1175
1176
1176
pp = ironlake_get_pp_control(dev_priv);
1177
-
pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1177
+
/* We need to switch off panel power _and_ force vdd, for otherwise some
1178
+
* panels get very unhappy and cease to work. */
1179
+
pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1178
1180
I915_WRITE(PCH_PP_CONTROL, pp);
1179
1181
POSTING_READ(PCH_PP_CONTROL);
1182
+
1183
+
intel_dp->want_panel_vdd = false;
1180
1184
1181
1185
ironlake_wait_panel_off(intel_dp);
1182
1186
}
···
1291
1287
* ensure that we have vdd while we switch off the panel. */
1292
1288
ironlake_edp_panel_vdd_on(intel_dp);
1293
1289
ironlake_edp_backlight_off(intel_dp);
1294
-
ironlake_edp_panel_off(intel_dp);
1295
-
1296
1290
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1291
+
ironlake_edp_panel_off(intel_dp);
1297
1292
intel_dp_link_down(intel_dp);
1298
-
ironlake_edp_panel_vdd_off(intel_dp, false);
1299
1293
}
1300
1294
1301
1295
static void intel_dp_commit(struct drm_encoder *encoder)
···
1328
1326
/* Switching the panel off requires vdd. */
1329
1327
ironlake_edp_panel_vdd_on(intel_dp);
1330
1328
ironlake_edp_backlight_off(intel_dp);
1331
-
ironlake_edp_panel_off(intel_dp);
1332
-
1333
1329
intel_dp_sink_dpms(intel_dp, mode);
1330
+
ironlake_edp_panel_off(intel_dp);
1334
1331
intel_dp_link_down(intel_dp);
1335
-
ironlake_edp_panel_vdd_off(intel_dp, false);
1336
1332
1337
1333
if (is_cpu_edp(intel_dp))
1338
1334
ironlake_edp_pll_off(encoder);
+4
-3
drivers/gpu/drm/i915/intel_i2c.c
+4
-3
drivers/gpu/drm/i915/intel_i2c.c
···
486
486
bus->dev_priv = dev_priv;
487
487
488
488
bus->adapter.algo = &gmbus_algorithm;
489
-
ret = i2c_add_adapter(&bus->adapter);
490
-
if (ret)
491
-
goto err;
492
489
493
490
/* By default use a conservative clock rate */
494
491
bus->reg0 = port | GMBUS_RATE_100KHZ;
···
495
498
bus->force_bit = true;
496
499
497
500
intel_gpio_setup(bus, port);
501
+
502
+
ret = i2c_add_adapter(&bus->adapter);
503
+
if (ret)
504
+
goto err;
498
505
}
499
506
500
507
intel_i2c_reset(dev_priv->dev);
+9
-4
drivers/gpu/drm/i915/intel_panel.c
+9
-4
drivers/gpu/drm/i915/intel_panel.c
···
311
311
if (dev_priv->backlight_level == 0)
312
312
dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
313
313
314
-
dev_priv->backlight_enabled = true;
315
-
intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
316
-
317
314
if (INTEL_INFO(dev)->gen >= 4) {
318
315
uint32_t reg, tmp;
319
316
···
323
326
* we don't track the backlight dpms state, hence check whether
324
327
* we have to do anything first. */
325
328
if (tmp & BLM_PWM_ENABLE)
326
-
return;
329
+
goto set_level;
327
330
328
331
if (dev_priv->num_pipe == 3)
329
332
tmp &= ~BLM_PIPE_SELECT_IVB;
···
344
347
I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
345
348
}
346
349
}
350
+
351
+
set_level:
352
+
/* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
353
+
* BLC_PWM_CPU_CTL may be cleared to zero automatically when these
354
+
* registers are set.
355
+
*/
356
+
dev_priv->backlight_enabled = true;
357
+
intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
347
358
}
348
359
349
360
static void intel_panel_init_backlight(struct drm_device *dev)
+23
-18
drivers/gpu/drm/i915/intel_ringbuffer.c
+23
-18
drivers/gpu/drm/i915/intel_ringbuffer.c
···
227
227
* number of bits based on the write domains has little performance
228
228
* impact.
229
229
*/
230
-
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231
-
flags |= PIPE_CONTROL_TLB_INVALIDATE;
232
-
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
233
-
flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
234
-
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
235
-
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
236
-
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
237
-
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
238
-
/*
239
-
* Ensure that any following seqno writes only happen when the render
240
-
* cache is indeed flushed (but only if the caller actually wants that).
241
-
*/
242
-
if (flush_domains)
230
+
if (flush_domains) {
231
+
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
232
+
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
233
+
/*
234
+
* Ensure that any following seqno writes only happen
235
+
* when the render cache is indeed flushed.
236
+
*/
243
237
flags |= PIPE_CONTROL_CS_STALL;
238
+
}
239
+
if (invalidate_domains) {
240
+
flags |= PIPE_CONTROL_TLB_INVALIDATE;
241
+
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
242
+
flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
243
+
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
244
+
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
245
+
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
246
+
/*
247
+
* TLB invalidate requires a post-sync write.
248
+
*/
249
+
flags |= PIPE_CONTROL_QW_WRITE;
250
+
}
244
251
245
-
ret = intel_ring_begin(ring, 6);
252
+
ret = intel_ring_begin(ring, 4);
246
253
if (ret)
247
254
return ret;
248
255
249
-
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
256
+
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
250
257
intel_ring_emit(ring, flags);
251
258
intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
252
-
intel_ring_emit(ring, 0); /* lower dword */
253
-
intel_ring_emit(ring, 0); /* uppwer dword */
254
-
intel_ring_emit(ring, MI_NOOP);
259
+
intel_ring_emit(ring, 0);
255
260
intel_ring_advance(ring);
256
261
257
262
return 0;
+1
-1
drivers/gpu/drm/nouveau/nouveau_i2c.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_i2c.c
-1
drivers/gpu/drm/nouveau/nouveau_state.c
-1
drivers/gpu/drm/nouveau/nouveau_state.c
+9
drivers/gpu/drm/nouveau/nv84_fifo.c
+9
drivers/gpu/drm/nouveau/nv84_fifo.c
···
117
117
struct drm_device *dev = chan->dev;
118
118
struct drm_nouveau_private *dev_priv = dev->dev_private;
119
119
unsigned long flags;
120
+
u32 save;
120
121
121
122
/* remove channel from playlist, will context switch if active */
122
123
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
123
124
nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000);
124
125
nv50_fifo_playlist_update(dev);
125
126
127
+
save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
128
+
126
129
/* tell any engines on this channel to unload their contexts */
127
130
nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
128
131
if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff))
129
132
NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
133
+
134
+
nv_wr32(dev, 0x002520, save);
130
135
131
136
nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000);
132
137
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
···
189
184
struct drm_nouveau_private *dev_priv = dev->dev_private;
190
185
struct nv84_fifo_priv *priv = nv_engine(dev, engine);
191
186
int i;
187
+
u32 save;
192
188
193
189
/* set playlist length to zero, fifo will unload context */
194
190
nv_wr32(dev, 0x0032ec, 0);
191
+
192
+
save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
195
193
196
194
/* tell all connected engines to unload their contexts */
197
195
for (i = 0; i < priv->base.channels; i++) {
···
207
199
}
208
200
}
209
201
202
+
nv_wr32(dev, 0x002520, save);
210
203
nv_wr32(dev, 0x002140, 0);
211
204
return 0;
212
205
}
+1
-1
drivers/gpu/drm/nouveau/nvc0_pm.c
+1
-1
drivers/gpu/drm/nouveau/nvc0_pm.c
+1
-1
drivers/gpu/drm/nouveau/nvd0_display.c
+1
-1
drivers/gpu/drm/nouveau/nvd0_display.c
···
790
790
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
791
791
int ch = EVO_CURS(nv_crtc->index);
792
792
793
-
evo_piow(crtc->dev, ch, 0x0084, (y << 16) | x);
793
+
evo_piow(crtc->dev, ch, 0x0084, (y << 16) | (x & 0xffff));
794
794
evo_piow(crtc->dev, ch, 0x0080, 0x00000000);
795
795
return 0;
796
796
}
+33
-4
drivers/gpu/drm/nouveau/nve0_fifo.c
+33
-4
drivers/gpu/drm/nouveau/nve0_fifo.c
···
294
294
printk(" on channel 0x%010llx\n", (u64)inst << 12);
295
295
}
296
296
297
+
static int
298
+
nve0_fifo_page_flip(struct drm_device *dev, u32 chid)
299
+
{
300
+
struct nve0_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO);
301
+
struct drm_nouveau_private *dev_priv = dev->dev_private;
302
+
struct nouveau_channel *chan = NULL;
303
+
unsigned long flags;
304
+
int ret = -EINVAL;
305
+
306
+
spin_lock_irqsave(&dev_priv->channels.lock, flags);
307
+
if (likely(chid >= 0 && chid < priv->base.channels)) {
308
+
chan = dev_priv->channels.ptr[chid];
309
+
if (likely(chan))
310
+
ret = nouveau_finish_page_flip(chan, NULL);
311
+
}
312
+
spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
313
+
return ret;
314
+
}
315
+
297
316
static void
298
317
nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
299
318
{
···
322
303
u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
323
304
u32 subc = (addr & 0x00070000);
324
305
u32 mthd = (addr & 0x00003ffc);
306
+
u32 show = stat;
325
307
326
-
NV_INFO(dev, "PSUBFIFO %d:", unit);
327
-
nouveau_bitfield_print(nve0_fifo_subfifo_intr, stat);
328
-
NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
329
-
unit, chid, subc, mthd, data);
308
+
if (stat & 0x00200000) {
309
+
if (mthd == 0x0054) {
310
+
if (!nve0_fifo_page_flip(dev, chid))
311
+
show &= ~0x00200000;
312
+
}
313
+
}
314
+
315
+
if (show) {
316
+
NV_INFO(dev, "PFIFO%d:", unit);
317
+
nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
318
+
NV_INFO(dev, "PFIFO%d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
319
+
unit, chid, subc, mthd, data);
320
+
}
330
321
331
322
nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
332
323
nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);