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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC
MT8196 uses set/clr/upd registers for mux gate enable/disable control,
along with a FENC bit to check the status. Add new set of mux gate
clock operations with support for set/clr/upd and FENC status logic.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Laura Nao
and committed by
Stephen Boyd
d3c4dde9
2c327a17
+94
+49
drivers/clk/mediatek/clk-mux.c
+49
drivers/clk/mediatek/clk-mux.c
···
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#include "clk-mux.h"
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#define MTK_WAIT_FENC_DONE_US 30
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struct mtk_clk_mux {
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struct clk_hw hw;
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struct regmap *regmap;
···
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static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_clk_mux, hw);
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}
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static int mtk_clk_mux_fenc_enable_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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unsigned long flags;
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u32 val;
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int ret;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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regmap_write(mux->regmap, mux->data->clr_ofs,
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BIT(mux->data->gate_shift));
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ret = regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_mon_ofs,
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val, val & BIT(mux->data->fenc_shift), 1,
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MTK_WAIT_FENC_DONE_US);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return ret;
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}
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static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
···
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regmap_write(mux->regmap, mux->data->set_ofs,
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BIT(mux->data->gate_shift));
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}
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static int mtk_clk_mux_fenc_is_enabled(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 val;
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regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);
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return !!(val & BIT(mux->data->fenc_shift));
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}
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static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
···
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.determine_rate = mtk_clk_mux_determine_rate,
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};
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EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
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const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops = {
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.enable = mtk_clk_mux_fenc_enable_setclr,
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.disable = mtk_clk_mux_disable_setclr,
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.is_enabled = mtk_clk_mux_fenc_is_enabled,
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_setclr_lock,
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.determine_rate = mtk_clk_mux_determine_rate,
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};
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EXPORT_SYMBOL_GPL(mtk_mux_gate_fenc_clr_set_upd_ops);
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static struct clk_hw *mtk_clk_register_mux(struct device *dev,
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const struct mtk_mux *mux,
+45
drivers/clk/mediatek/clk-mux.h
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drivers/clk/mediatek/clk-mux.h
···
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u32 set_ofs;
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u32 clr_ofs;
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u32 upd_ofs;
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u32 fenc_sta_mon_ofs;
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u8 mux_shift;
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u8 mux_width;
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u8 gate_shift;
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s8 upd_shift;
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u8 fenc_shift;
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const struct clk_ops *ops;
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signed char num_parents;
···
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extern const struct clk_ops mtk_mux_clr_set_upd_ops;
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extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
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extern const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops;
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#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
···
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
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mtk_mux_clr_set_upd_ops)
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#define MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
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_num_parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
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_shift, _width, _gate, _upd_ofs, _upd, \
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_fenc_sta_mon_ofs, _fenc, _flags) { \
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.id = _id, \
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.name = _name, \
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.mux_ofs = _mux_ofs, \
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.set_ofs = _mux_set_ofs, \
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.clr_ofs = _mux_clr_ofs, \
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.upd_ofs = _upd_ofs, \
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.fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_shift = _gate, \
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.upd_shift = _upd, \
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.fenc_shift = _fenc, \
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.parent_names = _parents, \
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.parent_index = _paridx, \
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.num_parents = _num_parents, \
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.flags = _flags, \
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.ops = &mtk_mux_gate_fenc_clr_set_upd_ops, \
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}
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#define MUX_GATE_FENC_CLR_SET_UPD(_id, _name, _parents, \
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_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
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_shift, _width, _gate, _upd_ofs, _upd, \
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_fenc_sta_mon_ofs, _fenc) \
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MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
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NULL, ARRAY_SIZE(_parents), _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, \
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_width, _gate, _upd_ofs, _upd, \
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_fenc_sta_mon_ofs, _fenc, 0)
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#define MUX_GATE_FENC_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \
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_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
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_shift, _width, _gate, _upd_ofs, _upd, \
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_fenc_sta_mon_ofs, _fenc) \
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MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
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ARRAY_SIZE(_paridx), _mux_ofs, _mux_set_ofs, \
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_mux_clr_ofs, _shift, _width, _gate, _upd_ofs, _upd, \
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_fenc_sta_mon_ofs, _fenc, 0)
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int mtk_clk_register_muxes(struct device *dev,
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const struct mtk_mux *muxes,