Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'char-misc-6.2-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver fixes from Greg KH:
"Here are a number of small char/misc/whatever driver fixes. They
include:
- IIO driver fixes for some reported problems
- nvmem driver fixes
- fpga driver fixes
- debugfs memory leak fix in the hv_balloon and irqdomain code
(irqdomain change was acked by the maintainer)
All have been in linux-next with no reported problems"
* tag 'char-misc-6.2-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (33 commits)
kernel/irq/irqdomain.c: fix memory leak with using debugfs_lookup()
HV: hv_balloon: fix memory leak with using debugfs_lookup()
nvmem: qcom-spmi-sdam: fix module autoloading
nvmem: core: fix return value
nvmem: core: fix cell removal on error
nvmem: core: fix device node refcounting
nvmem: core: fix registration vs use race
nvmem: core: fix cleanup after dev_set_name()
nvmem: core: remove nvmem_config wp_gpio
nvmem: core: initialise nvmem->id early
nvmem: sunxi_sid: Always use 32-bit MMIO reads
nvmem: brcm_nvram: Add check for kzalloc
iio: imu: fxos8700: fix MAGN sensor scale and unit
iio: imu: fxos8700: remove definition FXOS8700_CTRL_ODR_MIN
iio: imu: fxos8700: fix failed initialization ODR mode assignment
iio: imu: fxos8700: fix incorrect ODR mode readback
iio: light: cm32181: Fix PM support on system with 2 I2C resources
iio: hid: fix the retval in gyro_3d_capture_sample
iio: hid: fix the retval in accel_3d_capture_sample
iio: imu: st_lsm6dsx: fix build when CONFIG_IIO_TRIGGERED_BUFFER=m
...
+207
-72
+12
-5
drivers/fpga/intel-m10-bmc-sec-update.c
+12
-5
drivers/fpga/intel-m10-bmc-sec-update.c
···
574
574
len = scnprintf(buf, SEC_UPDATE_LEN_MAX, "secure-update%d",
575
575
sec->fw_name_id);
576
576
sec->fw_name = kmemdup_nul(buf, len, GFP_KERNEL);
577
-
if (!sec->fw_name)
578
-
return -ENOMEM;
577
+
if (!sec->fw_name) {
578
+
ret = -ENOMEM;
579
+
goto fw_name_fail;
580
+
}
579
581
580
582
fwl = firmware_upload_register(THIS_MODULE, sec->dev, sec->fw_name,
581
583
&m10bmc_ops, sec);
582
584
if (IS_ERR(fwl)) {
583
585
dev_err(sec->dev, "Firmware Upload driver failed to start\n");
584
-
kfree(sec->fw_name);
585
-
xa_erase(&fw_upload_xa, sec->fw_name_id);
586
-
return PTR_ERR(fwl);
586
+
ret = PTR_ERR(fwl);
587
+
goto fw_uploader_fail;
587
588
}
588
589
589
590
sec->fwl = fwl;
590
591
return 0;
592
+
593
+
fw_uploader_fail:
594
+
kfree(sec->fw_name);
595
+
fw_name_fail:
596
+
xa_erase(&fw_upload_xa, sec->fw_name_id);
597
+
return ret;
591
598
}
592
599
593
600
static int m10bmc_sec_remove(struct platform_device *pdev)
+2
-2
drivers/fpga/stratix10-soc.c
+2
-2
drivers/fpga/stratix10-soc.c
···
213
213
/* Allocate buffers from the service layer's pool. */
214
214
for (i = 0; i < NUM_SVC_BUFS; i++) {
215
215
kbuf = stratix10_svc_allocate_memory(priv->chan, SVC_BUF_SIZE);
216
-
if (!kbuf) {
216
+
if (IS_ERR(kbuf)) {
217
217
s10_free_buffers(mgr);
218
-
ret = -ENOMEM;
218
+
ret = PTR_ERR(kbuf);
219
219
goto init_done;
220
220
}
221
221
+1
-1
drivers/hv/hv_balloon.c
+1
-1
drivers/hv/hv_balloon.c
+1
drivers/iio/accel/hid-sensor-accel-3d.c
+1
drivers/iio/accel/hid-sensor-accel-3d.c
+3
-1
drivers/iio/adc/berlin2-adc.c
+3
-1
drivers/iio/adc/berlin2-adc.c
+9
-2
drivers/iio/adc/imx8qxp-adc.c
+9
-2
drivers/iio/adc/imx8qxp-adc.c
···
86
86
87
87
#define IMX8QXP_ADC_TIMEOUT msecs_to_jiffies(100)
88
88
89
+
#define IMX8QXP_ADC_MAX_FIFO_SIZE 16
90
+
89
91
struct imx8qxp_adc {
90
92
struct device *dev;
91
93
void __iomem *regs;
···
97
95
/* Serialise ADC channel reads */
98
96
struct mutex lock;
99
97
struct completion completion;
98
+
u32 fifo[IMX8QXP_ADC_MAX_FIFO_SIZE];
100
99
};
101
100
102
101
#define IMX8QXP_ADC_CHAN(_idx) { \
···
241
238
return ret;
242
239
}
243
240
244
-
*val = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
245
-
readl(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
241
+
*val = adc->fifo[0];
246
242
247
243
mutex_unlock(&adc->lock);
248
244
return IIO_VAL_INT;
···
267
265
{
268
266
struct imx8qxp_adc *adc = dev_id;
269
267
u32 fifo_count;
268
+
int i;
270
269
271
270
fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK,
272
271
readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL));
272
+
273
+
for (i = 0; i < fifo_count; i++)
274
+
adc->fifo[i] = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
275
+
readl_relaxed(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
273
276
274
277
if (fifo_count)
275
278
complete(&adc->completion);
+1
drivers/iio/adc/stm32-dfsdm-adc.c
+1
drivers/iio/adc/stm32-dfsdm-adc.c
+32
drivers/iio/adc/twl6030-gpadc.c
+32
drivers/iio/adc/twl6030-gpadc.c
···
57
57
#define TWL6030_GPADCS BIT(1)
58
58
#define TWL6030_GPADCR BIT(0)
59
59
60
+
#define USB_VBUS_CTRL_SET 0x04
61
+
#define USB_ID_CTRL_SET 0x06
62
+
63
+
#define TWL6030_MISC1 0xE4
64
+
#define VBUS_MEAS 0x01
65
+
#define ID_MEAS 0x01
66
+
67
+
#define VAC_MEAS 0x04
68
+
#define VBAT_MEAS 0x02
69
+
#define BB_MEAS 0x01
70
+
71
+
60
72
/**
61
73
* struct twl6030_chnl_calib - channel calibration
62
74
* @gain: slope coefficient for ideal curve
···
936
924
TWL6030_REG_TOGGLE1);
937
925
if (ret < 0) {
938
926
dev_err(dev, "failed to enable GPADC module\n");
927
+
return ret;
928
+
}
929
+
930
+
ret = twl_i2c_write_u8(TWL_MODULE_USB, VBUS_MEAS, USB_VBUS_CTRL_SET);
931
+
if (ret < 0) {
932
+
dev_err(dev, "failed to wire up inputs\n");
933
+
return ret;
934
+
}
935
+
936
+
ret = twl_i2c_write_u8(TWL_MODULE_USB, ID_MEAS, USB_ID_CTRL_SET);
937
+
if (ret < 0) {
938
+
dev_err(dev, "failed to wire up inputs\n");
939
+
return ret;
940
+
}
941
+
942
+
ret = twl_i2c_write_u8(TWL6030_MODULE_ID0,
943
+
VBAT_MEAS | BB_MEAS | VAC_MEAS,
944
+
TWL6030_MISC1);
945
+
if (ret < 0) {
946
+
dev_err(dev, "failed to wire up inputs\n");
939
947
return ret;
940
948
}
941
949
+1
-1
drivers/iio/adc/xilinx-ams.c
+1
-1
drivers/iio/adc/xilinx-ams.c
+1
drivers/iio/gyro/hid-sensor-gyro-3d.c
+1
drivers/iio/gyro/hid-sensor-gyro-3d.c
+89
-22
drivers/iio/imu/fxos8700_core.c
+89
-22
drivers/iio/imu/fxos8700_core.c
···
10
10
#include <linux/regmap.h>
11
11
#include <linux/acpi.h>
12
12
#include <linux/bitops.h>
13
+
#include <linux/bitfield.h>
13
14
14
15
#include <linux/iio/iio.h>
15
16
#include <linux/iio/sysfs.h>
···
145
144
#define FXOS8700_NVM_DATA_BNK0 0xa7
146
145
147
146
/* Bit definitions for FXOS8700_CTRL_REG1 */
148
-
#define FXOS8700_CTRL_ODR_MSK 0x38
149
147
#define FXOS8700_CTRL_ODR_MAX 0x00
150
-
#define FXOS8700_CTRL_ODR_MIN GENMASK(4, 3)
148
+
#define FXOS8700_CTRL_ODR_MSK GENMASK(5, 3)
151
149
152
150
/* Bit definitions for FXOS8700_M_CTRL_REG1 */
153
151
#define FXOS8700_HMS_MASK GENMASK(1, 0)
···
320
320
switch (iio_type) {
321
321
case IIO_ACCEL:
322
322
return FXOS8700_ACCEL;
323
-
case IIO_ANGL_VEL:
323
+
case IIO_MAGN:
324
324
return FXOS8700_MAGN;
325
325
default:
326
326
return -EINVAL;
···
345
345
static int fxos8700_set_scale(struct fxos8700_data *data,
346
346
enum fxos8700_sensor t, int uscale)
347
347
{
348
-
int i;
348
+
int i, ret, val;
349
+
bool active_mode;
349
350
static const int scale_num = ARRAY_SIZE(fxos8700_accel_scale);
350
351
struct device *dev = regmap_get_device(data->regmap);
351
352
352
353
if (t == FXOS8700_MAGN) {
353
-
dev_err(dev, "Magnetometer scale is locked at 1200uT\n");
354
+
dev_err(dev, "Magnetometer scale is locked at 0.001Gs\n");
354
355
return -EINVAL;
356
+
}
357
+
358
+
/*
359
+
* When device is in active mode, it failed to set an ACCEL
360
+
* full-scale range(2g/4g/8g) in FXOS8700_XYZ_DATA_CFG.
361
+
* This is not align with the datasheet, but it is a fxos8700
362
+
* chip behavier. Set the device in standby mode before setting
363
+
* an ACCEL full-scale range.
364
+
*/
365
+
ret = regmap_read(data->regmap, FXOS8700_CTRL_REG1, &val);
366
+
if (ret)
367
+
return ret;
368
+
369
+
active_mode = val & FXOS8700_ACTIVE;
370
+
if (active_mode) {
371
+
ret = regmap_write(data->regmap, FXOS8700_CTRL_REG1,
372
+
val & ~FXOS8700_ACTIVE);
373
+
if (ret)
374
+
return ret;
355
375
}
356
376
357
377
for (i = 0; i < scale_num; i++)
···
381
361
if (i == scale_num)
382
362
return -EINVAL;
383
363
384
-
return regmap_write(data->regmap, FXOS8700_XYZ_DATA_CFG,
364
+
ret = regmap_write(data->regmap, FXOS8700_XYZ_DATA_CFG,
385
365
fxos8700_accel_scale[i].bits);
366
+
if (ret)
367
+
return ret;
368
+
return regmap_write(data->regmap, FXOS8700_CTRL_REG1,
369
+
active_mode);
386
370
}
387
371
388
372
static int fxos8700_get_scale(struct fxos8700_data *data,
···
396
372
static const int scale_num = ARRAY_SIZE(fxos8700_accel_scale);
397
373
398
374
if (t == FXOS8700_MAGN) {
399
-
*uscale = 1200; /* Magnetometer is locked at 1200uT */
375
+
*uscale = 1000; /* Magnetometer is locked at 0.001Gs */
400
376
return 0;
401
377
}
402
378
···
418
394
int axis, int *val)
419
395
{
420
396
u8 base, reg;
397
+
s16 tmp;
421
398
int ret;
422
-
enum fxos8700_sensor type = fxos8700_to_sensor(chan_type);
423
399
424
-
base = type ? FXOS8700_OUT_X_MSB : FXOS8700_M_OUT_X_MSB;
400
+
/*
401
+
* Different register base addresses varies with channel types.
402
+
* This bug hasn't been noticed before because using an enum is
403
+
* really hard to read. Use an a switch statement to take over that.
404
+
*/
405
+
switch (chan_type) {
406
+
case IIO_ACCEL:
407
+
base = FXOS8700_OUT_X_MSB;
408
+
break;
409
+
case IIO_MAGN:
410
+
base = FXOS8700_M_OUT_X_MSB;
411
+
break;
412
+
default:
413
+
return -EINVAL;
414
+
}
425
415
426
416
/* Block read 6 bytes of device output registers to avoid data loss */
427
417
ret = regmap_bulk_read(data->regmap, base, data->buf,
428
-
FXOS8700_DATA_BUF_SIZE);
418
+
sizeof(data->buf));
429
419
if (ret)
430
420
return ret;
431
421
432
422
/* Convert axis to buffer index */
433
423
reg = axis - IIO_MOD_X;
434
424
425
+
/*
426
+
* Convert to native endianness. The accel data and magn data
427
+
* are signed, so a forced type conversion is needed.
428
+
*/
429
+
tmp = be16_to_cpu(data->buf[reg]);
430
+
431
+
/*
432
+
* ACCEL output data registers contain the X-axis, Y-axis, and Z-axis
433
+
* 14-bit left-justified sample data and MAGN output data registers
434
+
* contain the X-axis, Y-axis, and Z-axis 16-bit sample data. Apply
435
+
* a signed 2 bits right shift to the readback raw data from ACCEL
436
+
* output data register and keep that from MAGN sensor as the origin.
437
+
* Value should be extended to 32 bit.
438
+
*/
439
+
switch (chan_type) {
440
+
case IIO_ACCEL:
441
+
tmp = tmp >> 2;
442
+
break;
443
+
case IIO_MAGN:
444
+
/* Nothing to do */
445
+
break;
446
+
default:
447
+
return -EINVAL;
448
+
}
449
+
435
450
/* Convert to native endianness */
436
-
*val = sign_extend32(be16_to_cpu(data->buf[reg]), 15);
451
+
*val = sign_extend32(tmp, 15);
437
452
438
453
return 0;
439
454
}
···
508
445
if (i >= odr_num)
509
446
return -EINVAL;
510
447
511
-
return regmap_update_bits(data->regmap,
512
-
FXOS8700_CTRL_REG1,
513
-
FXOS8700_CTRL_ODR_MSK + FXOS8700_ACTIVE,
514
-
fxos8700_odr[i].bits << 3 | active_mode);
448
+
val &= ~FXOS8700_CTRL_ODR_MSK;
449
+
val |= FIELD_PREP(FXOS8700_CTRL_ODR_MSK, fxos8700_odr[i].bits) | FXOS8700_ACTIVE;
450
+
return regmap_write(data->regmap, FXOS8700_CTRL_REG1, val);
515
451
}
516
452
517
453
static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
···
523
461
if (ret)
524
462
return ret;
525
463
526
-
val &= FXOS8700_CTRL_ODR_MSK;
464
+
val = FIELD_GET(FXOS8700_CTRL_ODR_MSK, val);
527
465
528
466
for (i = 0; i < odr_num; i++)
529
467
if (val == fxos8700_odr[i].bits)
···
588
526
static IIO_CONST_ATTR(in_magn_sampling_frequency_available,
589
527
"1.5625 6.25 12.5 50 100 200 400 800");
590
528
static IIO_CONST_ATTR(in_accel_scale_available, "0.000244 0.000488 0.000976");
591
-
static IIO_CONST_ATTR(in_magn_scale_available, "0.000001200");
529
+
static IIO_CONST_ATTR(in_magn_scale_available, "0.001000");
592
530
593
531
static struct attribute *fxos8700_attrs[] = {
594
532
&iio_const_attr_in_accel_sampling_frequency_available.dev_attr.attr,
···
654
592
if (ret)
655
593
return ret;
656
594
657
-
/* Max ODR (800Hz individual or 400Hz hybrid), active mode */
658
-
ret = regmap_write(data->regmap, FXOS8700_CTRL_REG1,
659
-
FXOS8700_CTRL_ODR_MAX | FXOS8700_ACTIVE);
595
+
/*
596
+
* Set max full-scale range (+/-8G) for ACCEL sensor in chip
597
+
* initialization then activate the device.
598
+
*/
599
+
ret = regmap_write(data->regmap, FXOS8700_XYZ_DATA_CFG, MODE_8G);
660
600
if (ret)
661
601
return ret;
662
602
663
-
/* Set for max full-scale range (+/-8G) */
664
-
return regmap_write(data->regmap, FXOS8700_XYZ_DATA_CFG, MODE_8G);
603
+
/* Max ODR (800Hz individual or 400Hz hybrid), active mode */
604
+
return regmap_update_bits(data->regmap, FXOS8700_CTRL_REG1,
605
+
FXOS8700_CTRL_ODR_MSK | FXOS8700_ACTIVE,
606
+
FIELD_PREP(FXOS8700_CTRL_ODR_MSK, FXOS8700_CTRL_ODR_MAX) |
607
+
FXOS8700_ACTIVE);
665
608
}
666
609
667
610
static void fxos8700_chip_uninit(void *data)
+1
drivers/iio/imu/st_lsm6dsx/Kconfig
+1
drivers/iio/imu/st_lsm6dsx/Kconfig
+5
-4
drivers/iio/light/cm32181.c
+5
-4
drivers/iio/light/cm32181.c
···
440
440
if (!indio_dev)
441
441
return -ENOMEM;
442
442
443
+
i2c_set_clientdata(client, indio_dev);
444
+
443
445
/*
444
446
* Some ACPI systems list 2 I2C resources for the CM3218 sensor, the
445
447
* SMBus Alert Response Address (ARA, 0x0c) and the actual I2C address.
···
461
459
if (IS_ERR(client))
462
460
return PTR_ERR(client);
463
461
}
464
-
465
-
i2c_set_clientdata(client, indio_dev);
466
462
467
463
cm32181 = iio_priv(indio_dev);
468
464
cm32181->client = client;
···
490
490
491
491
static int cm32181_suspend(struct device *dev)
492
492
{
493
-
struct i2c_client *client = to_i2c_client(dev);
493
+
struct cm32181_chip *cm32181 = iio_priv(dev_get_drvdata(dev));
494
+
struct i2c_client *client = cm32181->client;
494
495
495
496
return i2c_smbus_write_word_data(client, CM32181_REG_ADDR_CMD,
496
497
CM32181_CMD_ALS_DISABLE);
···
499
498
500
499
static int cm32181_resume(struct device *dev)
501
500
{
502
-
struct i2c_client *client = to_i2c_client(dev);
503
501
struct cm32181_chip *cm32181 = iio_priv(dev_get_drvdata(dev));
502
+
struct i2c_client *client = cm32181->client;
504
503
505
504
return i2c_smbus_write_word_data(client, CM32181_REG_ADDR_CMD,
506
505
cm32181->conf_regs[CM32181_REG_ADDR_CMD]);
+3
drivers/nvmem/brcm_nvram.c
+3
drivers/nvmem/brcm_nvram.c
+30
-30
drivers/nvmem/core.c
+30
-30
drivers/nvmem/core.c
···
770
770
return ERR_PTR(rval);
771
771
}
772
772
773
-
if (config->wp_gpio)
774
-
nvmem->wp_gpio = config->wp_gpio;
775
-
else if (!config->ignore_wp)
773
+
nvmem->id = rval;
774
+
775
+
nvmem->dev.type = &nvmem_provider_type;
776
+
nvmem->dev.bus = &nvmem_bus_type;
777
+
nvmem->dev.parent = config->dev;
778
+
779
+
device_initialize(&nvmem->dev);
780
+
781
+
if (!config->ignore_wp)
776
782
nvmem->wp_gpio = gpiod_get_optional(config->dev, "wp",
777
783
GPIOD_OUT_HIGH);
778
784
if (IS_ERR(nvmem->wp_gpio)) {
779
-
ida_free(&nvmem_ida, nvmem->id);
780
785
rval = PTR_ERR(nvmem->wp_gpio);
781
-
kfree(nvmem);
782
-
return ERR_PTR(rval);
786
+
nvmem->wp_gpio = NULL;
787
+
goto err_put_device;
783
788
}
784
789
785
790
kref_init(&nvmem->refcnt);
786
791
INIT_LIST_HEAD(&nvmem->cells);
787
792
788
-
nvmem->id = rval;
789
793
nvmem->owner = config->owner;
790
794
if (!nvmem->owner && config->dev->driver)
791
795
nvmem->owner = config->dev->driver->owner;
792
796
nvmem->stride = config->stride ?: 1;
793
797
nvmem->word_size = config->word_size ?: 1;
794
798
nvmem->size = config->size;
795
-
nvmem->dev.type = &nvmem_provider_type;
796
-
nvmem->dev.bus = &nvmem_bus_type;
797
-
nvmem->dev.parent = config->dev;
798
799
nvmem->root_only = config->root_only;
799
800
nvmem->priv = config->priv;
800
801
nvmem->type = config->type;
···
823
822
break;
824
823
}
825
824
826
-
if (rval) {
827
-
ida_free(&nvmem_ida, nvmem->id);
828
-
kfree(nvmem);
829
-
return ERR_PTR(rval);
830
-
}
825
+
if (rval)
826
+
goto err_put_device;
831
827
832
828
nvmem->read_only = device_property_present(config->dev, "read-only") ||
833
829
config->read_only || !nvmem->reg_write;
···
833
835
nvmem->dev.groups = nvmem_dev_groups;
834
836
#endif
835
837
836
-
dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name);
837
-
838
-
rval = device_register(&nvmem->dev);
839
-
if (rval)
840
-
goto err_put_device;
841
-
842
838
if (nvmem->nkeepout) {
843
839
rval = nvmem_validate_keepouts(nvmem);
844
840
if (rval)
845
-
goto err_device_del;
841
+
goto err_put_device;
846
842
}
847
843
848
844
if (config->compat) {
849
845
rval = nvmem_sysfs_setup_compat(nvmem, config);
850
846
if (rval)
851
-
goto err_device_del;
847
+
goto err_put_device;
852
848
}
853
849
854
850
if (config->cells) {
855
851
rval = nvmem_add_cells(nvmem, config->cells, config->ncells);
856
852
if (rval)
857
-
goto err_teardown_compat;
853
+
goto err_remove_cells;
858
854
}
859
855
860
856
rval = nvmem_add_cells_from_table(nvmem);
···
859
867
if (rval)
860
868
goto err_remove_cells;
861
869
870
+
dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name);
871
+
872
+
rval = device_add(&nvmem->dev);
873
+
if (rval)
874
+
goto err_remove_cells;
875
+
862
876
blocking_notifier_call_chain(&nvmem_notifier, NVMEM_ADD, nvmem);
863
877
864
878
return nvmem;
865
879
866
880
err_remove_cells:
867
881
nvmem_device_remove_all_cells(nvmem);
868
-
err_teardown_compat:
869
882
if (config->compat)
870
883
nvmem_sysfs_remove_compat(nvmem, config);
871
-
err_device_del:
872
-
device_del(&nvmem->dev);
873
884
err_put_device:
874
885
put_device(&nvmem->dev);
875
886
···
1237
1242
if (!cell_np)
1238
1243
return ERR_PTR(-ENOENT);
1239
1244
1240
-
nvmem_np = of_get_next_parent(cell_np);
1241
-
if (!nvmem_np)
1245
+
nvmem_np = of_get_parent(cell_np);
1246
+
if (!nvmem_np) {
1247
+
of_node_put(cell_np);
1242
1248
return ERR_PTR(-EINVAL);
1249
+
}
1243
1250
1244
1251
nvmem = __nvmem_device_get(nvmem_np, device_match_of_node);
1245
1252
of_node_put(nvmem_np);
1246
-
if (IS_ERR(nvmem))
1253
+
if (IS_ERR(nvmem)) {
1254
+
of_node_put(cell_np);
1247
1255
return ERR_CAST(nvmem);
1256
+
}
1248
1257
1249
1258
cell_entry = nvmem_find_cell_entry_by_node(nvmem, cell_np);
1259
+
of_node_put(cell_np);
1250
1260
if (!cell_entry) {
1251
1261
__nvmem_device_put(nvmem);
1252
1262
return ERR_PTR(-ENOENT);
+1
drivers/nvmem/qcom-spmi-sdam.c
+1
drivers/nvmem/qcom-spmi-sdam.c
+14
-1
drivers/nvmem/sunxi_sid.c
+14
-1
drivers/nvmem/sunxi_sid.c
···
41
41
void *val, size_t bytes)
42
42
{
43
43
struct sunxi_sid *sid = context;
44
+
u32 word;
44
45
45
-
memcpy_fromio(val, sid->base + sid->value_offset + offset, bytes);
46
+
/* .stride = 4 so offset is guaranteed to be aligned */
47
+
__ioread32_copy(val, sid->base + sid->value_offset + offset, bytes / 4);
48
+
49
+
val += round_down(bytes, 4);
50
+
offset += round_down(bytes, 4);
51
+
bytes = bytes % 4;
52
+
53
+
if (!bytes)
54
+
return 0;
55
+
56
+
/* Handle any trailing bytes */
57
+
word = readl_relaxed(sid->base + sid->value_offset + offset);
58
+
memcpy(val, &word, bytes);
46
59
47
60
return 0;
48
61
}
-2
include/linux/nvmem-provider.h
-2
include/linux/nvmem-provider.h
···
70
70
* @word_size: Minimum read/write access granularity.
71
71
* @stride: Minimum read/write access stride.
72
72
* @priv: User context passed to read/write callbacks.
73
-
* @wp-gpio: Write protect pin
74
73
* @ignore_wp: Write Protect pin is managed by the provider.
75
74
*
76
75
* Note: A default "nvmem<id>" name will be assigned to the device if
···
84
85
const char *name;
85
86
int id;
86
87
struct module *owner;
87
-
struct gpio_desc *wp_gpio;
88
88
const struct nvmem_cell_info *cells;
89
89
int ncells;
90
90
const struct nvmem_keepout *keepout;
+1
-1
kernel/irq/irqdomain.c
+1
-1
kernel/irq/irqdomain.c