Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-imx-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Add delay to the PCC enable/disable in i.MX7ULP composite, needed by
some specific peripherals
- Simplify the i.MX8MP auxiomix by using devm_auxiliary_device_create()
- Add the i.MX8ULP SIM LPAV platform specific clock provider
* tag 'clk-imx-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx: add driver for imx8ulp's sim lpav
dt-bindings: clock: document 8ULP's SIM LPAV
clk: imx: imx8mp-audiomix: use devm_auxiliary_device_create() to simple code
clk: imx: Add some delay before deassert the reset
+268
-35
+72
Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml
+72
Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml
···
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+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8ULP LPAV System Integration Module (SIM)
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maintainers:
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- Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
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description:
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The i.MX8ULP LPAV subsystem contains a block control module known as
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SIM LPAV, which offers functionalities such as clock gating or reset
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line assertion/de-assertion.
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+
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properties:
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compatible:
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const: fsl,imx8ulp-sim-lpav
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+
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reg:
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maxItems: 1
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+
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clocks:
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maxItems: 3
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+
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clock-names:
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items:
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- const: bus
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- const: core
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- const: plat
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+
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'#clock-cells':
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const: 1
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+
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'#reset-cells':
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const: 1
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+
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mux-controller:
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$ref: /schemas/mux/reg-mux.yaml#
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+
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- mux-controller
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+
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additionalProperties: false
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+
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examples:
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- |
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#include <dt-bindings/clock/imx8ulp-clock.h>
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+
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clock-controller@2da50000 {
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compatible = "fsl,imx8ulp-sim-lpav";
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reg = <0x2da50000 0x10000>;
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clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
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<&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,
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<&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;
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clock-names = "bus", "core", "plat";
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#clock-cells = <1>;
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#reset-cells = <1>;
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+
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mux-controller {
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compatible = "reg-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x8 0x00000200>;
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};
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};
+1
drivers/clk/imx/Kconfig
+1
drivers/clk/imx/Kconfig
+1
drivers/clk/imx/Makefile
+1
drivers/clk/imx/Makefile
+13
drivers/clk/imx/clk-composite-7ulp.c
+13
drivers/clk/imx/clk-composite-7ulp.c
···
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
···
37
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if (ret)
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return ret;
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/* Make sure the IP's clock is ready before release reset */
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udelay(1);
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spin_lock_irqsave(gate->lock, flags);
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/*
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* release the sw reset for peripherals associated with
···
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writel(val, gate->reg);
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spin_unlock_irqrestore(gate->lock, flags);
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/*
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* Read back the register to make sure the previous write has been
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* done in the target HW register. For IP like GPU, after deassert
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* the reset, need to wait for a while to make sure the sync reset
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* is done
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*/
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readl(gate->reg);
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udelay(1);
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return 0;
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}
+4
-35
drivers/clk/imx/clk-imx8mp-audiomix.c
+4
-35
drivers/clk/imx/clk-imx8mp-audiomix.c
···
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#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
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-
static void clk_imx8mp_audiomix_reset_unregister_adev(void *_adev)
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-
{
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struct auxiliary_device *adev = _adev;
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-
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auxiliary_device_delete(adev);
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-
auxiliary_device_uninit(adev);
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-
}
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-
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static void clk_imx8mp_audiomix_reset_adev_release(struct device *dev)
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-
{
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struct auxiliary_device *adev = to_auxiliary_dev(dev);
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-
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kfree(adev);
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-
}
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-
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static int clk_imx8mp_audiomix_reset_controller_register(struct device *dev,
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struct clk_imx8mp_audiomix_priv *priv)
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{
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-
struct auxiliary_device *adev __free(kfree) = NULL;
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-
int ret;
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struct auxiliary_device *adev;
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if (!of_property_present(dev->of_node, "#reset-cells"))
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return 0;
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-
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
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adev = devm_auxiliary_device_create(dev, "reset", NULL);
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if (!adev)
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-
return -ENOMEM;
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return -ENODEV;
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adev->name = "reset";
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adev->dev.parent = dev;
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adev->dev.release = clk_imx8mp_audiomix_reset_adev_release;
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-
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ret = auxiliary_device_init(adev);
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if (ret)
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return ret;
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-
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ret = auxiliary_device_add(adev);
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if (ret) {
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auxiliary_device_uninit(adev);
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return ret;
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}
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-
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return devm_add_action_or_reset(dev, clk_imx8mp_audiomix_reset_unregister_adev,
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-
no_free_ptr(adev));
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return 0;
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}
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#else /* !CONFIG_RESET_CONTROLLER */
+156
drivers/clk/imx/clk-imx8ulp-sim-lpav.c
+156
drivers/clk/imx/clk-imx8ulp-sim-lpav.c
···
1
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2025 NXP
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*/
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#include <dt-bindings/clock/imx8ulp-clock.h>
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+
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#include <linux/auxiliary_bus.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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+
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#define SYSCTRL0 0x8
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+
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#define IMX8ULP_HIFI_CLK_GATE(gname, cname, pname, bidx) \
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{ \
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.name = gname "_cg", \
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.id = IMX8ULP_CLK_SIM_LPAV_HIFI_##cname, \
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.parent = { .fw_name = pname }, \
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.bit = bidx, \
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}
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+
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struct clk_imx8ulp_sim_lpav_data {
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spinlock_t lock; /* shared by MUX, clock gate and reset */
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unsigned long flags; /* for spinlock usage */
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struct clk_hw_onecell_data clk_data; /* keep last */
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};
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struct clk_imx8ulp_sim_lpav_gate {
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const char *name;
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int id;
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const struct clk_parent_data parent;
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u8 bit;
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};
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static struct clk_imx8ulp_sim_lpav_gate gates[] = {
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IMX8ULP_HIFI_CLK_GATE("hifi_core", CORE, "core", 17),
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IMX8ULP_HIFI_CLK_GATE("hifi_pbclk", PBCLK, "bus", 18),
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IMX8ULP_HIFI_CLK_GATE("hifi_plat", PLAT, "plat", 19)
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};
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+
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static void clk_imx8ulp_sim_lpav_lock(void *arg) __acquires(&data->lock)
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{
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struct clk_imx8ulp_sim_lpav_data *data = dev_get_drvdata(arg);
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spin_lock_irqsave(&data->lock, data->flags);
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}
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static void clk_imx8ulp_sim_lpav_unlock(void *arg) __releases(&data->lock)
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{
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struct clk_imx8ulp_sim_lpav_data *data = dev_get_drvdata(arg);
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+
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spin_unlock_irqrestore(&data->lock, data->flags);
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}
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+
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static int clk_imx8ulp_sim_lpav_probe(struct platform_device *pdev)
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{
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const struct regmap_config regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.lock = clk_imx8ulp_sim_lpav_lock,
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.unlock = clk_imx8ulp_sim_lpav_unlock,
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.lock_arg = &pdev->dev,
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};
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struct clk_imx8ulp_sim_lpav_data *data;
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struct auxiliary_device *adev;
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struct regmap *regmap;
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void __iomem *base;
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struct clk_hw *hw;
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int i, ret;
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+
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data = devm_kzalloc(&pdev->dev,
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struct_size(data, clk_data.hws, ARRAY_SIZE(gates)),
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GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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+
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dev_set_drvdata(&pdev->dev, data);
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+
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/*
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* this lock is used directly by the clock gate and indirectly
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* by the reset and mux controller via the regmap API
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*/
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spin_lock_init(&data->lock);
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+
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return dev_err_probe(&pdev->dev, PTR_ERR(base),
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"failed to ioremap base\n");
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/*
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* although the clock gate doesn't use the regmap API to modify the
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* registers, we still need the regmap because of the reset auxiliary
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* driver and the MUX drivers, which use the parent device's regmap
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*/
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regmap = devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
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if (IS_ERR(regmap))
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return dev_err_probe(&pdev->dev, PTR_ERR(regmap),
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"failed to initialize regmap\n");
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+
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data->clk_data.num = ARRAY_SIZE(gates);
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+
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for (i = 0; i < ARRAY_SIZE(gates); i++) {
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hw = devm_clk_hw_register_gate_parent_data(&pdev->dev,
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gates[i].name,
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&gates[i].parent,
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CLK_SET_RATE_PARENT,
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base + SYSCTRL0,
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gates[i].bit,
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0x0, &data->lock);
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if (IS_ERR(hw))
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return dev_err_probe(&pdev->dev, PTR_ERR(hw),
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"failed to register %s gate\n",
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gates[i].name);
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+
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data->clk_data.hws[i] = hw;
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}
122
+
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adev = devm_auxiliary_device_create(&pdev->dev, "reset", NULL);
124
+
if (!adev)
125
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return dev_err_probe(&pdev->dev, -ENODEV,
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"failed to register aux reset\n");
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+
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ret = devm_of_clk_add_hw_provider(&pdev->dev,
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of_clk_hw_onecell_get,
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&data->clk_data);
131
+
if (ret)
132
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return dev_err_probe(&pdev->dev, ret,
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"failed to register clk hw provider\n");
134
+
135
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/* used to probe MUX child device */
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return devm_of_platform_populate(&pdev->dev);
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}
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+
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static const struct of_device_id clk_imx8ulp_sim_lpav_of_match[] = {
140
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{ .compatible = "fsl,imx8ulp-sim-lpav" },
141
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{ }
142
+
};
143
+
MODULE_DEVICE_TABLE(of, clk_imx8ulp_sim_lpav_of_match);
144
+
145
+
static struct platform_driver clk_imx8ulp_sim_lpav_driver = {
146
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.probe = clk_imx8ulp_sim_lpav_probe,
147
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.driver = {
148
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.name = "clk-imx8ulp-sim-lpav",
149
+
.of_match_table = clk_imx8ulp_sim_lpav_of_match,
150
+
},
151
+
};
152
+
module_platform_driver(clk_imx8ulp_sim_lpav_driver);
153
+
154
+
MODULE_LICENSE("GPL");
155
+
MODULE_DESCRIPTION("i.MX8ULP LPAV System Integration Module (SIM) clock driver");
156
+
MODULE_AUTHOR("Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>");
+5
include/dt-bindings/clock/imx8ulp-clock.h
+5
include/dt-bindings/clock/imx8ulp-clock.h
+16
include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h
+16
include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright 2025 NXP
4
+
*/
5
+
6
+
#ifndef DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H
7
+
#define DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H
8
+
9
+
#define IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST 0
10
+
#define IMX8ULP_SIM_LPAV_HIFI4_DSP_RST 1
11
+
#define IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL 2
12
+
#define IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N 3
13
+
#define IMX8ULP_SIM_LPAV_DSI_RST_ESC_N 4
14
+
#define IMX8ULP_SIM_LPAV_DSI_RST_DPI_N 5
15
+
16
+
#endif /* DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H */