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drm/amd/display: Update DMCUB loading sequence for DCN3.5

[Why]
New sequence from HW for reset and firmware reloading has been
provided that aims to stabilize the reload sequence in the case the
firmware is hung or has outstanding requests.

[How]
Update the sequence to remove the DMUIF reset and the redundant
writes in the release.

Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Nicholas Kazlauskas and committed by
Alex Deucher d42b2331 aca63ca8

+3 -13
+3 -13
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
··· 92 92 uint32_t in_reset, is_enabled, scratch, i, pwait_mode; 93 93 94 94 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); 95 + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); 95 96 96 - if (in_reset == 0) { 97 + if (in_reset == 0 && is_enabled != 0) { 97 98 cmd.bits.status = 1; 98 99 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 99 100 cmd.bits.param = 0; 100 101 101 102 dmub->hw_funcs.set_gpint(dmub, cmd); 102 - 103 - /** 104 - * Timeout covers both the ACK and the wait 105 - * for remaining work to finish. 106 - */ 107 103 108 104 for (i = 0; i < timeout; ++i) { 109 105 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) ··· 126 130 /* Force reset in case we timed out, DMCUB is likely hung. */ 127 131 } 128 132 129 - REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); 130 - 131 133 if (is_enabled) { 132 134 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 133 - REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); 135 + udelay(1); 134 136 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 135 137 } 136 138 ··· 154 160 LONO_SOCCLK_GATE_DISABLE, 1, 155 161 LONO_DMCUBCLK_GATE_DISABLE, 1); 156 162 157 - REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); 158 - udelay(1); 159 163 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 160 - REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 161 - udelay(1); 162 164 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 163 165 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); 164 166 }