Merge tag 'tty-7.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

+25

drivers/tty/serial/8250/8250.h

··· 175 175 return value; 176 176 } 177 177 178 + void serial8250_clear_fifos(struct uart_8250_port *p); 178 179 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p); 180 + void serial8250_fifo_wait_for_lsr_thre(struct uart_8250_port *up, unsigned int count); 179 181 180 182 void serial8250_rpm_get(struct uart_8250_port *p); 181 183 void serial8250_rpm_put(struct uart_8250_port *p); ··· 402 400 403 401 return dma && dma->tx_running; 404 402 } 403 + 404 + static inline void serial8250_tx_dma_pause(struct uart_8250_port *p) 405 + { 406 + struct uart_8250_dma *dma = p->dma; 407 + 408 + if (!dma->tx_running) 409 + return; 410 + 411 + dmaengine_pause(dma->txchan); 412 + } 413 + 414 + static inline void serial8250_tx_dma_resume(struct uart_8250_port *p) 415 + { 416 + struct uart_8250_dma *dma = p->dma; 417 + 418 + if (!dma->tx_running) 419 + return; 420 + 421 + dmaengine_resume(dma->txchan); 422 + } 405 423 #else 406 424 static inline int serial8250_tx_dma(struct uart_8250_port *p) 407 425 { ··· 443 421 { 444 422 return false; 445 423 } 424 + 425 + static inline void serial8250_tx_dma_pause(struct uart_8250_port *p) { } 426 + static inline void serial8250_tx_dma_resume(struct uart_8250_port *p) { } 446 427 #endif 447 428 448 429 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)

+15

drivers/tty/serial/8250/8250_dma.c

··· 162 162 */ 163 163 dma->tx_size = 0; 164 164 165 + /* 166 + * We can't use `dmaengine_terminate_sync` because `uart_flush_buffer` is 167 + * holding the uart port spinlock. 168 + */ 165 169 dmaengine_terminate_async(dma->txchan); 170 + 171 + /* 172 + * The callback might or might not run. If it doesn't run, we need to ensure 173 + * that `tx_running` is cleared so that we can schedule new transactions. 174 + * If it does run, then the zombie callback will clear `tx_running` again 175 + * and perform a no-op since `tx_size` was cleared above. 176 + * 177 + * In either case, we ASSUME the DMA transaction will terminate before we 178 + * issue a new `serial8250_tx_dma`. 179 + */ 180 + dma->tx_running = 0; 166 181 } 167 182 168 183 int serial8250_rx_dma(struct uart_8250_port *p)

+239 -65

drivers/tty/serial/8250/8250_dw.c

··· 9 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 11 */ 12 + #include <linux/bitfield.h> 13 + #include <linux/bits.h> 14 + #include <linux/cleanup.h> 12 15 #include <linux/clk.h> 13 16 #include <linux/delay.h> 14 17 #include <linux/device.h> 15 18 #include <linux/io.h> 19 + #include <linux/lockdep.h> 16 20 #include <linux/mod_devicetable.h> 17 21 #include <linux/module.h> 18 22 #include <linux/notifier.h> ··· 44 40 #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ 45 41 46 42 /* DesignWare specific register fields */ 43 + #define DW_UART_IIR_IID GENMASK(3, 0) 44 + 47 45 #define DW_UART_MCR_SIRE BIT(6) 46 + 47 + #define DW_UART_USR_BUSY BIT(0) 48 48 49 49 /* Renesas specific register fields */ 50 50 #define RZN1_UART_xDMACR_DMA_EN BIT(0) ··· 64 56 #define DW_UART_QUIRK_IS_DMA_FC BIT(3) 65 57 #define DW_UART_QUIRK_APMC0D08 BIT(4) 66 58 #define DW_UART_QUIRK_CPR_VALUE BIT(5) 59 + #define DW_UART_QUIRK_IER_KICK BIT(6) 60 + 61 + /* 62 + * Number of consecutive IIR_NO_INT interrupts required to trigger interrupt 63 + * storm prevention code. 64 + */ 65 + #define DW_UART_QUIRK_IER_KICK_THRES 4 67 66 68 67 struct dw8250_platform_data { 69 68 u8 usr_reg; ··· 92 77 93 78 unsigned int skip_autocfg:1; 94 79 unsigned int uart_16550_compatible:1; 80 + unsigned int in_idle:1; 81 + 82 + u8 no_int_count; 95 83 }; 96 84 97 85 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) ··· 125 107 return value; 126 108 } 127 109 128 - /* 129 - * This function is being called as part of the uart_port::serial_out() 130 - * routine. Hence, it must not call serial_port_out() or serial_out() 131 - * against the modified registers here, i.e. LCR. 132 - */ 133 - static void dw8250_force_idle(struct uart_port *p) 110 + static void dw8250_idle_exit(struct uart_port *p) 134 111 { 112 + struct dw8250_data *d = to_dw8250_data(p->private_data); 135 113 struct uart_8250_port *up = up_to_u8250p(p); 136 - unsigned int lsr; 137 114 138 - /* 139 - * The following call currently performs serial_out() 140 - * against the FCR register. Because it differs to LCR 141 - * there will be no infinite loop, but if it ever gets 142 - * modified, we might need a new custom version of it 143 - * that avoids infinite recursion. 144 - */ 145 - serial8250_clear_and_reinit_fifos(up); 115 + if (d->uart_16550_compatible) 116 + return; 146 117 147 - /* 148 - * With PSLVERR_RESP_EN parameter set to 1, the device generates an 149 - * error response when an attempt to read an empty RBR with FIFO 150 - * enabled. 151 - */ 152 - if (up->fcr & UART_FCR_ENABLE_FIFO) { 153 - lsr = serial_port_in(p, UART_LSR); 154 - if (!(lsr & UART_LSR_DR)) 155 - return; 118 + if (up->capabilities & UART_CAP_FIFO) 119 + serial_port_out(p, UART_FCR, up->fcr); 120 + serial_port_out(p, UART_MCR, up->mcr); 121 + serial_port_out(p, UART_IER, up->ier); 122 + 123 + /* DMA Rx is restarted by IRQ handler as needed. */ 124 + if (up->dma) 125 + serial8250_tx_dma_resume(up); 126 + 127 + d->in_idle = 0; 128 + } 129 + 130 + /* 131 + * Ensure BUSY is not asserted. If DW UART is configured with 132 + * !uart_16550_compatible, the writes to LCR, DLL, and DLH fail while 133 + * BUSY is asserted. 134 + * 135 + * Context: port's lock must be held 136 + */ 137 + static int dw8250_idle_enter(struct uart_port *p) 138 + { 139 + struct dw8250_data *d = to_dw8250_data(p->private_data); 140 + unsigned int usr_reg = d->pdata ? d->pdata->usr_reg : DW_UART_USR; 141 + struct uart_8250_port *up = up_to_u8250p(p); 142 + int retries; 143 + u32 lsr; 144 + 145 + lockdep_assert_held_once(&p->lock); 146 + 147 + if (d->uart_16550_compatible) 148 + return 0; 149 + 150 + d->in_idle = 1; 151 + 152 + /* Prevent triggering interrupt from RBR filling */ 153 + serial_port_out(p, UART_IER, 0); 154 + 155 + if (up->dma) { 156 + serial8250_rx_dma_flush(up); 157 + if (serial8250_tx_dma_running(up)) 158 + serial8250_tx_dma_pause(up); 156 159 } 157 160 158 - serial_port_in(p, UART_RX); 161 + /* 162 + * Wait until Tx becomes empty + one extra frame time to ensure all bits 163 + * have been sent on the wire. 164 + * 165 + * FIXME: frame_time delay is too long with very low baudrates. 166 + */ 167 + serial8250_fifo_wait_for_lsr_thre(up, p->fifosize); 168 + ndelay(p->frame_time); 169 + 170 + serial_port_out(p, UART_MCR, up->mcr | UART_MCR_LOOP); 171 + 172 + retries = 4; /* Arbitrary limit, 2 was always enough in tests */ 173 + do { 174 + serial8250_clear_fifos(up); 175 + if (!(serial_port_in(p, usr_reg) & DW_UART_USR_BUSY)) 176 + break; 177 + /* FIXME: frame_time delay is too long with very low baudrates. */ 178 + ndelay(p->frame_time); 179 + } while (--retries); 180 + 181 + lsr = serial_lsr_in(up); 182 + if (lsr & UART_LSR_DR) { 183 + serial_port_in(p, UART_RX); 184 + up->lsr_saved_flags = 0; 185 + } 186 + 187 + /* Now guaranteed to have BUSY deasserted? Just sanity check */ 188 + if (serial_port_in(p, usr_reg) & DW_UART_USR_BUSY) { 189 + dw8250_idle_exit(p); 190 + return -EBUSY; 191 + } 192 + 193 + return 0; 194 + } 195 + 196 + static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, 197 + unsigned int quot, unsigned int quot_frac) 198 + { 199 + struct uart_8250_port *up = up_to_u8250p(p); 200 + int ret; 201 + 202 + ret = dw8250_idle_enter(p); 203 + if (ret < 0) 204 + return; 205 + 206 + serial_port_out(p, UART_LCR, up->lcr | UART_LCR_DLAB); 207 + if (!(serial_port_in(p, UART_LCR) & UART_LCR_DLAB)) 208 + goto idle_failed; 209 + 210 + serial_dl_write(up, quot); 211 + serial_port_out(p, UART_LCR, up->lcr); 212 + 213 + idle_failed: 214 + dw8250_idle_exit(p); 159 215 } 160 216 161 217 /* 162 218 * This function is being called as part of the uart_port::serial_out() 163 - * routine. Hence, it must not call serial_port_out() or serial_out() 164 - * against the modified registers here, i.e. LCR. 219 + * routine. Hence, special care must be taken when serial_port_out() or 220 + * serial_out() against the modified registers here, i.e. LCR (d->in_idle is 221 + * used to break recursion loop). 165 222 */ 166 223 static void dw8250_check_lcr(struct uart_port *p, unsigned int offset, u32 value) 167 224 { 168 225 struct dw8250_data *d = to_dw8250_data(p->private_data); 169 - void __iomem *addr = p->membase + (offset << p->regshift); 170 - int tries = 1000; 226 + u32 lcr; 227 + int ret; 171 228 172 229 if (offset != UART_LCR || d->uart_16550_compatible) 173 230 return; 174 231 232 + lcr = serial_port_in(p, UART_LCR); 233 + 175 234 /* Make sure LCR write wasn't ignored */ 176 - while (tries--) { 177 - u32 lcr = serial_port_in(p, offset); 235 + if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 236 + return; 178 237 179 - if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 180 - return; 238 + if (d->in_idle) 239 + goto write_err; 181 240 182 - dw8250_force_idle(p); 241 + ret = dw8250_idle_enter(p); 242 + if (ret < 0) 243 + goto write_err; 183 244 184 - #ifdef CONFIG_64BIT 185 - if (p->type == PORT_OCTEON) 186 - __raw_writeq(value & 0xff, addr); 187 - else 188 - #endif 189 - if (p->iotype == UPIO_MEM32) 190 - writel(value, addr); 191 - else if (p->iotype == UPIO_MEM32BE) 192 - iowrite32be(value, addr); 193 - else 194 - writeb(value, addr); 195 - } 245 + serial_port_out(p, UART_LCR, value); 246 + dw8250_idle_exit(p); 247 + return; 248 + 249 + write_err: 196 250 /* 197 251 * FIXME: this deadlocks if port->lock is already held 198 252 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 199 253 */ 254 + return; /* Silences "label at the end of compound statement" */ 255 + } 256 + 257 + /* 258 + * With BUSY, LCR writes can be very expensive (IRQ + complex retry logic). 259 + * If the write does not change the value of the LCR register, skip it entirely. 260 + */ 261 + static bool dw8250_can_skip_reg_write(struct uart_port *p, unsigned int offset, u32 value) 262 + { 263 + struct dw8250_data *d = to_dw8250_data(p->private_data); 264 + u32 lcr; 265 + 266 + if (offset != UART_LCR || d->uart_16550_compatible) 267 + return false; 268 + 269 + lcr = serial_port_in(p, offset); 270 + return lcr == value; 200 271 } 201 272 202 273 /* Returns once the transmitter is empty or we run out of retries */ ··· 314 207 315 208 static void dw8250_serial_out(struct uart_port *p, unsigned int offset, u32 value) 316 209 { 210 + if (dw8250_can_skip_reg_write(p, offset, value)) 211 + return; 212 + 317 213 writeb(value, p->membase + (offset << p->regshift)); 318 214 dw8250_check_lcr(p, offset, value); 319 215 } 320 216 321 217 static void dw8250_serial_out38x(struct uart_port *p, unsigned int offset, u32 value) 322 218 { 219 + if (dw8250_can_skip_reg_write(p, offset, value)) 220 + return; 221 + 323 222 /* Allow the TX to drain before we reconfigure */ 324 223 if (offset == UART_LCR) 325 224 dw8250_tx_wait_empty(p); ··· 350 237 351 238 static void dw8250_serial_outq(struct uart_port *p, unsigned int offset, u32 value) 352 239 { 240 + if (dw8250_can_skip_reg_write(p, offset, value)) 241 + return; 242 + 353 243 value &= 0xff; 354 244 __raw_writeq(value, p->membase + (offset << p->regshift)); 355 245 /* Read back to ensure register write ordering. */ ··· 364 248 365 249 static void dw8250_serial_out32(struct uart_port *p, unsigned int offset, u32 value) 366 250 { 251 + if (dw8250_can_skip_reg_write(p, offset, value)) 252 + return; 253 + 367 254 writel(value, p->membase + (offset << p->regshift)); 368 255 dw8250_check_lcr(p, offset, value); 369 256 } ··· 380 261 381 262 static void dw8250_serial_out32be(struct uart_port *p, unsigned int offset, u32 value) 382 263 { 264 + if (dw8250_can_skip_reg_write(p, offset, value)) 265 + return; 266 + 383 267 iowrite32be(value, p->membase + (offset << p->regshift)); 384 268 dw8250_check_lcr(p, offset, value); 385 269 } ··· 394 272 return dw8250_modify_msr(p, offset, value); 395 273 } 396 274 275 + /* 276 + * INTC10EE UART can IRQ storm while reporting IIR_NO_INT. Inducing IIR value 277 + * change has been observed to break the storm. 278 + * 279 + * If Tx is empty (THRE asserted), we use here IER_THRI to cause IIR_NO_INT -> 280 + * IIR_THRI transition. 281 + */ 282 + static void dw8250_quirk_ier_kick(struct uart_port *p) 283 + { 284 + struct uart_8250_port *up = up_to_u8250p(p); 285 + u32 lsr; 286 + 287 + if (up->ier & UART_IER_THRI) 288 + return; 289 + 290 + lsr = serial_lsr_in(up); 291 + if (!(lsr & UART_LSR_THRE)) 292 + return; 293 + 294 + serial_port_out(p, UART_IER, up->ier | UART_IER_THRI); 295 + serial_port_in(p, UART_LCR); /* safe, no side-effects */ 296 + serial_port_out(p, UART_IER, up->ier); 297 + } 397 298 398 299 static int dw8250_handle_irq(struct uart_port *p) 399 300 { ··· 426 281 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT; 427 282 unsigned int quirks = d->pdata->quirks; 428 283 unsigned int status; 429 - unsigned long flags; 284 + 285 + guard(uart_port_lock_irqsave)(p); 286 + 287 + switch (FIELD_GET(DW_UART_IIR_IID, iir)) { 288 + case UART_IIR_NO_INT: 289 + if (d->uart_16550_compatible || up->dma) 290 + return 0; 291 + 292 + if (quirks & DW_UART_QUIRK_IER_KICK && 293 + d->no_int_count == (DW_UART_QUIRK_IER_KICK_THRES - 1)) 294 + dw8250_quirk_ier_kick(p); 295 + d->no_int_count = (d->no_int_count + 1) % DW_UART_QUIRK_IER_KICK_THRES; 296 + 297 + return 0; 298 + 299 + case UART_IIR_BUSY: 300 + /* Clear the USR */ 301 + serial_port_in(p, d->pdata->usr_reg); 302 + 303 + d->no_int_count = 0; 304 + 305 + return 1; 306 + } 307 + 308 + d->no_int_count = 0; 430 309 431 310 /* 432 311 * There are ways to get Designware-based UARTs into a state where ··· 463 294 * so we limit the workaround only to non-DMA mode. 464 295 */ 465 296 if (!up->dma && rx_timeout) { 466 - uart_port_lock_irqsave(p, &flags); 467 297 status = serial_lsr_in(up); 468 298 469 299 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 470 300 serial_port_in(p, UART_RX); 471 - 472 - uart_port_unlock_irqrestore(p, flags); 473 301 } 474 302 475 303 /* Manually stop the Rx DMA transfer when acting as flow controller */ 476 304 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { 477 - uart_port_lock_irqsave(p, &flags); 478 305 status = serial_lsr_in(up); 479 - uart_port_unlock_irqrestore(p, flags); 480 306 481 307 if (status & (UART_LSR_DR | UART_LSR_BI)) { 482 308 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0); ··· 479 315 } 480 316 } 481 317 482 - if (serial8250_handle_irq(p, iir)) 483 - return 1; 318 + serial8250_handle_irq_locked(p, iir); 484 319 485 - if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 486 - /* Clear the USR */ 487 - serial_port_in(p, d->pdata->usr_reg); 488 - 489 - return 1; 490 - } 491 - 492 - return 0; 320 + return 1; 493 321 } 494 322 495 323 static void dw8250_clk_work_cb(struct work_struct *work) ··· 683 527 reset_control_assert(data); 684 528 } 685 529 530 + static void dw8250_shutdown(struct uart_port *port) 531 + { 532 + struct dw8250_data *d = to_dw8250_data(port->private_data); 533 + 534 + serial8250_do_shutdown(port); 535 + d->no_int_count = 0; 536 + } 537 + 686 538 static int dw8250_probe(struct platform_device *pdev) 687 539 { 688 540 struct uart_8250_port uart = {}, *up = &uart; ··· 709 545 p->type = PORT_8250; 710 546 p->flags = UPF_FIXED_PORT; 711 547 p->dev = dev; 548 + 712 549 p->set_ldisc = dw8250_set_ldisc; 713 550 p->set_termios = dw8250_set_termios; 551 + p->set_divisor = dw8250_set_divisor; 714 552 715 553 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 716 554 if (!data) ··· 820 654 dw8250_quirks(p, data); 821 655 822 656 /* If the Busy Functionality is not implemented, don't handle it */ 823 - if (data->uart_16550_compatible) 657 + if (data->uart_16550_compatible) { 824 658 p->handle_irq = NULL; 825 - else if (data->pdata) 659 + } else if (data->pdata) { 826 660 p->handle_irq = dw8250_handle_irq; 661 + p->shutdown = dw8250_shutdown; 662 + } 827 663 828 664 dw8250_setup_dma_filter(p, data); 829 665 ··· 957 789 .quirks = DW_UART_QUIRK_SKIP_SET_RATE, 958 790 }; 959 791 792 + static const struct dw8250_platform_data dw8250_intc10ee = { 793 + .usr_reg = DW_UART_USR, 794 + .quirks = DW_UART_QUIRK_IER_KICK, 795 + }; 796 + 960 797 static const struct of_device_id dw8250_of_match[] = { 961 798 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, 962 799 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, ··· 991 818 { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb }, 992 819 { "INT3434", (kernel_ulong_t)&dw8250_dw_apb }, 993 820 { "INT3435", (kernel_ulong_t)&dw8250_dw_apb }, 994 - { "INTC10EE", (kernel_ulong_t)&dw8250_dw_apb }, 821 + { "INTC10EE", (kernel_ulong_t)&dw8250_intc10ee }, 995 822 { }, 996 823 }; 997 824 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); ··· 1009 836 1010 837 module_platform_driver(dw8250_platform_driver); 1011 838 839 + MODULE_IMPORT_NS("SERIAL_8250"); 1012 840 MODULE_AUTHOR("Jamie Iles"); 1013 841 MODULE_LICENSE("GPL"); 1014 842 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");

+17

drivers/tty/serial/8250/8250_pci.c

··· 137 137 }; 138 138 139 139 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 140 + #define PCIE_VENDOR_ID_ASIX 0x125B 141 + #define PCIE_DEVICE_ID_AX99100 0x9100 140 142 141 143 static const struct pci_device_id pci_use_msi[] = { 142 144 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, ··· 151 149 0xA000, 0x1000) }, 152 150 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 153 151 PCI_ANY_ID, PCI_ANY_ID) }, 152 + { PCI_DEVICE_SUB(PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100, 153 + 0xA000, 0x1000) }, 154 154 { } 155 155 }; 156 156 ··· 924 920 case PCI_DEVICE_ID_NETMOS_9912: 925 921 case PCI_DEVICE_ID_NETMOS_9922: 926 922 case PCI_DEVICE_ID_NETMOS_9900: 923 + case PCIE_DEVICE_ID_AX99100: 927 924 num_serial = pci_netmos_9900_numports(dev); 928 925 break; 929 926 ··· 2543 2538 */ 2544 2539 { 2545 2540 .vendor = PCI_VENDOR_ID_NETMOS, 2541 + .device = PCI_ANY_ID, 2542 + .subvendor = PCI_ANY_ID, 2543 + .subdevice = PCI_ANY_ID, 2544 + .init = pci_netmos_init, 2545 + .setup = pci_netmos_9900_setup, 2546 + }, 2547 + { 2548 + .vendor = PCIE_VENDOR_ID_ASIX, 2546 2549 .device = PCI_ANY_ID, 2547 2550 .subvendor = PCI_ANY_ID, 2548 2551 .subdevice = PCI_ANY_ID, ··· 6077 6064 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 6078 6065 0xA000, 0x3002, 6079 6066 0, 0, pbn_NETMOS9900_2s_115200 }, 6067 + 6068 + { PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100, 6069 + 0xA000, 0x1000, 6070 + 0, 0, pbn_b0_1_115200 }, 6080 6071 6081 6072 /* 6082 6073 * Best Connectivity and Rosewill PCI Multi I/O cards

+45 -30

drivers/tty/serial/8250/8250_port.c

··· 18 18 #include <linux/irq.h> 19 19 #include <linux/console.h> 20 20 #include <linux/gpio/consumer.h> 21 + #include <linux/lockdep.h> 21 22 #include <linux/sysrq.h> 22 23 #include <linux/delay.h> 23 24 #include <linux/platform_device.h> ··· 489 488 /* 490 489 * FIFO support. 491 490 */ 492 - static void serial8250_clear_fifos(struct uart_8250_port *p) 491 + void serial8250_clear_fifos(struct uart_8250_port *p) 493 492 { 494 493 if (p->capabilities & UART_CAP_FIFO) { 495 494 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); ··· 498 497 serial_out(p, UART_FCR, 0); 499 498 } 500 499 } 500 + EXPORT_SYMBOL_NS_GPL(serial8250_clear_fifos, "SERIAL_8250"); 501 501 502 502 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t); 503 503 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t); ··· 1784 1782 } 1785 1783 1786 1784 /* 1787 - * This handles the interrupt from one port. 1785 + * Context: port's lock must be held by the caller. 1788 1786 */ 1789 - int serial8250_handle_irq(struct uart_port *port, unsigned int iir) 1787 + void serial8250_handle_irq_locked(struct uart_port *port, unsigned int iir) 1790 1788 { 1791 1789 struct uart_8250_port *up = up_to_u8250p(port); 1792 1790 struct tty_port *tport = &port->state->port; 1793 1791 bool skip_rx = false; 1794 - unsigned long flags; 1795 1792 u16 status; 1796 1793 1797 - if (iir & UART_IIR_NO_INT) 1798 - return 0; 1799 - 1800 - uart_port_lock_irqsave(port, &flags); 1794 + lockdep_assert_held_once(&port->lock); 1801 1795 1802 1796 status = serial_lsr_in(up); 1803 1797 ··· 1826 1828 else if (!up->dma->tx_running) 1827 1829 __stop_tx(up); 1828 1830 } 1831 + } 1832 + EXPORT_SYMBOL_NS_GPL(serial8250_handle_irq_locked, "SERIAL_8250"); 1829 1833 1830 - uart_unlock_and_check_sysrq_irqrestore(port, flags); 1834 + /* 1835 + * This handles the interrupt from one port. 1836 + */ 1837 + int serial8250_handle_irq(struct uart_port *port, unsigned int iir) 1838 + { 1839 + if (iir & UART_IIR_NO_INT) 1840 + return 0; 1841 + 1842 + guard(uart_port_lock_irqsave)(port); 1843 + serial8250_handle_irq_locked(port, iir); 1831 1844 1832 1845 return 1; 1833 1846 } ··· 2156 2147 if (up->port.flags & UPF_NO_THRE_TEST) 2157 2148 return; 2158 2149 2159 - if (port->irqflags & IRQF_SHARED) 2160 - disable_irq_nosync(port->irq); 2150 + disable_irq(port->irq); 2161 2151 2162 2152 /* 2163 2153 * Test for UARTs that do not reassert THRE when the transmitter is idle and the interrupt ··· 2178 2170 serial_port_out(port, UART_IER, 0); 2179 2171 } 2180 2172 2181 - if (port->irqflags & IRQF_SHARED) 2182 - enable_irq(port->irq); 2173 + enable_irq(port->irq); 2183 2174 2184 2175 /* 2185 2176 * If the interrupt is not reasserted, or we otherwise don't trust the iir, setup a timer to ··· 2357 2350 void serial8250_do_shutdown(struct uart_port *port) 2358 2351 { 2359 2352 struct uart_8250_port *up = up_to_u8250p(port); 2353 + u32 lcr; 2360 2354 2361 2355 serial8250_rpm_get(up); 2362 2356 /* ··· 2384 2376 port->mctrl &= ~TIOCM_OUT2; 2385 2377 2386 2378 serial8250_set_mctrl(port, port->mctrl); 2379 + 2380 + /* Disable break condition */ 2381 + lcr = serial_port_in(port, UART_LCR); 2382 + lcr &= ~UART_LCR_SBC; 2383 + serial_port_out(port, UART_LCR, lcr); 2387 2384 } 2388 2385 2389 - /* 2390 - * Disable break condition and FIFOs 2391 - */ 2392 - serial_port_out(port, UART_LCR, 2393 - serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); 2394 2386 serial8250_clear_fifos(up); 2395 2387 2396 2388 rsa_disable(up); ··· 2400 2392 * the IRQ chain. 2401 2393 */ 2402 2394 serial_port_in(port, UART_RX); 2395 + /* 2396 + * LCR writes on DW UART can trigger late (unmaskable) IRQs. 2397 + * Handle them before releasing the handler. 2398 + */ 2399 + synchronize_irq(port->irq); 2400 + 2403 2401 serial8250_rpm_put(up); 2404 2402 2405 2403 up->ops->release_irq(up); ··· 3199 3185 } 3200 3186 EXPORT_SYMBOL_GPL(serial8250_set_defaults); 3201 3187 3188 + void serial8250_fifo_wait_for_lsr_thre(struct uart_8250_port *up, unsigned int count) 3189 + { 3190 + unsigned int i; 3191 + 3192 + for (i = 0; i < count; i++) { 3193 + if (wait_for_lsr(up, UART_LSR_THRE)) 3194 + return; 3195 + } 3196 + } 3197 + EXPORT_SYMBOL_NS_GPL(serial8250_fifo_wait_for_lsr_thre, "SERIAL_8250"); 3198 + 3202 3199 #ifdef CONFIG_SERIAL_8250_CONSOLE 3203 3200 3204 3201 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch) ··· 3251 3226 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS); 3252 3227 } 3253 3228 3254 - static void fifo_wait_for_lsr(struct uart_8250_port *up, unsigned int count) 3255 - { 3256 - unsigned int i; 3257 - 3258 - for (i = 0; i < count; i++) { 3259 - if (wait_for_lsr(up, UART_LSR_THRE)) 3260 - return; 3261 - } 3262 - } 3263 - 3264 3229 /* 3265 3230 * Print a string to the serial port using the device FIFO 3266 3231 * ··· 3269 3254 3270 3255 while (s != end) { 3271 3256 /* Allow timeout for each byte of a possibly full FIFO */ 3272 - fifo_wait_for_lsr(up, fifosize); 3257 + serial8250_fifo_wait_for_lsr_thre(up, fifosize); 3273 3258 3274 3259 for (i = 0; i < fifosize && s != end; ++i) { 3275 3260 if (*s == '\n' && !cr_sent) { ··· 3287 3272 * Allow timeout for each byte written since the caller will only wait 3288 3273 * for UART_LSR_BOTH_EMPTY using the timeout of a single character 3289 3274 */ 3290 - fifo_wait_for_lsr(up, tx_count); 3275 + serial8250_fifo_wait_for_lsr_thre(up, tx_count); 3291 3276 } 3292 3277 3293 3278 /*

+4 -1

drivers/tty/serial/serial_core.c

··· 643 643 unsigned int ret; 644 644 645 645 port = uart_port_ref_lock(state, &flags); 646 - ret = kfifo_avail(&state->port.xmit_fifo); 646 + if (!state->port.xmit_buf) 647 + ret = 0; 648 + else 649 + ret = kfifo_avail(&state->port.xmit_fifo); 647 650 uart_port_unlock_deref(port, flags); 648 651 return ret; 649 652 }

+1

drivers/tty/serial/uartlite.c

··· 878 878 pm_runtime_use_autosuspend(&pdev->dev); 879 879 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 880 880 pm_runtime_set_active(&pdev->dev); 881 + pm_runtime_get_noresume(&pdev->dev); 881 882 pm_runtime_enable(&pdev->dev); 882 883 883 884 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);

+8

drivers/tty/vt/vt.c

··· 1339 1339 kfree(vc->vc_saved_screen); 1340 1340 vc->vc_saved_screen = NULL; 1341 1341 } 1342 + vc_uniscr_free(vc->vc_saved_uni_lines); 1343 + vc->vc_saved_uni_lines = NULL; 1342 1344 } 1343 1345 return vc; 1344 1346 } ··· 1886 1884 vc->vc_saved_screen = kmemdup((u16 *)vc->vc_origin, size, GFP_KERNEL); 1887 1885 if (vc->vc_saved_screen == NULL) 1888 1886 return; 1887 + vc->vc_saved_uni_lines = vc->vc_uni_lines; 1888 + vc->vc_uni_lines = NULL; 1889 1889 vc->vc_saved_rows = vc->vc_rows; 1890 1890 vc->vc_saved_cols = vc->vc_cols; 1891 1891 save_cur(vc); ··· 1909 1905 dest = ((u16 *)vc->vc_origin) + r * vc->vc_cols; 1910 1906 memcpy(dest, src, 2 * cols); 1911 1907 } 1908 + vc_uniscr_set(vc, vc->vc_saved_uni_lines); 1909 + vc->vc_saved_uni_lines = NULL; 1912 1910 restore_cur(vc); 1913 1911 /* Update the entire screen */ 1914 1912 if (con_should_update(vc)) ··· 2233 2227 if (vc->vc_saved_screen != NULL) { 2234 2228 kfree(vc->vc_saved_screen); 2235 2229 vc->vc_saved_screen = NULL; 2230 + vc_uniscr_free(vc->vc_saved_uni_lines); 2231 + vc->vc_saved_uni_lines = NULL; 2236 2232 vc->vc_saved_rows = 0; 2237 2233 vc->vc_saved_cols = 0; 2238 2234 }

+1

include/linux/console_struct.h

··· 160 160 struct uni_pagedict **uni_pagedict_loc; /* [!] Location of uni_pagedict variable for this console */ 161 161 u32 **vc_uni_lines; /* unicode screen content */ 162 162 u16 *vc_saved_screen; 163 + u32 **vc_saved_uni_lines; 163 164 unsigned int vc_saved_cols; 164 165 unsigned int vc_saved_rows; 165 166 /* additional information is in vt_kern.h */

+1

include/linux/serial_8250.h

··· 195 195 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud, 196 196 unsigned int quot); 197 197 int fsl8250_handle_irq(struct uart_port *port); 198 + void serial8250_handle_irq_locked(struct uart_port *port, unsigned int iir); 198 199 int serial8250_handle_irq(struct uart_port *port, unsigned int iir); 199 200 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr); 200 201 void serial8250_read_char(struct uart_8250_port *up, u16 lsr);

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