Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc fixes from Benjamin Herrenschmidt:
"Some more P8 related bits, a bunch of fixes for our P7+/P8 HW crypto
drivers, some added workarounds for those radeons that don't do proper
64-bit MSIs and a couple of other trivialities by myself."
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
powerpc/pseries: Make 32-bit MSI quirk work on systems lacking firmware support
powerpc/powernv: Build a zImage.epapr
powerpc: Make radeon 32-bit MSI quirk work on powernv
powerpc: Context switch more PMU related SPRs
powerpc/powernv: Fix condition for when to invalidate the TCE cache
powerpc/pci: Fix bogus message at boot about empty memory resources
powerpc: Fix TLB cleanup at boot on POWER8
drivers/crypto/nx: Fixes for multiple races and issues
+146
-95
+2
arch/powerpc/include/asm/pci-bridge.h
+2
arch/powerpc/include/asm/pci-bridge.h
···
174
174
/* Get the pointer to a device_node's pci_dn */
175
175
#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
176
176
177
+
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
178
+
177
179
extern void * update_dn_pci_info(struct device_node *dn, void *data);
178
180
179
181
static inline int pci_device_from_OF_node(struct device_node *np,
+6
arch/powerpc/include/asm/processor.h
+6
arch/powerpc/include/asm/processor.h
+6
arch/powerpc/kernel/asm-offsets.c
+6
arch/powerpc/kernel/asm-offsets.c
···
127
127
DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr));
128
128
DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr));
129
129
DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr));
130
+
DEFINE(THREAD_SIAR, offsetof(struct thread_struct, siar));
131
+
DEFINE(THREAD_SDAR, offsetof(struct thread_struct, sdar));
132
+
DEFINE(THREAD_SIER, offsetof(struct thread_struct, sier));
133
+
DEFINE(THREAD_MMCR0, offsetof(struct thread_struct, mmcr0));
134
+
DEFINE(THREAD_MMCR2, offsetof(struct thread_struct, mmcr2));
135
+
DEFINE(THREAD_MMCRA, offsetof(struct thread_struct, mmcra));
130
136
#endif
131
137
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
132
138
DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
+6
-2
arch/powerpc/kernel/cpu_setup_power.S
+6
-2
arch/powerpc/kernel/cpu_setup_power.S
···
135
135
blr
136
136
137
137
__init_TLB:
138
-
/* Clear the TLB */
139
-
li r6,128
138
+
/*
139
+
* Clear the TLB using the "IS 3" form of tlbiel instruction
140
+
* (invalidate by congruence class). P7 has 128 CCs, P8 has 512
141
+
* so we just always do 512
142
+
*/
143
+
li r6,512
140
144
mtctr r6
141
145
li r7,0xc00 /* IS field = 0b11 */
142
146
ptesync
+28
arch/powerpc/kernel/entry_64.S
+28
arch/powerpc/kernel/entry_64.S
···
465
465
std r0, THREAD_EBBHR(r3)
466
466
mfspr r0, SPRN_EBBRR
467
467
std r0, THREAD_EBBRR(r3)
468
+
469
+
/* PMU registers made user read/(write) by EBB */
470
+
mfspr r0, SPRN_SIAR
471
+
std r0, THREAD_SIAR(r3)
472
+
mfspr r0, SPRN_SDAR
473
+
std r0, THREAD_SDAR(r3)
474
+
mfspr r0, SPRN_SIER
475
+
std r0, THREAD_SIER(r3)
476
+
mfspr r0, SPRN_MMCR0
477
+
std r0, THREAD_MMCR0(r3)
478
+
mfspr r0, SPRN_MMCR2
479
+
std r0, THREAD_MMCR2(r3)
480
+
mfspr r0, SPRN_MMCRA
481
+
std r0, THREAD_MMCRA(r3)
468
482
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
469
483
#endif
470
484
···
573
559
mtspr SPRN_EBBHR, r0
574
560
ld r0, THREAD_EBBRR(r4)
575
561
mtspr SPRN_EBBRR, r0
562
+
563
+
/* PMU registers made user read/(write) by EBB */
564
+
ld r0, THREAD_SIAR(r4)
565
+
mtspr SPRN_SIAR, r0
566
+
ld r0, THREAD_SDAR(r4)
567
+
mtspr SPRN_SDAR, r0
568
+
ld r0, THREAD_SIER(r4)
569
+
mtspr SPRN_SIER, r0
570
+
ld r0, THREAD_MMCR0(r4)
571
+
mtspr SPRN_MMCR0, r0
572
+
ld r0, THREAD_MMCR2(r4)
573
+
mtspr SPRN_MMCR2, r0
574
+
ld r0, THREAD_MMCRA(r4)
575
+
mtspr SPRN_MMCRA, r0
576
576
577
577
ld r0,THREAD_TAR(r4)
578
578
mtspr SPRN_TAR,r0
+4
-3
arch/powerpc/kernel/pci-common.c
+4
-3
arch/powerpc/kernel/pci-common.c
···
1520
1520
for (i = 0; i < 3; ++i) {
1521
1521
res = &hose->mem_resources[i];
1522
1522
if (!res->flags) {
1523
-
printk(KERN_ERR "PCI: Memory resource 0 not set for "
1524
-
"host bridge %s (domain %d)\n",
1525
-
hose->dn->full_name, hose->global_number);
1523
+
if (i == 0)
1524
+
printk(KERN_ERR "PCI: Memory resource 0 not set for "
1525
+
"host bridge %s (domain %d)\n",
1526
+
hose->dn->full_name, hose->global_number);
1526
1527
continue;
1527
1528
}
1528
1529
offset = hose->mem_offset[i];
+10
arch/powerpc/kernel/pci_64.c
+10
arch/powerpc/kernel/pci_64.c
···
266
266
}
267
267
EXPORT_SYMBOL(pcibus_to_node);
268
268
#endif
269
+
270
+
static void quirk_radeon_32bit_msi(struct pci_dev *dev)
271
+
{
272
+
struct pci_dn *pdn = pci_get_pdn(dev);
273
+
274
+
if (pdn)
275
+
pdn->force_32bit_msi = 1;
276
+
}
277
+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon_32bit_msi);
278
+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon_32bit_msi);
+8
arch/powerpc/kernel/pci_dn.c
+8
arch/powerpc/kernel/pci_dn.c
···
32
32
#include <asm/ppc-pci.h>
33
33
#include <asm/firmware.h>
34
34
35
+
struct pci_dn *pci_get_pdn(struct pci_dev *pdev)
36
+
{
37
+
struct device_node *dn = pci_device_to_OF_node(pdev);
38
+
if (!dn)
39
+
return NULL;
40
+
return PCI_DN(dn);
41
+
}
42
+
35
43
/*
36
44
* Traverse_func that inits the PCI fields of the device node.
37
45
* NOTE: this *must* be done before read/write config to the device.
+1
arch/powerpc/platforms/powernv/Kconfig
+1
arch/powerpc/platforms/powernv/Kconfig
+11
-16
arch/powerpc/platforms/powernv/pci-ioda.c
+11
-16
arch/powerpc/platforms/powernv/pci-ioda.c
···
68
68
define_pe_printk_level(pe_warn, KERN_WARNING);
69
69
define_pe_printk_level(pe_info, KERN_INFO);
70
70
71
-
static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev)
72
-
{
73
-
struct device_node *np;
74
-
75
-
np = pci_device_to_OF_node(dev);
76
-
if (!np)
77
-
return NULL;
78
-
return PCI_DN(np);
79
-
}
80
-
81
71
static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
82
72
{
83
73
unsigned long pe;
···
100
110
{
101
111
struct pci_controller *hose = pci_bus_to_host(dev->bus);
102
112
struct pnv_phb *phb = hose->private_data;
103
-
struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
113
+
struct pci_dn *pdn = pci_get_pdn(dev);
104
114
105
115
if (!pdn)
106
116
return NULL;
···
163
173
164
174
/* Add to all parents PELT-V */
165
175
while (parent) {
166
-
struct pci_dn *pdn = pnv_ioda_get_pdn(parent);
176
+
struct pci_dn *pdn = pci_get_pdn(parent);
167
177
if (pdn && pdn->pe_number != IODA_INVALID_PE) {
168
178
rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
169
179
pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
···
242
252
{
243
253
struct pci_controller *hose = pci_bus_to_host(dev->bus);
244
254
struct pnv_phb *phb = hose->private_data;
245
-
struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
255
+
struct pci_dn *pdn = pci_get_pdn(dev);
246
256
struct pnv_ioda_pe *pe;
247
257
int pe_num;
248
258
···
313
323
struct pci_dev *dev;
314
324
315
325
list_for_each_entry(dev, &bus->devices, bus_list) {
316
-
struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
326
+
struct pci_dn *pdn = pci_get_pdn(dev);
317
327
318
328
if (pdn == NULL) {
319
329
pr_warn("%s: No device node associated with device !\n",
···
426
436
427
437
static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
428
438
{
429
-
struct pci_dn *pdn = pnv_ioda_get_pdn(pdev);
439
+
struct pci_dn *pdn = pci_get_pdn(pdev);
430
440
struct pnv_ioda_pe *pe;
431
441
432
442
/*
···
758
768
unsigned int is_64, struct msi_msg *msg)
759
769
{
760
770
struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
771
+
struct pci_dn *pdn = pci_get_pdn(dev);
761
772
struct irq_data *idata;
762
773
struct irq_chip *ichip;
763
774
unsigned int xive_num = hwirq - phb->msi_base;
···
773
782
/* Check if we have an MVE */
774
783
if (pe->mve_number < 0)
775
784
return -ENXIO;
785
+
786
+
/* Force 32-bit MSI on some broken devices */
787
+
if (pdn && pdn->force_32bit_msi)
788
+
is_64 = 0;
776
789
777
790
/* Assign XIVE to PE */
778
791
rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
···
1030
1035
if (!phb->initialized)
1031
1036
return 0;
1032
1037
1033
-
pdn = pnv_ioda_get_pdn(dev);
1038
+
pdn = pci_get_pdn(dev);
1034
1039
if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1035
1040
return -EINVAL;
1036
1041
+5
-1
arch/powerpc/platforms/powernv/pci.c
+5
-1
arch/powerpc/platforms/powernv/pci.c
···
47
47
{
48
48
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
49
49
struct pnv_phb *phb = hose->private_data;
50
+
struct pci_dn *pdn = pci_get_pdn(pdev);
51
+
52
+
if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
53
+
return -ENODEV;
50
54
51
55
return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
52
56
}
···
371
367
while (npages--)
372
368
*(tcep++) = 0;
373
369
374
-
if (tbl->it_type & TCE_PCI_SWINV_CREATE)
370
+
if (tbl->it_type & TCE_PCI_SWINV_FREE)
375
371
pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
376
372
}
377
373
+40
-35
arch/powerpc/platforms/pseries/msi.c
+40
-35
arch/powerpc/platforms/pseries/msi.c
···
26
26
#define RTAS_CHANGE_MSIX_FN 4
27
27
#define RTAS_CHANGE_32MSI_FN 5
28
28
29
-
static struct pci_dn *get_pdn(struct pci_dev *pdev)
30
-
{
31
-
struct device_node *dn;
32
-
struct pci_dn *pdn;
33
-
34
-
dn = pci_device_to_OF_node(pdev);
35
-
if (!dn) {
36
-
dev_dbg(&pdev->dev, "rtas_msi: No OF device node\n");
37
-
return NULL;
38
-
}
39
-
40
-
pdn = PCI_DN(dn);
41
-
if (!pdn) {
42
-
dev_dbg(&pdev->dev, "rtas_msi: No PCI DN\n");
43
-
return NULL;
44
-
}
45
-
46
-
return pdn;
47
-
}
48
-
49
29
/* RTAS Helpers */
50
30
51
31
static int rtas_change_msi(struct pci_dn *pdn, u32 func, u32 num_irqs)
···
71
91
{
72
92
struct pci_dn *pdn;
73
93
74
-
pdn = get_pdn(pdev);
94
+
pdn = pci_get_pdn(pdev);
75
95
if (!pdn)
76
96
return;
77
97
···
132
152
struct pci_dn *pdn;
133
153
const u32 *req_msi;
134
154
135
-
pdn = get_pdn(pdev);
155
+
pdn = pci_get_pdn(pdev);
136
156
if (!pdn)
137
157
return -ENODEV;
138
158
···
374
394
return 0;
375
395
}
376
396
397
+
static void rtas_hack_32bit_msi_gen2(struct pci_dev *pdev)
398
+
{
399
+
u32 addr_hi, addr_lo;
400
+
401
+
/*
402
+
* We should only get in here for IODA1 configs. This is based on the
403
+
* fact that we using RTAS for MSIs, we don't have the 32 bit MSI RTAS
404
+
* support, and we are in a PCIe Gen2 slot.
405
+
*/
406
+
dev_info(&pdev->dev,
407
+
"rtas_msi: No 32 bit MSI firmware support, forcing 32 bit MSI\n");
408
+
pci_read_config_dword(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_HI, &addr_hi);
409
+
addr_lo = 0xffff0000 | ((addr_hi >> (48 - 32)) << 4);
410
+
pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_LO, addr_lo);
411
+
pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_HI, 0);
412
+
}
413
+
377
414
static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type)
378
415
{
379
416
struct pci_dn *pdn;
···
398
401
struct msi_desc *entry;
399
402
struct msi_msg msg;
400
403
int nvec = nvec_in;
404
+
int use_32bit_msi_hack = 0;
401
405
402
-
pdn = get_pdn(pdev);
406
+
pdn = pci_get_pdn(pdev);
403
407
if (!pdn)
404
408
return -ENODEV;
405
409
···
426
428
*/
427
429
again:
428
430
if (type == PCI_CAP_ID_MSI) {
429
-
if (pdn->force_32bit_msi)
431
+
if (pdn->force_32bit_msi) {
430
432
rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec);
431
-
else
433
+
if (rc < 0) {
434
+
/*
435
+
* We only want to run the 32 bit MSI hack below if
436
+
* the max bus speed is Gen2 speed
437
+
*/
438
+
if (pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT)
439
+
return rc;
440
+
441
+
use_32bit_msi_hack = 1;
442
+
}
443
+
} else
444
+
rc = -1;
445
+
446
+
if (rc < 0)
432
447
rc = rtas_change_msi(pdn, RTAS_CHANGE_MSI_FN, nvec);
433
448
434
-
if (rc < 0 && !pdn->force_32bit_msi) {
449
+
if (rc < 0) {
435
450
pr_debug("rtas_msi: trying the old firmware call.\n");
436
451
rc = rtas_change_msi(pdn, RTAS_CHANGE_FN, nvec);
437
452
}
453
+
454
+
if (use_32bit_msi_hack && rc > 0)
455
+
rtas_hack_32bit_msi_gen2(pdev);
438
456
} else
439
457
rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec);
440
458
···
532
518
}
533
519
arch_initcall(rtas_msi_init);
534
520
535
-
static void quirk_radeon(struct pci_dev *dev)
536
-
{
537
-
struct pci_dn *pdn = get_pdn(dev);
538
-
539
-
if (pdn)
540
-
pdn->force_32bit_msi = 1;
541
-
}
542
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon);
543
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon);
+1
drivers/crypto/nx/nx-aes-cbc.c
+1
drivers/crypto/nx/nx-aes-cbc.c
+1
drivers/crypto/nx/nx-aes-ecb.c
+1
drivers/crypto/nx/nx-aes-ecb.c
+1
-1
drivers/crypto/nx/nx-aes-gcm.c
+1
-1
drivers/crypto/nx/nx-aes-gcm.c
+5
-3
drivers/crypto/nx/nx-sha256.c
+5
-3
drivers/crypto/nx/nx-sha256.c
···
69
69
* 1: <= SHA256_BLOCK_SIZE: copy into state, return 0
70
70
* 2: > SHA256_BLOCK_SIZE: process X blocks, copy in leftover
71
71
*/
72
-
if (len + sctx->count <= SHA256_BLOCK_SIZE) {
72
+
if (len + sctx->count < SHA256_BLOCK_SIZE) {
73
73
memcpy(sctx->buf + sctx->count, data, len);
74
74
sctx->count += len;
75
75
goto out;
···
110
110
atomic_inc(&(nx_ctx->stats->sha256_ops));
111
111
112
112
/* copy the leftover back into the state struct */
113
-
memcpy(sctx->buf, data + len - leftover, leftover);
113
+
if (leftover)
114
+
memcpy(sctx->buf, data + len - leftover, leftover);
114
115
sctx->count = leftover;
115
116
116
117
csbcpb->cpb.sha256.message_bit_length += (u64)
···
130
129
struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
131
130
struct nx_sg *in_sg, *out_sg;
132
131
int rc;
132
+
133
133
134
134
if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
135
135
/* we've hit the nx chip previously, now we're finalizing,
···
164
162
165
163
atomic_inc(&(nx_ctx->stats->sha256_ops));
166
164
167
-
atomic64_add(csbcpb->cpb.sha256.message_bit_length,
165
+
atomic64_add(csbcpb->cpb.sha256.message_bit_length / 8,
168
166
&(nx_ctx->stats->sha256_bytes));
169
167
memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
170
168
out:
+4
-3
drivers/crypto/nx/nx-sha512.c
+4
-3
drivers/crypto/nx/nx-sha512.c
···
69
69
* 1: <= SHA512_BLOCK_SIZE: copy into state, return 0
70
70
* 2: > SHA512_BLOCK_SIZE: process X blocks, copy in leftover
71
71
*/
72
-
if ((u64)len + sctx->count[0] <= SHA512_BLOCK_SIZE) {
72
+
if ((u64)len + sctx->count[0] < SHA512_BLOCK_SIZE) {
73
73
memcpy(sctx->buf + sctx->count[0], data, len);
74
74
sctx->count[0] += len;
75
75
goto out;
···
110
110
atomic_inc(&(nx_ctx->stats->sha512_ops));
111
111
112
112
/* copy the leftover back into the state struct */
113
-
memcpy(sctx->buf, data + len - leftover, leftover);
113
+
if (leftover)
114
+
memcpy(sctx->buf, data + len - leftover, leftover);
114
115
sctx->count[0] = leftover;
115
116
116
117
spbc_bits = csbcpb->cpb.sha512.spbc * 8;
···
169
168
goto out;
170
169
171
170
atomic_inc(&(nx_ctx->stats->sha512_ops));
172
-
atomic64_add(csbcpb->cpb.sha512.message_bit_length_lo,
171
+
atomic64_add(csbcpb->cpb.sha512.message_bit_length_lo / 8,
173
172
&(nx_ctx->stats->sha512_bytes));
174
173
175
174
memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
+7
-31
drivers/crypto/nx/nx.c
+7
-31
drivers/crypto/nx/nx.c
···
211
211
{
212
212
struct nx_sg *nx_insg = nx_ctx->in_sg;
213
213
struct nx_sg *nx_outsg = nx_ctx->out_sg;
214
-
struct blkcipher_walk walk;
215
-
int rc;
216
-
217
-
blkcipher_walk_init(&walk, dst, src, nbytes);
218
-
rc = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE);
219
-
if (rc)
220
-
goto out;
221
214
222
215
if (iv)
223
-
memcpy(iv, walk.iv, AES_BLOCK_SIZE);
216
+
memcpy(iv, desc->info, AES_BLOCK_SIZE);
224
217
225
-
while (walk.nbytes) {
226
-
nx_insg = nx_build_sg_list(nx_insg, walk.src.virt.addr,
227
-
walk.nbytes, nx_ctx->ap->sglen);
228
-
nx_outsg = nx_build_sg_list(nx_outsg, walk.dst.virt.addr,
229
-
walk.nbytes, nx_ctx->ap->sglen);
230
-
231
-
rc = blkcipher_walk_done(desc, &walk, 0);
232
-
if (rc)
233
-
break;
234
-
}
235
-
236
-
if (walk.nbytes) {
237
-
nx_insg = nx_build_sg_list(nx_insg, walk.src.virt.addr,
238
-
walk.nbytes, nx_ctx->ap->sglen);
239
-
nx_outsg = nx_build_sg_list(nx_outsg, walk.dst.virt.addr,
240
-
walk.nbytes, nx_ctx->ap->sglen);
241
-
242
-
rc = 0;
243
-
}
218
+
nx_insg = nx_walk_and_build(nx_insg, nx_ctx->ap->sglen, src, 0, nbytes);
219
+
nx_outsg = nx_walk_and_build(nx_outsg, nx_ctx->ap->sglen, dst, 0, nbytes);
244
220
245
221
/* these lengths should be negative, which will indicate to phyp that
246
222
* the input and output parameters are scatterlists, not linear
247
223
* buffers */
248
224
nx_ctx->op.inlen = (nx_ctx->in_sg - nx_insg) * sizeof(struct nx_sg);
249
225
nx_ctx->op.outlen = (nx_ctx->out_sg - nx_outsg) * sizeof(struct nx_sg);
250
-
out:
251
-
return rc;
226
+
227
+
return 0;
252
228
}
253
229
254
230
/**
···
430
454
if (rc)
431
455
goto out;
432
456
457
+
nx_driver.of.status = NX_OKAY;
458
+
433
459
rc = crypto_register_alg(&nx_ecb_aes_alg);
434
460
if (rc)
435
461
goto out;
···
475
497
rc = crypto_register_shash(&nx_shash_aes_xcbc_alg);
476
498
if (rc)
477
499
goto out_unreg_s512;
478
-
479
-
nx_driver.of.status = NX_OKAY;
480
500
481
501
goto out;
482
502