tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-for-v4.9-rc4' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Fixes for amdgpu, radeon, intel, imx and virtio-gpu.

This is a bit larger than I'd like, but I had some stuff I meant to
send for -rc3 but was waiting for the PAT regression fix to land. So
this is really fixes for rc3 and rc4 in one go.

There are a set of fixes for an oops we've been seeing around MST
display unplug, along with more suspend/resume and shutdown fixes for
amdgpu, one power management follow on fix for nouveau, and set of imx
fixes, and a single virtio-gpu regression fix"

* tag 'drm-fixes-for-v4.9-rc4' of git://people.freedesktop.org/~airlied/linux: (54 commits)
virtio-gpu: fix vblank events
drm/nouveau/acpi: fix check for power resources support
drm/i915: Fix SKL+ 90/270 degree rotated plane coordinate computation
drm/i915: Remove two invalid warns
drm/i915: Rotated view does not need a fence
drm/i915/fbc: fix CFB size calculation for gen8+
drm: i915: Wait for fences on new fb, not old
drm/i915: Clean up DDI DDC/AUX CH sanitation
drm/i915: Respect alternate_aux_channel for all DDI ports
drm/i915/gen9: fix watermarks when using the pipe scaler
drm/i915: Fix mismatched INIT power domain disabling during suspend
drm/i915: fix a read size argument
drm/i915: Use fence_write() from rpm resume
drm/i915/gen9: fix DDB partitioning for multi-screen cases
drm/i915: workaround sparse warning on variable length arrays
drm/i915: keep declarations in i915_drv.h
drm/amd/powerplay: fix bug get wrong evv voltage of Polaris.
drm/amdgpu/si_dpm: workaround for SI kickers
drm/radeon/si_dpm: workaround for SI kickers
drm/amdgpu: fix s3 resume back, uvd dpm randomly can't disable.
...

Linus Torvalds d4c5f43d 66cecb67

+451 -242
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
··· 519 519 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, 520 520 &duplicates); 521 521 if (unlikely(r != 0)) { 522 - DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); 522 + if (r != -ERESTARTSYS) 523 + DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); 523 524 goto error_free_pages; 524 525 } 525 526
+4 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 1959 1959 /* evict remaining vram memory */ 1960 1960 amdgpu_bo_evict_vram(adev); 1961 1961 1962 + amdgpu_atombios_scratch_regs_save(adev); 1962 1963 pci_save_state(dev->pdev); 1963 1964 if (suspend) { 1964 1965 /* Shut down the device */ ··· 2011 2010 return r; 2012 2011 } 2013 2012 } 2013 + amdgpu_atombios_scratch_regs_restore(adev); 2014 2014 2015 2015 /* post card */ 2016 2016 if (!amdgpu_card_posted(adev) || !resume) { ··· 2270 2268 } 2271 2269 2272 2270 if (need_full_reset) { 2273 - /* save scratch */ 2274 - amdgpu_atombios_scratch_regs_save(adev); 2275 2271 r = amdgpu_suspend(adev); 2276 2272 2277 2273 retry: ··· 2279 2279 amdgpu_display_stop_mc_access(adev, &save); 2280 2280 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); 2281 2281 } 2282 - 2282 + amdgpu_atombios_scratch_regs_save(adev); 2283 2283 r = amdgpu_asic_reset(adev); 2284 + amdgpu_atombios_scratch_regs_restore(adev); 2284 2285 /* post card */ 2285 2286 amdgpu_atom_asic_init(adev->mode_info.atom_context); 2286 2287 ··· 2289 2288 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); 2290 2289 r = amdgpu_resume(adev); 2291 2290 } 2292 - /* restore scratch */ 2293 - amdgpu_atombios_scratch_regs_restore(adev); 2294 2291 } 2295 2292 if (!r) { 2296 2293 amdgpu_irq_gpu_reset_resume_helper(adev);
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
··· 68 68 69 69 void amdgpu_fence_slab_fini(void) 70 70 { 71 + rcu_barrier(); 71 72 kmem_cache_destroy(amdgpu_fence_slab); 72 73 } 73 74 /*
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
··· 239 239 if (r) { 240 240 adev->irq.installed = false; 241 241 flush_work(&adev->hotplug_work); 242 + cancel_work_sync(&adev->reset_work); 242 243 return r; 243 244 } 244 245 ··· 265 264 if (adev->irq.msi_enabled) 266 265 pci_disable_msi(adev->pdev); 267 266 flush_work(&adev->hotplug_work); 267 + cancel_work_sync(&adev->reset_work); 268 268 } 269 269 270 270 for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
+2 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
··· 459 459 /* return all clocks in KHz */ 460 460 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 461 461 if (adev->pm.dpm_enabled) { 462 - dev_info.max_engine_clock = 463 - adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 464 - dev_info.max_memory_clock = 465 - adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; 462 + dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 463 + dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 466 464 } else { 467 465 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 468 466 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 1758 1758 fence_put(adev->vm_manager.ids[i].first); 1759 1759 amdgpu_sync_free(&adev->vm_manager.ids[i].active); 1760 1760 fence_put(id->flushed_updates); 1761 + fence_put(id->last_flush); 1761 1762 } 1762 1763 }
+3 -1
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
··· 4075 4075 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 4076 4076 } 4077 4077 } else { 4078 - if (pi->last_mclk_dpm_enable_mask & 0x1) { 4078 + if (pi->uvd_enabled) { 4079 4079 pi->uvd_enabled = false; 4080 4080 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; 4081 4081 amdgpu_ci_send_msg_to_smc_with_parameter(adev, ··· 6235 6235 static int ci_dpm_sw_fini(void *handle) 6236 6236 { 6237 6237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6238 + 6239 + flush_work(&adev->pm.dpm.thermal.work); 6238 6240 6239 6241 mutex_lock(&adev->pm.mutex); 6240 6242 amdgpu_pm_sysfs_fini(adev);
-6
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
··· 3151 3151 3152 3152 static int dce_v10_0_suspend(void *handle) 3153 3153 { 3154 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3155 - 3156 - amdgpu_atombios_scratch_regs_save(adev); 3157 - 3158 3154 return dce_v10_0_hw_fini(handle); 3159 3155 } 3160 3156 ··· 3160 3164 int ret; 3161 3165 3162 3166 ret = dce_v10_0_hw_init(handle); 3163 - 3164 - amdgpu_atombios_scratch_regs_restore(adev); 3165 3167 3166 3168 /* turn on the BL */ 3167 3169 if (adev->mode_info.bl_encoder) {
-6
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
··· 3215 3215 3216 3216 static int dce_v11_0_suspend(void *handle) 3217 3217 { 3218 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3219 - 3220 - amdgpu_atombios_scratch_regs_save(adev); 3221 - 3222 3218 return dce_v11_0_hw_fini(handle); 3223 3219 } 3224 3220 ··· 3224 3228 int ret; 3225 3229 3226 3230 ret = dce_v11_0_hw_init(handle); 3227 - 3228 - amdgpu_atombios_scratch_regs_restore(adev); 3229 3231 3230 3232 /* turn on the BL */ 3231 3233 if (adev->mode_info.bl_encoder) {
-6
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
··· 2482 2482 2483 2483 static int dce_v6_0_suspend(void *handle) 2484 2484 { 2485 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2486 - 2487 - amdgpu_atombios_scratch_regs_save(adev); 2488 - 2489 2485 return dce_v6_0_hw_fini(handle); 2490 2486 } 2491 2487 ··· 2491 2495 int ret; 2492 2496 2493 2497 ret = dce_v6_0_hw_init(handle); 2494 - 2495 - amdgpu_atombios_scratch_regs_restore(adev); 2496 2498 2497 2499 /* turn on the BL */ 2498 2500 if (adev->mode_info.bl_encoder) {
-6
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 3033 3033 3034 3034 static int dce_v8_0_suspend(void *handle) 3035 3035 { 3036 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3037 - 3038 - amdgpu_atombios_scratch_regs_save(adev); 3039 - 3040 3036 return dce_v8_0_hw_fini(handle); 3041 3037 } 3042 3038 ··· 3042 3046 int ret; 3043 3047 3044 3048 ret = dce_v8_0_hw_init(handle); 3045 - 3046 - amdgpu_atombios_scratch_regs_restore(adev); 3047 3049 3048 3050 /* turn on the BL */ 3049 3051 if (adev->mode_info.bl_encoder) {
-1
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 640 640 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201, 641 641 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201, 642 642 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 643 - mmATC_MISC_CG, 0xffffffff, 0x000c0200, 644 643 }; 645 644 646 645 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
+1
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
··· 100 100 101 101 static const u32 stoney_mgcg_cgcg_init[] = 102 102 { 103 + mmATC_MISC_CG, 0xffffffff, 0x000c0200, 103 104 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 104 105 }; 105 106
+2
drivers/gpu/drm/amd/amdgpu/kv_dpm.c
··· 3063 3063 { 3064 3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3065 3065 3066 + flush_work(&adev->pm.dpm.thermal.work); 3067 + 3066 3068 mutex_lock(&adev->pm.mutex); 3067 3069 amdgpu_pm_sysfs_fini(adev); 3068 3070 kv_dpm_fini(adev);
+45 -16
drivers/gpu/drm/amd/amdgpu/si_dpm.c
··· 3477 3477 int i; 3478 3478 struct si_dpm_quirk *p = si_dpm_quirk_list; 3479 3479 3480 + /* limit all SI kickers */ 3481 + if (adev->asic_type == CHIP_PITCAIRN) { 3482 + if ((adev->pdev->revision == 0x81) || 3483 + (adev->pdev->device == 0x6810) || 3484 + (adev->pdev->device == 0x6811) || 3485 + (adev->pdev->device == 0x6816) || 3486 + (adev->pdev->device == 0x6817) || 3487 + (adev->pdev->device == 0x6806)) 3488 + max_mclk = 120000; 3489 + } else if (adev->asic_type == CHIP_VERDE) { 3490 + if ((adev->pdev->revision == 0x81) || 3491 + (adev->pdev->revision == 0x83) || 3492 + (adev->pdev->revision == 0x87) || 3493 + (adev->pdev->device == 0x6820) || 3494 + (adev->pdev->device == 0x6821) || 3495 + (adev->pdev->device == 0x6822) || 3496 + (adev->pdev->device == 0x6823) || 3497 + (adev->pdev->device == 0x682A) || 3498 + (adev->pdev->device == 0x682B)) { 3499 + max_sclk = 75000; 3500 + max_mclk = 80000; 3501 + } 3502 + } else if (adev->asic_type == CHIP_OLAND) { 3503 + if ((adev->pdev->revision == 0xC7) || 3504 + (adev->pdev->revision == 0x80) || 3505 + (adev->pdev->revision == 0x81) || 3506 + (adev->pdev->revision == 0x83) || 3507 + (adev->pdev->device == 0x6604) || 3508 + (adev->pdev->device == 0x6605)) { 3509 + max_sclk = 75000; 3510 + max_mclk = 80000; 3511 + } 3512 + } else if (adev->asic_type == CHIP_HAINAN) { 3513 + if ((adev->pdev->revision == 0x81) || 3514 + (adev->pdev->revision == 0x83) || 3515 + (adev->pdev->revision == 0xC3) || 3516 + (adev->pdev->device == 0x6664) || 3517 + (adev->pdev->device == 0x6665) || 3518 + (adev->pdev->device == 0x6667)) { 3519 + max_sclk = 75000; 3520 + max_mclk = 80000; 3521 + } 3522 + } 3480 3523 /* Apply dpm quirks */ 3481 3524 while (p && p->chip_device != 0) { 3482 3525 if (adev->pdev->vendor == p->chip_vendor && ··· 3531 3488 break; 3532 3489 } 3533 3490 ++p; 3534 - } 3535 - /* limit mclk on all R7 370 parts for stability */ 3536 - if (adev->pdev->device == 0x6811 && 3537 - adev->pdev->revision == 0x81) 3538 - max_mclk = 120000; 3539 - /* limit sclk/mclk on Jet parts for stability */ 3540 - if (adev->pdev->device == 0x6665 && 3541 - adev->pdev->revision == 0xc3) { 3542 - max_sclk = 75000; 3543 - max_mclk = 80000; 3544 - } 3545 - /* Limit clocks for some HD8600 parts */ 3546 - if (adev->pdev->device == 0x6660 && 3547 - adev->pdev->revision == 0x83) { 3548 - max_sclk = 75000; 3549 - max_mclk = 80000; 3550 3491 } 3551 3492 3552 3493 if (rps->vce_active) { ··· 7803 7776 static int si_dpm_sw_fini(void *handle) 7804 7777 { 7805 7778 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7779 + 7780 + flush_work(&adev->pm.dpm.thermal.work); 7806 7781 7807 7782 mutex_lock(&adev->pm.mutex); 7808 7783 amdgpu_pm_sysfs_fini(adev);
+6
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
··· 52 52 #define VCE_V3_0_STACK_SIZE (64 * 1024) 53 53 #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) 54 54 55 + #define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8)) 56 + 55 57 static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); 56 58 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); 57 59 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); ··· 383 381 (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2); 384 382 if (r) 385 383 return r; 384 + 385 + /* 52.8.3 required for 3 ring support */ 386 + if (adev->vce.fw_version < FW_52_8_3) 387 + adev->vce.num_rings = 2; 386 388 387 389 r = amdgpu_vce_resume(adev); 388 390 if (r)
+1 -1
drivers/gpu/drm/amd/amdgpu/vi.c
··· 1651 1651 AMD_CG_SUPPORT_SDMA_MGCG | 1652 1652 AMD_CG_SUPPORT_SDMA_LS | 1653 1653 AMD_CG_SUPPORT_VCE_MGCG; 1654 - adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1654 + adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1655 1655 AMD_PG_SUPPORT_GFX_SMG | 1656 1656 AMD_PG_SUPPORT_GFX_PIPELINE | 1657 1657 AMD_PG_SUPPORT_UVD |
+1 -1
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
··· 716 716 *voltage = 1150; 717 717 } else { 718 718 ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol); 719 - *voltage = (uint16_t)vol/100; 719 + *voltage = (uint16_t)(vol/100); 720 720 } 721 721 return ret; 722 722 }
+2 -1
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
··· 1320 1320 if (0 != result) 1321 1321 return result; 1322 1322 1323 - *voltage = le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel); 1323 + *voltage = le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *) 1324 + (&get_voltage_info_param_space))->ulVoltageLevel); 1324 1325 1325 1326 return result; 1326 1327 }
+6 -3
drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
··· 1201 1201 static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr) 1202 1202 { 1203 1203 const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr); 1204 - const ATOM_Tonga_VCE_State_Table *vce_state_table = 1205 - (ATOM_Tonga_VCE_State_Table *)(((unsigned long)pp_table) + le16_to_cpu(pp_table->usVCEStateTableOffset)); 1204 + const ATOM_Tonga_VCE_State_Table *vce_state_table; 1206 1205 1207 - if (vce_state_table == NULL) 1206 + 1207 + if (pp_table == NULL) 1208 1208 return 0; 1209 + 1210 + vce_state_table = (void *)pp_table + 1211 + le16_to_cpu(pp_table->usVCEStateTableOffset); 1209 1212 1210 1213 return vce_state_table->ucNumEntries; 1211 1214 }
+10 -7
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
··· 1168 1168 1169 1169 tmp_result = (!smum_is_dpm_running(hwmgr)) ? 0 : -1; 1170 1170 PP_ASSERT_WITH_CODE(tmp_result == 0, 1171 - "DPM is already running right now, no need to enable DPM!", 1172 - return 0); 1171 + "DPM is already running", 1172 + ); 1173 1173 1174 1174 if (smu7_voltage_control(hwmgr)) { 1175 1175 tmp_result = smu7_enable_voltage_control(hwmgr); ··· 2127 2127 } 2128 2128 2129 2129 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, 2130 - struct phm_clock_and_voltage_limits *tab) 2130 + struct phm_clock_and_voltage_limits *tab) 2131 2131 { 2132 + uint32_t vddc, vddci; 2132 2133 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2133 2134 2134 2135 if (tab) { 2135 - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, (uint32_t *)&tab->vddc, 2136 - &data->vddc_leakage); 2137 - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, (uint32_t *)&tab->vddci, 2138 - &data->vddci_leakage); 2136 + smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, 2137 + &data->vddc_leakage); 2138 + tab->vddc = vddc; 2139 + smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, 2140 + &data->vddci_leakage); 2141 + tab->vddci = vddci; 2139 2142 } 2140 2143 2141 2144 return 0;
+1
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
··· 645 645 { 646 646 if (sched->thread) 647 647 kthread_stop(sched->thread); 648 + rcu_barrier(); 648 649 if (atomic_dec_and_test(&sched_fence_slab_ref)) 649 650 kmem_cache_destroy(sched_fence_slab); 650 651 }
+2 -2
drivers/gpu/drm/amd/scheduler/sched_fence.c
··· 103 103 } 104 104 105 105 /** 106 - * amd_sched_fence_release - callback that fence can be freed 106 + * amd_sched_fence_release_scheduled - callback that fence can be freed 107 107 * 108 108 * @fence: fence 109 109 * ··· 118 118 } 119 119 120 120 /** 121 - * amd_sched_fence_release_scheduled - drop extra reference 121 + * amd_sched_fence_release_finished - drop extra reference 122 122 * 123 123 * @f: fence 124 124 *
+6 -3
drivers/gpu/drm/drm_atomic.c
··· 420 420 ssize_t expected_size, 421 421 bool *replaced) 422 422 { 423 - struct drm_device *dev = crtc->dev; 424 423 struct drm_property_blob *new_blob = NULL; 425 424 426 425 if (blob_id != 0) { 427 - new_blob = drm_property_lookup_blob(dev, blob_id); 426 + new_blob = drm_property_lookup_blob(crtc->dev, blob_id); 428 427 if (new_blob == NULL) 429 428 return -EINVAL; 430 - if (expected_size > 0 && expected_size != new_blob->length) 429 + 430 + if (expected_size > 0 && expected_size != new_blob->length) { 431 + drm_property_unreference_blob(new_blob); 431 432 return -EINVAL; 433 + } 432 434 } 433 435 434 436 drm_atomic_replace_property_blob(blob, new_blob, replaced); 437 + drm_property_unreference_blob(new_blob); 435 438 436 439 return 0; 437 440 }
-4
drivers/gpu/drm/drm_atomic_helper.c
··· 594 594 struct drm_plane_state *plane_state; 595 595 int i, ret = 0; 596 596 597 - ret = drm_atomic_normalize_zpos(dev, state); 598 - if (ret) 599 - return ret; 600 - 601 597 for_each_plane_in_state(state, plane, plane_state, i) { 602 598 const struct drm_plane_helper_funcs *funcs; 603 599
+5 -1
drivers/gpu/drm/drm_dp_mst_topology.c
··· 914 914 /* no need to clean up vcpi 915 915 * as if we have no connector we never setup a vcpi */ 916 916 drm_dp_port_teardown_pdt(port, port->pdt); 917 + port->pdt = DP_PEER_DEVICE_NONE; 917 918 } 918 919 kfree(port); 919 920 } ··· 1160 1159 drm_dp_put_port(port); 1161 1160 goto out; 1162 1161 } 1163 - if (port->port_num >= DP_MST_LOGICAL_PORT_0) { 1162 + if ((port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV || 1163 + port->pdt == DP_PEER_DEVICE_SST_SINK) && 1164 + port->port_num >= DP_MST_LOGICAL_PORT_0) { 1164 1165 port->cached_edid = drm_get_edid(port->connector, &port->aux.ddc); 1165 1166 drm_mode_connector_set_tile_property(port->connector); 1166 1167 } ··· 2922 2919 mgr->cbs->destroy_connector(mgr, port->connector); 2923 2920 2924 2921 drm_dp_port_teardown_pdt(port, port->pdt); 2922 + port->pdt = DP_PEER_DEVICE_NONE; 2925 2923 2926 2924 if (!port->input && port->vcpi.vcpi > 0) { 2927 2925 drm_dp_mst_reset_vcpi_slots(mgr, port);
+42 -26
drivers/gpu/drm/drm_fb_helper.c
··· 131 131 return 0; 132 132 fail: 133 133 for (i = 0; i < fb_helper->connector_count; i++) { 134 - kfree(fb_helper->connector_info[i]); 134 + struct drm_fb_helper_connector *fb_helper_connector = 135 + fb_helper->connector_info[i]; 136 + 137 + drm_connector_unreference(fb_helper_connector->connector); 138 + 139 + kfree(fb_helper_connector); 135 140 fb_helper->connector_info[i] = NULL; 136 141 } 137 142 fb_helper->connector_count = 0; ··· 608 603 } 609 604 EXPORT_SYMBOL(drm_fb_helper_blank); 610 605 606 + static void drm_fb_helper_modeset_release(struct drm_fb_helper *helper, 607 + struct drm_mode_set *modeset) 608 + { 609 + int i; 610 + 611 + for (i = 0; i < modeset->num_connectors; i++) { 612 + drm_connector_unreference(modeset->connectors[i]); 613 + modeset->connectors[i] = NULL; 614 + } 615 + modeset->num_connectors = 0; 616 + 617 + drm_mode_destroy(helper->dev, modeset->mode); 618 + modeset->mode = NULL; 619 + 620 + /* FIXME should hold a ref? */ 621 + modeset->fb = NULL; 622 + } 623 + 611 624 static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper) 612 625 { 613 626 int i; ··· 635 612 kfree(helper->connector_info[i]); 636 613 } 637 614 kfree(helper->connector_info); 615 + 638 616 for (i = 0; i < helper->crtc_count; i++) { 639 - kfree(helper->crtc_info[i].mode_set.connectors); 640 - if (helper->crtc_info[i].mode_set.mode) 641 - drm_mode_destroy(helper->dev, helper->crtc_info[i].mode_set.mode); 617 + struct drm_mode_set *modeset = &helper->crtc_info[i].mode_set; 618 + 619 + drm_fb_helper_modeset_release(helper, modeset); 620 + kfree(modeset->connectors); 642 621 } 643 622 kfree(helper->crtc_info); 644 623 } ··· 669 644 clip->x2 = clip->y2 = 0; 670 645 spin_unlock_irqrestore(&helper->dirty_lock, flags); 671 646 672 - helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, &clip_copy, 1); 647 + /* call dirty callback only when it has been really touched */ 648 + if (clip_copy.x1 < clip_copy.x2 && clip_copy.y1 < clip_copy.y2) 649 + helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, &clip_copy, 1); 673 650 } 674 651 675 652 /** ··· 2115 2088 struct drm_fb_helper_crtc **crtcs; 2116 2089 struct drm_display_mode **modes; 2117 2090 struct drm_fb_offset *offsets; 2118 - struct drm_mode_set *modeset; 2119 2091 bool *enabled; 2120 2092 int width, height; 2121 2093 int i; ··· 2162 2136 2163 2137 /* need to set the modesets up here for use later */ 2164 2138 /* fill out the connector<->crtc mappings into the modesets */ 2165 - for (i = 0; i < fb_helper->crtc_count; i++) { 2166 - modeset = &fb_helper->crtc_info[i].mode_set; 2167 - modeset->num_connectors = 0; 2168 - modeset->fb = NULL; 2169 - } 2139 + for (i = 0; i < fb_helper->crtc_count; i++) 2140 + drm_fb_helper_modeset_release(fb_helper, 2141 + &fb_helper->crtc_info[i].mode_set); 2170 2142 2171 2143 for (i = 0; i < fb_helper->connector_count; i++) { 2172 2144 struct drm_display_mode *mode = modes[i]; 2173 2145 struct drm_fb_helper_crtc *fb_crtc = crtcs[i]; 2174 2146 struct drm_fb_offset *offset = &offsets[i]; 2175 - modeset = &fb_crtc->mode_set; 2147 + struct drm_mode_set *modeset = &fb_crtc->mode_set; 2176 2148 2177 2149 if (mode && fb_crtc) { 2150 + struct drm_connector *connector = 2151 + fb_helper->connector_info[i]->connector; 2152 + 2178 2153 DRM_DEBUG_KMS("desired mode %s set on crtc %d (%d,%d)\n", 2179 2154 mode->name, fb_crtc->mode_set.crtc->base.id, offset->x, offset->y); 2155 + 2180 2156 fb_crtc->desired_mode = mode; 2181 2157 fb_crtc->x = offset->x; 2182 2158 fb_crtc->y = offset->y; 2183 - if (modeset->mode) 2184 - drm_mode_destroy(dev, modeset->mode); 2185 2159 modeset->mode = drm_mode_duplicate(dev, 2186 2160 fb_crtc->desired_mode); 2187 - modeset->connectors[modeset->num_connectors++] = fb_helper->connector_info[i]->connector; 2161 + drm_connector_reference(connector); 2162 + modeset->connectors[modeset->num_connectors++] = connector; 2188 2163 modeset->fb = fb_helper->fb; 2189 2164 modeset->x = offset->x; 2190 2165 modeset->y = offset->y; 2191 - } 2192 - } 2193 - 2194 - /* Clear out any old modes if there are no more connected outputs. */ 2195 - for (i = 0; i < fb_helper->crtc_count; i++) { 2196 - modeset = &fb_helper->crtc_info[i].mode_set; 2197 - if (modeset->num_connectors == 0) { 2198 - BUG_ON(modeset->fb); 2199 - if (modeset->mode) 2200 - drm_mode_destroy(dev, modeset->mode); 2201 - modeset->mode = NULL; 2202 2166 } 2203 2167 } 2204 2168 out:
+20
drivers/gpu/drm/exynos/exynos_drm_drv.c
··· 262 262 return 0; 263 263 } 264 264 265 + int exynos_atomic_check(struct drm_device *dev, 266 + struct drm_atomic_state *state) 267 + { 268 + int ret; 269 + 270 + ret = drm_atomic_helper_check_modeset(dev, state); 271 + if (ret) 272 + return ret; 273 + 274 + ret = drm_atomic_normalize_zpos(dev, state); 275 + if (ret) 276 + return ret; 277 + 278 + ret = drm_atomic_helper_check_planes(dev, state); 279 + if (ret) 280 + return ret; 281 + 282 + return ret; 283 + } 284 + 265 285 static int exynos_drm_open(struct drm_device *dev, struct drm_file *file) 266 286 { 267 287 struct drm_exynos_file_private *file_priv;
+1
drivers/gpu/drm/exynos/exynos_drm_drv.h
··· 301 301 302 302 int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, 303 303 bool nonblock); 304 + int exynos_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 304 305 305 306 306 307 extern struct platform_driver fimd_driver;
+1 -1
drivers/gpu/drm/exynos/exynos_drm_fb.c
··· 190 190 static const struct drm_mode_config_funcs exynos_drm_mode_config_funcs = { 191 191 .fb_create = exynos_user_fb_create, 192 192 .output_poll_changed = exynos_drm_output_poll_changed, 193 - .atomic_check = drm_atomic_helper_check, 193 + .atomic_check = exynos_atomic_check, 194 194 .atomic_commit = exynos_atomic_commit, 195 195 }; 196 196
+2 -2
drivers/gpu/drm/i915/i915_drv.c
··· 1447 1447 1448 1448 dev_priv->suspend_count++; 1449 1449 1450 - intel_display_set_init_power(dev_priv, false); 1451 - 1452 1450 intel_csr_ucode_suspend(dev_priv); 1453 1451 1454 1452 out: ··· 1463 1465 int ret; 1464 1466 1465 1467 disable_rpm_wakeref_asserts(dev_priv); 1468 + 1469 + intel_display_set_init_power(dev_priv, false); 1466 1470 1467 1471 fw_csr = !IS_BROXTON(dev_priv) && 1468 1472 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
+5
drivers/gpu/drm/i915/i915_drv.h
··· 2883 2883 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2884 2884 unsigned long arg); 2885 2885 #endif 2886 + extern const struct dev_pm_ops i915_pm_ops; 2887 + 2888 + extern int i915_driver_load(struct pci_dev *pdev, 2889 + const struct pci_device_id *ent); 2890 + extern void i915_driver_unload(struct drm_device *dev); 2886 2891 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); 2887 2892 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); 2888 2893 extern void i915_reset(struct drm_i915_private *dev_priv);
+6 -4
drivers/gpu/drm/i915/i915_gem.c
··· 3550 3550 3551 3551 vma->display_alignment = max_t(u64, vma->display_alignment, alignment); 3552 3552 3553 - WARN_ON(obj->pin_display > i915_vma_pin_count(vma)); 3554 - 3555 3553 i915_gem_object_flush_cpu_write_domain(obj); 3556 3554 3557 3555 old_write_domain = obj->base.write_domain; ··· 3586 3588 list_move_tail(&vma->vm_link, &vma->vm->inactive_list); 3587 3589 3588 3590 i915_vma_unpin(vma); 3589 - WARN_ON(vma->obj->pin_display > i915_vma_pin_count(vma)); 3590 3591 } 3591 3592 3592 3593 /** ··· 3742 3745 mappable = (vma->node.start + fence_size <= 3743 3746 dev_priv->ggtt.mappable_end); 3744 3747 3745 - if (mappable && fenceable) 3748 + /* 3749 + * Explicitly disable for rotated VMA since the display does not 3750 + * need the fence and the VMA is not accessible to other users. 3751 + */ 3752 + if (mappable && fenceable && 3753 + vma->ggtt_view.type != I915_GGTT_VIEW_ROTATED) 3746 3754 vma->flags |= I915_VMA_CAN_FENCE; 3747 3755 else 3748 3756 vma->flags &= ~I915_VMA_CAN_FENCE;
+20 -3
drivers/gpu/drm/i915/i915_gem_fence.c
··· 290 290 { 291 291 struct drm_i915_fence_reg *fence = vma->fence; 292 292 293 + assert_rpm_wakelock_held(to_i915(vma->vm->dev)); 294 + 293 295 if (!fence) 294 296 return 0; 295 297 ··· 343 341 struct drm_i915_fence_reg *fence; 344 342 struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL; 345 343 344 + assert_rpm_wakelock_held(to_i915(vma->vm->dev)); 345 + 346 346 /* Just update our place in the LRU if our fence is getting reused. */ 347 347 if (vma->fence) { 348 348 fence = vma->fence; ··· 375 371 struct drm_i915_private *dev_priv = to_i915(dev); 376 372 int i; 377 373 374 + /* Note that this may be called outside of struct_mutex, by 375 + * runtime suspend/resume. The barrier we require is enforced by 376 + * rpm itself - all access to fences/GTT are only within an rpm 377 + * wakeref, and to acquire that wakeref you must pass through here. 378 + */ 379 + 378 380 for (i = 0; i < dev_priv->num_fence_regs; i++) { 379 381 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; 380 382 struct i915_vma *vma = reg->vma; ··· 389 379 * Commit delayed tiling changes if we have an object still 390 380 * attached to the fence, otherwise just clear the fence. 391 381 */ 392 - if (vma && !i915_gem_object_is_tiled(vma->obj)) 393 - vma = NULL; 382 + if (vma && !i915_gem_object_is_tiled(vma->obj)) { 383 + GEM_BUG_ON(!reg->dirty); 384 + GEM_BUG_ON(vma->obj->fault_mappable); 394 385 395 - fence_update(reg, vma); 386 + list_move(&reg->link, &dev_priv->mm.fence_list); 387 + vma->fence = NULL; 388 + vma = NULL; 389 + } 390 + 391 + fence_write(reg, vma); 392 + reg->vma = vma; 396 393 } 397 394 } 398 395
-7
drivers/gpu/drm/i915/i915_pci.c
··· 431 431 }; 432 432 MODULE_DEVICE_TABLE(pci, pciidlist); 433 433 434 - extern int i915_driver_load(struct pci_dev *pdev, 435 - const struct pci_device_id *ent); 436 - 437 434 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 438 435 { 439 436 struct intel_device_info *intel_info = ··· 460 463 return i915_driver_load(pdev, ent); 461 464 } 462 465 463 - extern void i915_driver_unload(struct drm_device *dev); 464 - 465 466 static void i915_pci_remove(struct pci_dev *pdev) 466 467 { 467 468 struct drm_device *dev = pci_get_drvdata(pdev); ··· 467 472 i915_driver_unload(dev); 468 473 drm_dev_unref(dev); 469 474 } 470 - 471 - extern const struct dev_pm_ops i915_pm_ops; 472 475 473 476 static struct pci_driver i915_pci_driver = { 474 477 .name = DRIVER_NAME,
+77 -45
drivers/gpu/drm/i915/intel_bios.c
··· 1031 1031 return mapping[val]; 1032 1032 } 1033 1033 1034 + static void sanitize_ddc_pin(struct drm_i915_private *dev_priv, 1035 + enum port port) 1036 + { 1037 + const struct ddi_vbt_port_info *info = 1038 + &dev_priv->vbt.ddi_port_info[port]; 1039 + enum port p; 1040 + 1041 + if (!info->alternate_ddc_pin) 1042 + return; 1043 + 1044 + for_each_port_masked(p, (1 << port) - 1) { 1045 + struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p]; 1046 + 1047 + if (info->alternate_ddc_pin != i->alternate_ddc_pin) 1048 + continue; 1049 + 1050 + DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as port %c, " 1051 + "disabling port %c DVI/HDMI support\n", 1052 + port_name(p), i->alternate_ddc_pin, 1053 + port_name(port), port_name(p)); 1054 + 1055 + /* 1056 + * If we have multiple ports supposedly sharing the 1057 + * pin, then dvi/hdmi couldn't exist on the shared 1058 + * port. Otherwise they share the same ddc bin and 1059 + * system couldn't communicate with them separately. 1060 + * 1061 + * Due to parsing the ports in alphabetical order, 1062 + * a higher port will always clobber a lower one. 1063 + */ 1064 + i->supports_dvi = false; 1065 + i->supports_hdmi = false; 1066 + i->alternate_ddc_pin = 0; 1067 + } 1068 + } 1069 + 1070 + static void sanitize_aux_ch(struct drm_i915_private *dev_priv, 1071 + enum port port) 1072 + { 1073 + const struct ddi_vbt_port_info *info = 1074 + &dev_priv->vbt.ddi_port_info[port]; 1075 + enum port p; 1076 + 1077 + if (!info->alternate_aux_channel) 1078 + return; 1079 + 1080 + for_each_port_masked(p, (1 << port) - 1) { 1081 + struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p]; 1082 + 1083 + if (info->alternate_aux_channel != i->alternate_aux_channel) 1084 + continue; 1085 + 1086 + DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as port %c, " 1087 + "disabling port %c DP support\n", 1088 + port_name(p), i->alternate_aux_channel, 1089 + port_name(port), port_name(p)); 1090 + 1091 + /* 1092 + * If we have multiple ports supposedlt sharing the 1093 + * aux channel, then DP couldn't exist on the shared 1094 + * port. Otherwise they share the same aux channel 1095 + * and system couldn't communicate with them separately. 1096 + * 1097 + * Due to parsing the ports in alphabetical order, 1098 + * a higher port will always clobber a lower one. 1099 + */ 1100 + i->supports_dp = false; 1101 + i->alternate_aux_channel = 0; 1102 + } 1103 + } 1104 + 1034 1105 static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, 1035 1106 const struct bdb_header *bdb) 1036 1107 { ··· 1176 1105 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port)); 1177 1106 1178 1107 if (is_dvi) { 1179 - if (port == PORT_E) { 1180 - info->alternate_ddc_pin = ddc_pin; 1181 - /* if DDIE share ddc pin with other port, then 1182 - * dvi/hdmi couldn't exist on the shared port. 1183 - * Otherwise they share the same ddc bin and system 1184 - * couldn't communicate with them seperately. */ 1185 - if (ddc_pin == DDC_PIN_B) { 1186 - dev_priv->vbt.ddi_port_info[PORT_B].supports_dvi = 0; 1187 - dev_priv->vbt.ddi_port_info[PORT_B].supports_hdmi = 0; 1188 - } else if (ddc_pin == DDC_PIN_C) { 1189 - dev_priv->vbt.ddi_port_info[PORT_C].supports_dvi = 0; 1190 - dev_priv->vbt.ddi_port_info[PORT_C].supports_hdmi = 0; 1191 - } else if (ddc_pin == DDC_PIN_D) { 1192 - dev_priv->vbt.ddi_port_info[PORT_D].supports_dvi = 0; 1193 - dev_priv->vbt.ddi_port_info[PORT_D].supports_hdmi = 0; 1194 - } 1195 - } else if (ddc_pin == DDC_PIN_B && port != PORT_B) 1196 - DRM_DEBUG_KMS("Unexpected DDC pin for port B\n"); 1197 - else if (ddc_pin == DDC_PIN_C && port != PORT_C) 1198 - DRM_DEBUG_KMS("Unexpected DDC pin for port C\n"); 1199 - else if (ddc_pin == DDC_PIN_D && port != PORT_D) 1200 - DRM_DEBUG_KMS("Unexpected DDC pin for port D\n"); 1108 + info->alternate_ddc_pin = ddc_pin; 1109 + 1110 + sanitize_ddc_pin(dev_priv, port); 1201 1111 } 1202 1112 1203 1113 if (is_dp) { 1204 - if (port == PORT_E) { 1205 - info->alternate_aux_channel = aux_channel; 1206 - /* if DDIE share aux channel with other port, then 1207 - * DP couldn't exist on the shared port. Otherwise 1208 - * they share the same aux channel and system 1209 - * couldn't communicate with them seperately. */ 1210 - if (aux_channel == DP_AUX_A) 1211 - dev_priv->vbt.ddi_port_info[PORT_A].supports_dp = 0; 1212 - else if (aux_channel == DP_AUX_B) 1213 - dev_priv->vbt.ddi_port_info[PORT_B].supports_dp = 0; 1214 - else if (aux_channel == DP_AUX_C) 1215 - dev_priv->vbt.ddi_port_info[PORT_C].supports_dp = 0; 1216 - else if (aux_channel == DP_AUX_D) 1217 - dev_priv->vbt.ddi_port_info[PORT_D].supports_dp = 0; 1218 - } 1219 - else if (aux_channel == DP_AUX_A && port != PORT_A) 1220 - DRM_DEBUG_KMS("Unexpected AUX channel for port A\n"); 1221 - else if (aux_channel == DP_AUX_B && port != PORT_B) 1222 - DRM_DEBUG_KMS("Unexpected AUX channel for port B\n"); 1223 - else if (aux_channel == DP_AUX_C && port != PORT_C) 1224 - DRM_DEBUG_KMS("Unexpected AUX channel for port C\n"); 1225 - else if (aux_channel == DP_AUX_D && port != PORT_D) 1226 - DRM_DEBUG_KMS("Unexpected AUX channel for port D\n"); 1114 + info->alternate_aux_channel = aux_channel; 1115 + 1116 + sanitize_aux_ch(dev_priv, port); 1227 1117 } 1228 1118 1229 1119 if (bdb->version >= 158) {
+1 -1
drivers/gpu/drm/i915/intel_device_info.c
··· 192 192 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; 193 193 const int s_max = 3, ss_max = 3, eu_max = 8; 194 194 int s, ss; 195 - u32 fuse2, eu_disable[s_max]; 195 + u32 fuse2, eu_disable[3]; /* s_max */ 196 196 197 197 fuse2 = I915_READ(GEN8_FUSE2); 198 198 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
+3 -2
drivers/gpu/drm/i915/intel_display.c
··· 2978 2978 /* Rotate src coordinates to match rotated GTT view */ 2979 2979 if (intel_rotation_90_or_270(rotation)) 2980 2980 drm_rect_rotate(&plane_state->base.src, 2981 - fb->width, fb->height, DRM_ROTATE_270); 2981 + fb->width << 16, fb->height << 16, 2982 + DRM_ROTATE_270); 2982 2983 2983 2984 /* 2984 2985 * Handle the AUX surface first since ··· 14311 14310 14312 14311 for_each_plane_in_state(state, plane, plane_state, i) { 14313 14312 struct intel_plane_state *intel_plane_state = 14314 - to_intel_plane_state(plane_state); 14313 + to_intel_plane_state(plane->state); 14315 14314 14316 14315 if (!intel_plane_state->wait_req) 14317 14316 continue;
+42 -33
drivers/gpu/drm/i915/intel_dp.c
··· 1108 1108 return ret; 1109 1109 } 1110 1110 1111 + static enum port intel_aux_port(struct drm_i915_private *dev_priv, 1112 + enum port port) 1113 + { 1114 + const struct ddi_vbt_port_info *info = 1115 + &dev_priv->vbt.ddi_port_info[port]; 1116 + enum port aux_port; 1117 + 1118 + if (!info->alternate_aux_channel) { 1119 + DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", 1120 + port_name(port), port_name(port)); 1121 + return port; 1122 + } 1123 + 1124 + switch (info->alternate_aux_channel) { 1125 + case DP_AUX_A: 1126 + aux_port = PORT_A; 1127 + break; 1128 + case DP_AUX_B: 1129 + aux_port = PORT_B; 1130 + break; 1131 + case DP_AUX_C: 1132 + aux_port = PORT_C; 1133 + break; 1134 + case DP_AUX_D: 1135 + aux_port = PORT_D; 1136 + break; 1137 + default: 1138 + MISSING_CASE(info->alternate_aux_channel); 1139 + aux_port = PORT_A; 1140 + break; 1141 + } 1142 + 1143 + DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", 1144 + port_name(aux_port), port_name(port)); 1145 + 1146 + return aux_port; 1147 + } 1148 + 1111 1149 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, 1112 1150 enum port port) 1113 1151 { ··· 1206 1168 } 1207 1169 } 1208 1170 1209 - /* 1210 - * On SKL we don't have Aux for port E so we rely 1211 - * on VBT to set a proper alternate aux channel. 1212 - */ 1213 - static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) 1214 - { 1215 - const struct ddi_vbt_port_info *info = 1216 - &dev_priv->vbt.ddi_port_info[PORT_E]; 1217 - 1218 - switch (info->alternate_aux_channel) { 1219 - case DP_AUX_A: 1220 - return PORT_A; 1221 - case DP_AUX_B: 1222 - return PORT_B; 1223 - case DP_AUX_C: 1224 - return PORT_C; 1225 - case DP_AUX_D: 1226 - return PORT_D; 1227 - default: 1228 - MISSING_CASE(info->alternate_aux_channel); 1229 - return PORT_A; 1230 - } 1231 - } 1232 - 1233 1171 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, 1234 1172 enum port port) 1235 1173 { 1236 - if (port == PORT_E) 1237 - port = skl_porte_aux_port(dev_priv); 1238 - 1239 1174 switch (port) { 1240 1175 case PORT_A: 1241 1176 case PORT_B: ··· 1224 1213 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, 1225 1214 enum port port, int index) 1226 1215 { 1227 - if (port == PORT_E) 1228 - port = skl_porte_aux_port(dev_priv); 1229 - 1230 1216 switch (port) { 1231 1217 case PORT_A: 1232 1218 case PORT_B: ··· 1261 1253 static void intel_aux_reg_init(struct intel_dp *intel_dp) 1262 1254 { 1263 1255 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 1264 - enum port port = dp_to_dig_port(intel_dp)->port; 1256 + enum port port = intel_aux_port(dev_priv, 1257 + dp_to_dig_port(intel_dp)->port); 1265 1258 int i; 1266 1259 1267 1260 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); ··· 3560 3551 /* Read the eDP Display control capabilities registers */ 3561 3552 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && 3562 3553 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 3563 - intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) == 3564 - sizeof(intel_dp->edp_dpcd))) 3554 + intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 3555 + sizeof(intel_dp->edp_dpcd)) 3565 3556 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), 3566 3557 intel_dp->edp_dpcd); 3567 3558
+3 -1
drivers/gpu/drm/i915/intel_fbc.c
··· 104 104 int lines; 105 105 106 106 intel_fbc_get_plane_source_size(cache, NULL, &lines); 107 - if (INTEL_INFO(dev_priv)->gen >= 7) 107 + if (INTEL_GEN(dev_priv) == 7) 108 108 lines = min(lines, 2048); 109 + else if (INTEL_GEN(dev_priv) >= 8) 110 + lines = min(lines, 2560); 109 111 110 112 /* Hardware needs the full buffer stride, not just the active area. */ 111 113 return lines * cache->fb.stride;
+13 -11
drivers/gpu/drm/i915/intel_pm.c
··· 3362 3362 int num_active; 3363 3363 int id, i; 3364 3364 3365 + /* Clear the partitioning for disabled planes. */ 3366 + memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); 3367 + memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe])); 3368 + 3365 3369 if (WARN_ON(!state)) 3366 3370 return 0; 3367 3371 3368 3372 if (!cstate->base.active) { 3369 3373 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0; 3370 - memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); 3371 - memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe])); 3372 3374 return 0; 3373 3375 } 3374 3376 ··· 3470 3468 return 0; 3471 3469 } 3472 3470 3473 - static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) 3474 - { 3475 - /* TODO: Take into account the scalers once we support them */ 3476 - return config->base.adjusted_mode.crtc_clock; 3477 - } 3478 - 3479 3471 /* 3480 3472 * The max latency should be 257 (max the punit can code is 255 and we add 2us 3481 3473 * for the read latency) and cpp should always be <= 8, so that ··· 3520 3524 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate 3521 3525 * with additional adjustments for plane-specific scaling. 3522 3526 */ 3523 - adjusted_pixel_rate = skl_pipe_pixel_rate(cstate); 3527 + adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate); 3524 3528 downscale_amount = skl_plane_downscale_amount(pstate); 3525 3529 3526 3530 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16; ··· 3732 3736 if (!cstate->base.active) 3733 3737 return 0; 3734 3738 3735 - if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0)) 3739 + if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0)) 3736 3740 return 0; 3737 3741 3738 3742 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, 3739 - skl_pipe_pixel_rate(cstate)); 3743 + ilk_pipe_pixel_rate(cstate)); 3740 3744 } 3741 3745 3742 3746 static void skl_compute_transition_wm(struct intel_crtc_state *cstate, ··· 4045 4049 realloc_pipes = ~0; 4046 4050 intel_state->wm_results.dirty_pipes = ~0; 4047 4051 } 4052 + 4053 + /* 4054 + * We're not recomputing for the pipes not included in the commit, so 4055 + * make sure we start with the current state. 4056 + */ 4057 + memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb)); 4048 4058 4049 4059 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) { 4050 4060 struct intel_crtc_state *cstate;
+4 -2
drivers/gpu/drm/imx/imx-drm-core.c
··· 357 357 int ret; 358 358 359 359 drm = drm_dev_alloc(&imx_drm_driver, dev); 360 - if (!drm) 361 - return -ENOMEM; 360 + if (IS_ERR(drm)) 361 + return PTR_ERR(drm); 362 362 363 363 imxdrm = devm_kzalloc(dev, sizeof(*imxdrm), GFP_KERNEL); 364 364 if (!imxdrm) { ··· 436 436 437 437 err_fbhelper: 438 438 drm_kms_helper_poll_fini(drm); 439 + #if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) 439 440 if (imxdrm->fbhelper) 440 441 drm_fbdev_cma_fini(imxdrm->fbhelper); 441 442 err_unbind: 443 + #endif 442 444 component_unbind_all(drm->dev, drm); 443 445 err_vblank: 444 446 drm_vblank_cleanup(drm);
+21 -7
drivers/gpu/drm/imx/ipuv3-plane.c
··· 103 103 (state->src_x >> 16) / 2 - eba; 104 104 } 105 105 106 - static void ipu_plane_atomic_set_base(struct ipu_plane *ipu_plane, 107 - struct drm_plane_state *old_state) 106 + static void ipu_plane_atomic_set_base(struct ipu_plane *ipu_plane) 108 107 { 109 108 struct drm_plane *plane = &ipu_plane->base; 110 109 struct drm_plane_state *state = plane->state; 110 + struct drm_crtc_state *crtc_state = state->crtc->state; 111 111 struct drm_framebuffer *fb = state->fb; 112 112 unsigned long eba, ubo, vbo; 113 113 int active; ··· 117 117 switch (fb->pixel_format) { 118 118 case DRM_FORMAT_YUV420: 119 119 case DRM_FORMAT_YVU420: 120 - if (old_state->fb) 120 + if (!drm_atomic_crtc_needs_modeset(crtc_state)) 121 121 break; 122 122 123 123 /* ··· 149 149 break; 150 150 } 151 151 152 - if (old_state->fb) { 152 + if (!drm_atomic_crtc_needs_modeset(crtc_state)) { 153 153 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch); 154 154 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba); 155 155 ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active); ··· 259 259 struct drm_framebuffer *fb = state->fb; 260 260 struct drm_framebuffer *old_fb = old_state->fb; 261 261 unsigned long eba, ubo, vbo, old_ubo, old_vbo; 262 + int hsub, vsub; 262 263 263 264 /* Ok to disable */ 264 265 if (!fb) ··· 356 355 if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) 357 356 return -EINVAL; 358 357 359 - if (old_fb) { 358 + if (old_fb && 359 + (old_fb->pixel_format == DRM_FORMAT_YUV420 || 360 + old_fb->pixel_format == DRM_FORMAT_YVU420)) { 360 361 old_ubo = drm_plane_state_to_ubo(old_state); 361 362 old_vbo = drm_plane_state_to_vbo(old_state); 362 363 if (ubo != old_ubo || vbo != old_vbo) ··· 373 370 374 371 if (old_fb && old_fb->pitches[1] != fb->pitches[1]) 375 372 crtc_state->mode_changed = true; 373 + 374 + /* 375 + * The x/y offsets must be even in case of horizontal/vertical 376 + * chroma subsampling. 377 + */ 378 + hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 379 + vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 380 + if (((state->src_x >> 16) & (hsub - 1)) || 381 + ((state->src_y >> 16) & (vsub - 1))) 382 + return -EINVAL; 376 383 } 377 384 378 385 return 0; ··· 405 392 struct drm_crtc_state *crtc_state = state->crtc->state; 406 393 407 394 if (!drm_atomic_crtc_needs_modeset(crtc_state)) { 408 - ipu_plane_atomic_set_base(ipu_plane, old_state); 395 + ipu_plane_atomic_set_base(ipu_plane); 409 396 return; 410 397 } 411 398 } ··· 437 424 ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false); 438 425 break; 439 426 default: 427 + ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true); 440 428 break; 441 429 } 442 430 } ··· 451 437 ipu_cpmem_set_high_priority(ipu_plane->ipu_ch); 452 438 ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1); 453 439 ipu_cpmem_set_stride(ipu_plane->ipu_ch, state->fb->pitches[0]); 454 - ipu_plane_atomic_set_base(ipu_plane, old_state); 440 + ipu_plane_atomic_set_base(ipu_plane); 455 441 ipu_plane_enable(ipu_plane); 456 442 } 457 443
+2 -1
drivers/gpu/drm/nouveau/nouveau_acpi.c
··· 240 240 if (!parent_adev) 241 241 return false; 242 242 243 - return acpi_has_method(parent_adev->handle, "_PR3"); 243 + return parent_adev->power.flags.power_resources && 244 + acpi_has_method(parent_adev->handle, "_PR3"); 244 245 } 245 246 246 247 static void nouveau_dsm_pci_probe(struct pci_dev *pdev, acpi_handle *dhandle_out,
+1 -3
drivers/gpu/drm/radeon/ni.c
··· 1396 1396 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 1397 1397 int ring, u32 cp_int_cntl) 1398 1398 { 1399 - u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3; 1400 - 1401 - WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3)); 1399 + WREG32(SRBM_GFX_CNTL, RINGID(ring)); 1402 1400 WREG32(CP_INT_CNTL, cp_int_cntl); 1403 1401 } 1404 1402
+1 -1
drivers/gpu/drm/radeon/radeon_dp_auxch.c
··· 105 105 106 106 tmp &= AUX_HPD_SEL(0x7); 107 107 tmp |= AUX_HPD_SEL(chan->rec.hpd); 108 - tmp |= AUX_EN | AUX_LS_READ_EN | AUX_HPD_DISCON(0x1); 108 + tmp |= AUX_EN | AUX_LS_READ_EN; 109 109 110 110 WREG32(AUX_CONTROL + aux_offset[instance], tmp); 111 111
+43 -10
drivers/gpu/drm/radeon/si_dpm.c
··· 2999 2999 int i; 3000 3000 struct si_dpm_quirk *p = si_dpm_quirk_list; 3001 3001 3002 + /* limit all SI kickers */ 3003 + if (rdev->family == CHIP_PITCAIRN) { 3004 + if ((rdev->pdev->revision == 0x81) || 3005 + (rdev->pdev->device == 0x6810) || 3006 + (rdev->pdev->device == 0x6811) || 3007 + (rdev->pdev->device == 0x6816) || 3008 + (rdev->pdev->device == 0x6817) || 3009 + (rdev->pdev->device == 0x6806)) 3010 + max_mclk = 120000; 3011 + } else if (rdev->family == CHIP_VERDE) { 3012 + if ((rdev->pdev->revision == 0x81) || 3013 + (rdev->pdev->revision == 0x83) || 3014 + (rdev->pdev->revision == 0x87) || 3015 + (rdev->pdev->device == 0x6820) || 3016 + (rdev->pdev->device == 0x6821) || 3017 + (rdev->pdev->device == 0x6822) || 3018 + (rdev->pdev->device == 0x6823) || 3019 + (rdev->pdev->device == 0x682A) || 3020 + (rdev->pdev->device == 0x682B)) { 3021 + max_sclk = 75000; 3022 + max_mclk = 80000; 3023 + } 3024 + } else if (rdev->family == CHIP_OLAND) { 3025 + if ((rdev->pdev->revision == 0xC7) || 3026 + (rdev->pdev->revision == 0x80) || 3027 + (rdev->pdev->revision == 0x81) || 3028 + (rdev->pdev->revision == 0x83) || 3029 + (rdev->pdev->device == 0x6604) || 3030 + (rdev->pdev->device == 0x6605)) { 3031 + max_sclk = 75000; 3032 + max_mclk = 80000; 3033 + } 3034 + } else if (rdev->family == CHIP_HAINAN) { 3035 + if ((rdev->pdev->revision == 0x81) || 3036 + (rdev->pdev->revision == 0x83) || 3037 + (rdev->pdev->revision == 0xC3) || 3038 + (rdev->pdev->device == 0x6664) || 3039 + (rdev->pdev->device == 0x6665) || 3040 + (rdev->pdev->device == 0x6667)) { 3041 + max_sclk = 75000; 3042 + max_mclk = 80000; 3043 + } 3044 + } 3002 3045 /* Apply dpm quirks */ 3003 3046 while (p && p->chip_device != 0) { 3004 3047 if (rdev->pdev->vendor == p->chip_vendor && ··· 3053 3010 break; 3054 3011 } 3055 3012 ++p; 3056 - } 3057 - /* limit mclk on all R7 370 parts for stability */ 3058 - if (rdev->pdev->device == 0x6811 && 3059 - rdev->pdev->revision == 0x81) 3060 - max_mclk = 120000; 3061 - /* limit sclk/mclk on Jet parts for stability */ 3062 - if (rdev->pdev->device == 0x6665 && 3063 - rdev->pdev->revision == 0xc3) { 3064 - max_sclk = 75000; 3065 - max_mclk = 80000; 3066 3013 } 3067 3014 3068 3015 if (rps->vce_active) {
+10 -2
drivers/gpu/drm/rcar-du/rcar_du_kms.c
··· 231 231 struct rcar_du_device *rcdu = dev->dev_private; 232 232 int ret; 233 233 234 - ret = drm_atomic_helper_check(dev, state); 235 - if (ret < 0) 234 + ret = drm_atomic_helper_check_modeset(dev, state); 235 + if (ret) 236 + return ret; 237 + 238 + ret = drm_atomic_normalize_zpos(dev, state); 239 + if (ret) 240 + return ret; 241 + 242 + ret = drm_atomic_helper_check_planes(dev, state); 243 + if (ret) 236 244 return ret; 237 245 238 246 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
+21 -1
drivers/gpu/drm/sti/sti_drv.c
··· 195 195 sti_atomic_complete(private, private->commit.state); 196 196 } 197 197 198 + static int sti_atomic_check(struct drm_device *dev, 199 + struct drm_atomic_state *state) 200 + { 201 + int ret; 202 + 203 + ret = drm_atomic_helper_check_modeset(dev, state); 204 + if (ret) 205 + return ret; 206 + 207 + ret = drm_atomic_normalize_zpos(dev, state); 208 + if (ret) 209 + return ret; 210 + 211 + ret = drm_atomic_helper_check_planes(dev, state); 212 + if (ret) 213 + return ret; 214 + 215 + return ret; 216 + } 217 + 198 218 static int sti_atomic_commit(struct drm_device *drm, 199 219 struct drm_atomic_state *state, bool nonblock) 200 220 { ··· 268 248 static const struct drm_mode_config_funcs sti_mode_config_funcs = { 269 249 .fb_create = drm_fb_cma_create, 270 250 .output_poll_changed = sti_output_poll_changed, 271 - .atomic_check = drm_atomic_helper_check, 251 + .atomic_check = sti_atomic_check, 272 252 .atomic_commit = sti_atomic_commit, 273 253 }; 274 254
+1 -2
drivers/gpu/drm/virtio/virtgpu_display.c
··· 338 338 339 339 drm_atomic_helper_commit_modeset_disables(dev, state); 340 340 drm_atomic_helper_commit_modeset_enables(dev, state); 341 - drm_atomic_helper_commit_planes(dev, state, 342 - DRM_PLANE_COMMIT_ACTIVE_ONLY); 341 + drm_atomic_helper_commit_planes(dev, state, 0); 343 342 344 343 drm_atomic_helper_commit_hw_done(state); 345 344
+1 -1
drivers/gpu/ipu-v3/ipu-image-convert.c
··· 1617 1617 ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, 1618 1618 complete, complete_context); 1619 1619 if (IS_ERR(ctx)) 1620 - return ERR_PTR(PTR_ERR(ctx)); 1620 + return ERR_CAST(ctx); 1621 1621 1622 1622 run = kzalloc(sizeof(*run), GFP_KERNEL); 1623 1623 if (!run) {
+7 -1
include/drm/drm_plane.h
··· 47 47 * @src_h: height of visible portion of plane (in 16.16) 48 48 * @rotation: rotation of the plane 49 49 * @zpos: priority of the given plane on crtc (optional) 50 + * Note that multiple active planes on the same crtc can have an identical 51 + * zpos value. The rule to solving the conflict is to compare the plane 52 + * object IDs; the plane with a higher ID must be stacked on top of a 53 + * plane with a lower ID. 50 54 * @normalized_zpos: normalized value of zpos: unique, range from 0 to N-1 51 - * where N is the number of active planes for given crtc 55 + * where N is the number of active planes for given crtc. Note that 56 + * the driver must call drm_atomic_normalize_zpos() to update this before 57 + * it can be trusted. 52 58 * @src: clipped source coordinates of the plane (in 16.16) 53 59 * @dst: clipped destination coordinates of the plane 54 60 * @visible: visibility of the plane