Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Update headers for CPER support on SRIOV
Update amdgv_sriovmsg.h and mxgpu_nv.h to add new definitions for
CPER support on VFs. PMFW ACA messages are not available on VFs,
and VFs must query CPERs from host.
Signed-off-by: Tony Yi <Tony.Yi@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Tony Yi
and committed by
Alex Deucher
d4c60219
a3199eba
+29
-13
+27
-13
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+27
-13
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
···
97
97
uint32_t pp_one_vf_mode : 1;
98
98
uint32_t reg_indirect_acc : 1;
99
99
uint32_t av1_support : 1;
100
-
uint32_t vcn_rb_decouple : 1;
100
+
uint32_t vcn_rb_decouple : 1;
101
101
uint32_t mes_info_dump_enable : 1;
102
102
uint32_t ras_caps : 1;
103
103
uint32_t ras_telemetry : 1;
104
-
uint32_t reserved : 21;
104
+
uint32_t ras_cper : 1;
105
+
uint32_t reserved : 20;
105
106
} flags;
106
107
uint32_t all;
107
108
};
···
329
328
MB_REQ_MSG_READY_TO_RESET = 201,
330
329
MB_REQ_MSG_RAS_POISON = 202,
331
330
MB_REQ_RAS_ERROR_COUNT = 203,
331
+
MB_REQ_RAS_CPER_DUMP = 204,
332
332
};
333
333
334
334
/* mailbox message send from host to guest */
335
335
enum amd_sriov_mailbox_response_message {
336
-
MB_RES_MSG_CLR_MSG_BUF = 0,
337
-
MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
338
-
MB_RES_MSG_FLR_NOTIFICATION,
339
-
MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
340
-
MB_RES_MSG_SUCCESS,
341
-
MB_RES_MSG_FAIL,
342
-
MB_RES_MSG_QUERY_ALIVE,
343
-
MB_RES_MSG_GPU_INIT_DATA_READY,
344
-
MB_RES_MSG_RAS_ERROR_COUNT_READY = 11,
345
-
346
-
MB_RES_MSG_TEXT_MESSAGE = 255
336
+
MB_RES_MSG_CLR_MSG_BUF = 0,
337
+
MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
338
+
MB_RES_MSG_FLR_NOTIFICATION = 2,
339
+
MB_RES_MSG_FLR_NOTIFICATION_COMPLETION = 3,
340
+
MB_RES_MSG_SUCCESS = 4,
341
+
MB_RES_MSG_FAIL = 5,
342
+
MB_RES_MSG_QUERY_ALIVE = 6,
343
+
MB_RES_MSG_GPU_INIT_DATA_READY = 7,
344
+
MB_RES_MSG_RAS_POISON_READY = 8,
345
+
MB_RES_MSG_PF_SOFT_FLR_NOTIFICATION = 9,
346
+
MB_RES_MSG_GPU_RMA = 10,
347
+
MB_RES_MSG_RAS_ERROR_COUNT_READY = 11,
348
+
MB_REQ_RAS_CPER_DUMP_READY = 14,
349
+
MB_RES_MSG_TEXT_MESSAGE = 255
347
350
};
348
351
349
352
enum amd_sriov_ras_telemetry_gpu_block {
···
391
386
} block[RAS_TELEMETRY_GPU_BLOCK_COUNT];
392
387
};
393
388
389
+
struct amd_sriov_ras_cper_dump {
390
+
uint32_t more;
391
+
uint64_t overflow_count;
392
+
uint64_t count;
393
+
uint64_t wptr;
394
+
uint32_t buf[];
395
+
};
396
+
394
397
struct amdsriov_ras_telemetry {
395
398
struct amd_sriov_ras_telemetry_header header;
396
399
397
400
union {
398
401
struct amd_sriov_ras_telemetry_error_count error_count;
402
+
struct amd_sriov_ras_cper_dump cper_dump;
399
403
} body;
400
404
};
401
405
+2
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
+2
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
···
41
41
IDH_READY_TO_RESET = 201,
42
42
IDH_RAS_POISON = 202,
43
43
IDH_REQ_RAS_ERROR_COUNT = 203,
44
+
IDH_REQ_RAS_CPER_DUMP = 204,
44
45
};
45
46
46
47
enum idh_event {
···
57
56
IDH_PF_SOFT_FLR_NOTIFICATION,
58
57
IDH_RAS_ERROR_DETECTED,
59
58
IDH_RAS_ERROR_COUNT_READY = 11,
59
+
IDH_RAS_CPER_DUMP_READY = 14,
60
60
61
61
IDH_TEXT_MESSAGE = 255,
62
62
};