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clk: qcom: dispcc-sm6350: Add missing parent_map for a clock

If a clk_rcg2 has a parent, it should also have parent_map defined,
otherwise we'll get a NULL pointer dereference when calling clk_set_rate
like the following:

[ 3.388105] Call trace:
[ 3.390664] qcom_find_src_index+0x3c/0x70 (P)
[ 3.395301] qcom_find_src_index+0x1c/0x70 (L)
[ 3.399934] _freq_tbl_determine_rate+0x48/0x100
[ 3.404753] clk_rcg2_determine_rate+0x1c/0x28
[ 3.409387] clk_core_determine_round_nolock+0x58/0xe4
[ 3.421414] clk_core_round_rate_nolock+0x48/0xfc
[ 3.432974] clk_core_round_rate_nolock+0xd0/0xfc
[ 3.444483] clk_core_set_rate_nolock+0x8c/0x300
[ 3.455886] clk_set_rate+0x38/0x14c

Add the parent_map property for the clock where it's missing and also
un-inline the parent_data as well to keep the matching parent_map and
parent_data together.

Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350")
Cc: stable@vger.kernel.org
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241220-sm6350-parent_map-v1-2-64f3d04cb2eb@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Luca Weiss and committed by
Bjorn Andersson d4cdb196 96fe1a7e

+3 -4
+3 -4
drivers/clk/qcom/dispcc-sm6350.c
··· 187 187 .cmd_rcgr = 0x1144, 188 188 .mnd_width = 0, 189 189 .hid_width = 5, 190 + .parent_map = disp_cc_parent_map_6, 190 191 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, 191 192 .clkr.hw.init = &(struct clk_init_data){ 192 193 .name = "disp_cc_mdss_dp_aux_clk_src", 193 - .parent_data = &(const struct clk_parent_data){ 194 - .fw_name = "bi_tcxo", 195 - }, 196 - .num_parents = 1, 194 + .parent_data = disp_cc_parent_data_6, 195 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 197 196 .ops = &clk_rcg2_ops, 198 197 }, 199 198 };