Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs
MIPS: PowerTV: Streamline access to platform device registers
MIPS: Fix vmlinuz build for 32bit-only math shells
MIPS: Add support of LZO-compressed kernels
+392
-309
+1
arch/mips/Kconfig
+1
arch/mips/Kconfig
+7
-2
arch/mips/boot/compressed/Makefile
+7
-2
arch/mips/boot/compressed/Makefile
···
14
14
15
15
# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
16
16
VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
17
-
VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
18
-
VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" ] && printf %x $$(($(VMLINUX_LOAD_ADDRESS) + $(VMLINUX_SIZE))))
17
+
VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo -n $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
18
+
# VMLINUZ_LOAD_ADDRESS = concat "high32 of VMLINUX_LOAD_ADDRESS" and "(low32 of VMLINUX_LOAD_ADDRESS) + VMLINUX_SIZE"
19
+
HIGH32 := $(shell A=$(VMLINUX_LOAD_ADDRESS); [ $${\#A} -gt 10 ] && expr substr "$(VMLINUX_LOAD_ADDRESS)" 3 $$(($${\#A} - 10)))
20
+
LOW32 := $(shell [ -n "$(HIGH32)" ] && A=11 || A=3; expr substr "$(VMLINUX_LOAD_ADDRESS)" $${A} 8)
21
+
VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" -a -n "$(LOW32)" ] && printf "$(HIGH32)%08x" $$(($(VMLINUX_SIZE) + 0x$(LOW32))))
19
22
20
23
# set the default size of the mallocing area for decompressing
21
24
BOOT_HEAP_SIZE := 0x400000
···
44
41
suffix_$(CONFIG_KERNEL_GZIP) = gz
45
42
suffix_$(CONFIG_KERNEL_BZIP2) = bz2
46
43
suffix_$(CONFIG_KERNEL_LZMA) = lzma
44
+
suffix_$(CONFIG_KERNEL_LZO) = lzo
47
45
tool_$(CONFIG_KERNEL_GZIP) = gzip
48
46
tool_$(CONFIG_KERNEL_BZIP2) = bzip2
49
47
tool_$(CONFIG_KERNEL_LZMA) = lzma
48
+
tool_$(CONFIG_KERNEL_LZO) = lzo
50
49
$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
51
50
$(call if_changed,$(tool_y))
52
51
+4
arch/mips/boot/compressed/decompress.c
+4
arch/mips/boot/compressed/decompress.c
+1
arch/mips/include/asm/irq.h
+1
arch/mips/include/asm/irq.h
+90
arch/mips/include/asm/mach-powertv/asic_reg_map.h
+90
arch/mips/include/asm/mach-powertv/asic_reg_map.h
···
1
+
/*
2
+
* asic_reg_map.h
3
+
*
4
+
* A macro-enclosed list of the elements for the register_map structure for
5
+
* use in defining and manipulating the structure.
6
+
*
7
+
* Copyright (C) 2009 Cisco Systems, Inc.
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License as published by
11
+
* the Free Software Foundation; either version 2 of the License, or
12
+
* (at your option) any later version.
13
+
*
14
+
* This program is distributed in the hope that it will be useful,
15
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
16
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17
+
* GNU General Public License for more details.
18
+
*
19
+
* You should have received a copy of the GNU General Public License
20
+
* along with this program; if not, write to the Free Software
21
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22
+
*/
23
+
24
+
REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
25
+
REGISTER_MAP_ELEMENT(eic_cfg_bits)
26
+
REGISTER_MAP_ELEMENT(eic_ready_status)
27
+
REGISTER_MAP_ELEMENT(chipver3)
28
+
REGISTER_MAP_ELEMENT(chipver2)
29
+
REGISTER_MAP_ELEMENT(chipver1)
30
+
REGISTER_MAP_ELEMENT(chipver0)
31
+
REGISTER_MAP_ELEMENT(uart1_intstat)
32
+
REGISTER_MAP_ELEMENT(uart1_inten)
33
+
REGISTER_MAP_ELEMENT(uart1_config1)
34
+
REGISTER_MAP_ELEMENT(uart1_config2)
35
+
REGISTER_MAP_ELEMENT(uart1_divisorhi)
36
+
REGISTER_MAP_ELEMENT(uart1_divisorlo)
37
+
REGISTER_MAP_ELEMENT(uart1_data)
38
+
REGISTER_MAP_ELEMENT(uart1_status)
39
+
REGISTER_MAP_ELEMENT(int_stat_3)
40
+
REGISTER_MAP_ELEMENT(int_stat_2)
41
+
REGISTER_MAP_ELEMENT(int_stat_1)
42
+
REGISTER_MAP_ELEMENT(int_stat_0)
43
+
REGISTER_MAP_ELEMENT(int_config)
44
+
REGISTER_MAP_ELEMENT(int_int_scan)
45
+
REGISTER_MAP_ELEMENT(ien_int_3)
46
+
REGISTER_MAP_ELEMENT(ien_int_2)
47
+
REGISTER_MAP_ELEMENT(ien_int_1)
48
+
REGISTER_MAP_ELEMENT(ien_int_0)
49
+
REGISTER_MAP_ELEMENT(int_level_3_3)
50
+
REGISTER_MAP_ELEMENT(int_level_3_2)
51
+
REGISTER_MAP_ELEMENT(int_level_3_1)
52
+
REGISTER_MAP_ELEMENT(int_level_3_0)
53
+
REGISTER_MAP_ELEMENT(int_level_2_3)
54
+
REGISTER_MAP_ELEMENT(int_level_2_2)
55
+
REGISTER_MAP_ELEMENT(int_level_2_1)
56
+
REGISTER_MAP_ELEMENT(int_level_2_0)
57
+
REGISTER_MAP_ELEMENT(int_level_1_3)
58
+
REGISTER_MAP_ELEMENT(int_level_1_2)
59
+
REGISTER_MAP_ELEMENT(int_level_1_1)
60
+
REGISTER_MAP_ELEMENT(int_level_1_0)
61
+
REGISTER_MAP_ELEMENT(int_level_0_3)
62
+
REGISTER_MAP_ELEMENT(int_level_0_2)
63
+
REGISTER_MAP_ELEMENT(int_level_0_1)
64
+
REGISTER_MAP_ELEMENT(int_level_0_0)
65
+
REGISTER_MAP_ELEMENT(int_docsis_en)
66
+
REGISTER_MAP_ELEMENT(mips_pll_setup)
67
+
REGISTER_MAP_ELEMENT(usb_fs)
68
+
REGISTER_MAP_ELEMENT(test_bus)
69
+
REGISTER_MAP_ELEMENT(crt_spare)
70
+
REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
71
+
REGISTER_MAP_ELEMENT(usb2_strap)
72
+
REGISTER_MAP_ELEMENT(ehci_hcapbase)
73
+
REGISTER_MAP_ELEMENT(ohci_hc_revision)
74
+
REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
75
+
REGISTER_MAP_ELEMENT(usb2_control)
76
+
REGISTER_MAP_ELEMENT(usb2_stbus_obc)
77
+
REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
78
+
REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
79
+
REGISTER_MAP_ELEMENT(pcie_regs)
80
+
REGISTER_MAP_ELEMENT(tim_ch)
81
+
REGISTER_MAP_ELEMENT(tim_cl)
82
+
REGISTER_MAP_ELEMENT(gpio_dout)
83
+
REGISTER_MAP_ELEMENT(gpio_din)
84
+
REGISTER_MAP_ELEMENT(gpio_dir)
85
+
REGISTER_MAP_ELEMENT(watchdog)
86
+
REGISTER_MAP_ELEMENT(front_panel)
87
+
REGISTER_MAP_ELEMENT(misc_clk_ctl1)
88
+
REGISTER_MAP_ELEMENT(misc_clk_ctl2)
89
+
REGISTER_MAP_ELEMENT(crt_ext_ctl)
90
+
REGISTER_MAP_ELEMENT(register_maps)
+52
-85
arch/mips/include/asm/mach-powertv/asic_regs.h
+52
-85
arch/mips/include/asm/mach-powertv/asic_regs.h
···
35
35
#define CRONUS_11 0x0B4C1C21
36
36
#define CRONUSLITE_10 0x0B4C1C40
37
37
38
-
#define NAND_FLASH_BASE 0x03000000
39
-
#define ZEUS_IO_BASE 0x09000000
38
+
#define NAND_FLASH_BASE 0x03000000
40
39
#define CALLIOPE_IO_BASE 0x08000000
41
-
#define CRONUS_IO_BASE 0x09000000
42
-
#define ASIC_IO_SIZE 0x01000000
40
+
#define CRONUS_IO_BASE 0x09000000
41
+
#define ZEUS_IO_BASE 0x09000000
42
+
43
+
#define ASIC_IO_SIZE 0x01000000
43
44
44
45
/* Definitions for backward compatibility */
45
46
#define UART1_INTSTAT uart1_intstat
···
53
52
#define UART1_STATUS uart1_status
54
53
55
54
/* ASIC register enumeration */
56
-
struct register_map {
57
-
u32 eic_slow0_strt_add;
58
-
u32 eic_cfg_bits;
59
-
u32 eic_ready_status;
60
-
61
-
u32 chipver3;
62
-
u32 chipver2;
63
-
u32 chipver1;
64
-
u32 chipver0;
65
-
66
-
u32 uart1_intstat;
67
-
u32 uart1_inten;
68
-
u32 uart1_config1;
69
-
u32 uart1_config2;
70
-
u32 uart1_divisorhi;
71
-
u32 uart1_divisorlo;
72
-
u32 uart1_data;
73
-
u32 uart1_status;
74
-
75
-
u32 int_stat_3;
76
-
u32 int_stat_2;
77
-
u32 int_stat_1;
78
-
u32 int_stat_0;
79
-
u32 int_config;
80
-
u32 int_int_scan;
81
-
u32 ien_int_3;
82
-
u32 ien_int_2;
83
-
u32 ien_int_1;
84
-
u32 ien_int_0;
85
-
u32 int_level_3_3;
86
-
u32 int_level_3_2;
87
-
u32 int_level_3_1;
88
-
u32 int_level_3_0;
89
-
u32 int_level_2_3;
90
-
u32 int_level_2_2;
91
-
u32 int_level_2_1;
92
-
u32 int_level_2_0;
93
-
u32 int_level_1_3;
94
-
u32 int_level_1_2;
95
-
u32 int_level_1_1;
96
-
u32 int_level_1_0;
97
-
u32 int_level_0_3;
98
-
u32 int_level_0_2;
99
-
u32 int_level_0_1;
100
-
u32 int_level_0_0;
101
-
u32 int_docsis_en;
102
-
103
-
u32 mips_pll_setup;
104
-
u32 usb_fs;
105
-
u32 test_bus;
106
-
u32 crt_spare;
107
-
u32 usb2_ohci_int_mask;
108
-
u32 usb2_strap;
109
-
u32 ehci_hcapbase;
110
-
u32 ohci_hc_revision;
111
-
u32 bcm1_bs_lmi_steer;
112
-
u32 usb2_control;
113
-
u32 usb2_stbus_obc;
114
-
u32 usb2_stbus_mess_size;
115
-
u32 usb2_stbus_chunk_size;
116
-
117
-
u32 pcie_regs;
118
-
u32 tim_ch;
119
-
u32 tim_cl;
120
-
u32 gpio_dout;
121
-
u32 gpio_din;
122
-
u32 gpio_dir;
123
-
u32 watchdog;
124
-
u32 front_panel;
125
-
126
-
u32 register_maps;
55
+
union register_map_entry {
56
+
unsigned long phys;
57
+
u32 *virt;
127
58
};
128
59
129
-
extern enum asic_type asic;
130
-
extern const struct register_map *register_map;
131
-
extern unsigned long asic_phy_base; /* Physical address of ASIC */
132
-
extern unsigned long asic_base; /* Virtual address of ASIC */
60
+
#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
61
+
struct register_map {
62
+
#include <asm/mach-powertv/asic_reg_map.h>
63
+
};
64
+
#undef REGISTER_MAP_ELEMENT
65
+
66
+
/**
67
+
* register_map_offset_phys - add an offset to the physical address
68
+
* @map: Pointer to the &struct register_map
69
+
* @offset: Value to add
70
+
*
71
+
* Only adds the base to non-zero physical addresses
72
+
*/
73
+
static inline void register_map_offset_phys(struct register_map *map,
74
+
unsigned long offset)
75
+
{
76
+
#define REGISTER_MAP_ELEMENT(x) do { \
77
+
if (map->x.phys != 0) \
78
+
map->x.phys += offset; \
79
+
} while (false);
80
+
81
+
#include <asm/mach-powertv/asic_reg_map.h>
82
+
#undef REGISTER_MAP_ELEMENT
83
+
}
84
+
85
+
/**
86
+
* register_map_virtualize - Convert ®ister_map to virtual addresses
87
+
* @map: Pointer to ®ister_map to virtualize
88
+
*/
89
+
static inline void register_map_virtualize(struct register_map *map)
90
+
{
91
+
#define REGISTER_MAP_ELEMENT(x) do { \
92
+
map->x.virt = (!map->x.phys) ? NULL : \
93
+
UNCAC_ADDR(phys_to_virt(map->x.phys)); \
94
+
} while (false);
95
+
96
+
#include <asm/mach-powertv/asic_reg_map.h>
97
+
#undef REGISTER_MAP_ELEMENT
98
+
}
99
+
100
+
extern struct register_map _asic_register_map;
133
101
134
102
/*
135
103
* Macros to interface to registers through their ioremapped address
136
-
* asic_reg_offset Returns the offset of a given register from the start
137
-
* of the ASIC address space
138
104
* asic_reg_phys_addr Returns the physical address of the given register
139
105
* asic_reg_addr Returns the iomapped virtual address of the given
140
106
* register.
141
107
*/
142
-
#define asic_reg_offset(x) (register_map->x)
143
-
#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x))
144
-
#define asic_reg_addr(x) \
145
-
((unsigned int *) (asic_base + asic_reg_offset(x)))
108
+
#define asic_reg_addr(x) (_asic_register_map.x.virt)
109
+
#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
110
+
(unsigned long) asic_reg_addr(x))))
146
111
147
112
/*
148
113
* The asic_reg macro is gone. It should be replaced by either asic_read or
+12
arch/mips/include/asm/mipsregs.h
+12
arch/mips/include/asm/mipsregs.h
···
406
406
#define ST0_XX 0x80000000 /* MIPS IV naming */
407
407
408
408
/*
409
+
* Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
410
+
*
411
+
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
412
+
*/
413
+
#define INTCTLB_IPPCI 26
414
+
#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
415
+
#define INTCTLB_IPTI 29
416
+
#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
417
+
418
+
/*
409
419
* Bitfields and bit numbers in the coprocessor 0 cause register.
410
420
*
411
421
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
···
444
434
#define CAUSEF_IV (_ULCAST_(1) << 23)
445
435
#define CAUSEB_CE 28
446
436
#define CAUSEF_CE (_ULCAST_(3) << 28)
437
+
#define CAUSEB_TI 30
438
+
#define CAUSEF_TI (_ULCAST_(1) << 30)
447
439
#define CAUSEB_BD 31
448
440
#define CAUSEF_BD (_ULCAST_(1) << 31)
449
441
+1
-1
arch/mips/kernel/cevt-r4k.c
+1
-1
arch/mips/kernel/cevt-r4k.c
+4
-2
arch/mips/kernel/traps.c
+4
-2
arch/mips/kernel/traps.c
···
1403
1403
* Timer interrupt
1404
1404
*/
1405
1405
int cp0_compare_irq;
1406
+
int cp0_compare_irq_shift;
1406
1407
1407
1408
/*
1408
1409
* Performance counter IRQ or -1 if shared with timer
···
1494
1493
* o read IntCtl.IPPCI to determine the performance counter interrupt
1495
1494
*/
1496
1495
if (cpu_has_mips_r2) {
1497
-
cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1498
-
cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1496
+
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1497
+
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1498
+
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1499
1499
if (cp0_perfcount_irq == cp0_compare_irq)
1500
1500
cp0_perfcount_irq = -1;
1501
1501
} else {
+67
-64
arch/mips/powertv/asic/asic-calliope.c
+67
-64
arch/mips/powertv/asic/asic-calliope.c
···
23
23
* Description: Defines the platform resources for the SA settop.
24
24
*/
25
25
26
+
#include <linux/init.h>
26
27
#include <asm/mach-powertv/asic.h>
27
28
28
-
const struct register_map calliope_register_map = {
29
-
.eic_slow0_strt_add = 0x800000,
30
-
.eic_cfg_bits = 0x800038,
31
-
.eic_ready_status = 0x80004c,
29
+
#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
32
30
33
-
.chipver3 = 0xA00800,
34
-
.chipver2 = 0xA00804,
35
-
.chipver1 = 0xA00808,
36
-
.chipver0 = 0xA0080c,
31
+
const struct register_map calliope_register_map __initdata = {
32
+
.eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
33
+
.eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
34
+
.eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
35
+
36
+
.chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
37
+
.chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
38
+
.chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
39
+
.chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
37
40
38
41
/* The registers of IRBlaster */
39
-
.uart1_intstat = 0xA01800,
40
-
.uart1_inten = 0xA01804,
41
-
.uart1_config1 = 0xA01808,
42
-
.uart1_config2 = 0xA0180C,
43
-
.uart1_divisorhi = 0xA01810,
44
-
.uart1_divisorlo = 0xA01814,
45
-
.uart1_data = 0xA01818,
46
-
.uart1_status = 0xA0181C,
42
+
.uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
43
+
.uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
44
+
.uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
45
+
.uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
46
+
.uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
47
+
.uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
48
+
.uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
49
+
.uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
47
50
48
-
.int_stat_3 = 0xA02800,
49
-
.int_stat_2 = 0xA02804,
50
-
.int_stat_1 = 0xA02808,
51
-
.int_stat_0 = 0xA0280c,
52
-
.int_config = 0xA02810,
53
-
.int_int_scan = 0xA02818,
54
-
.ien_int_3 = 0xA02830,
55
-
.ien_int_2 = 0xA02834,
56
-
.ien_int_1 = 0xA02838,
57
-
.ien_int_0 = 0xA0283c,
58
-
.int_level_3_3 = 0xA02880,
59
-
.int_level_3_2 = 0xA02884,
60
-
.int_level_3_1 = 0xA02888,
61
-
.int_level_3_0 = 0xA0288c,
62
-
.int_level_2_3 = 0xA02890,
63
-
.int_level_2_2 = 0xA02894,
64
-
.int_level_2_1 = 0xA02898,
65
-
.int_level_2_0 = 0xA0289c,
66
-
.int_level_1_3 = 0xA028a0,
67
-
.int_level_1_2 = 0xA028a4,
68
-
.int_level_1_1 = 0xA028a8,
69
-
.int_level_1_0 = 0xA028ac,
70
-
.int_level_0_3 = 0xA028b0,
71
-
.int_level_0_2 = 0xA028b4,
72
-
.int_level_0_1 = 0xA028b8,
73
-
.int_level_0_0 = 0xA028bc,
74
-
.int_docsis_en = 0xA028F4,
51
+
.int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
52
+
.int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
53
+
.int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
54
+
.int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
55
+
.int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
56
+
.int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
57
+
.ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
58
+
.ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
59
+
.ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
60
+
.ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
61
+
.int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
62
+
.int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
63
+
.int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
64
+
.int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
65
+
.int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
66
+
.int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
67
+
.int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
68
+
.int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
69
+
.int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
70
+
.int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
71
+
.int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
72
+
.int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
73
+
.int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
74
+
.int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
75
+
.int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
76
+
.int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
77
+
.int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
75
78
76
-
.mips_pll_setup = 0x980000,
77
-
.usb_fs = 0x980030, /* -default 72800028- */
78
-
.test_bus = 0x9800CC,
79
-
.crt_spare = 0x9800d4,
80
-
.usb2_ohci_int_mask = 0x9A000c,
81
-
.usb2_strap = 0x9A0014,
82
-
.ehci_hcapbase = 0x9BFE00,
83
-
.ohci_hc_revision = 0x9BFC00,
84
-
.bcm1_bs_lmi_steer = 0x9E0004,
85
-
.usb2_control = 0x9E0054,
86
-
.usb2_stbus_obc = 0x9BFF00,
87
-
.usb2_stbus_mess_size = 0x9BFF04,
88
-
.usb2_stbus_chunk_size = 0x9BFF08,
79
+
.mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
80
+
.usb_fs = {.phys = CALLIOPE_ADDR(0x980030)},
81
+
.test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
82
+
.crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
83
+
.usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
84
+
.usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
85
+
.ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
86
+
.ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
87
+
.bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
88
+
.usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
89
+
.usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
90
+
.usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
91
+
.usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
89
92
90
-
.pcie_regs = 0x000000, /* -doesn't exist- */
91
-
.tim_ch = 0xA02C10,
92
-
.tim_cl = 0xA02C14,
93
-
.gpio_dout = 0xA02c20,
94
-
.gpio_din = 0xA02c24,
95
-
.gpio_dir = 0xA02c2C,
96
-
.watchdog = 0xA02c30,
97
-
.front_panel = 0x000000, /* -not used- */
93
+
.pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
94
+
.tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
95
+
.tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
96
+
.gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
97
+
.gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
98
+
.gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
99
+
.watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
100
+
.front_panel = {.phys = 0x000000}, /* -not used- */
98
101
};
+67
-64
arch/mips/powertv/asic/asic-cronus.c
+67
-64
arch/mips/powertv/asic/asic-cronus.c
···
23
23
* Description: Defines the platform resources for the SA settop.
24
24
*/
25
25
26
+
#include <linux/init.h>
26
27
#include <asm/mach-powertv/asic.h>
27
28
28
-
const struct register_map cronus_register_map = {
29
-
.eic_slow0_strt_add = 0x000000,
30
-
.eic_cfg_bits = 0x000038,
31
-
.eic_ready_status = 0x00004C,
29
+
#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x))
32
30
33
-
.chipver3 = 0x2A0800,
34
-
.chipver2 = 0x2A0804,
35
-
.chipver1 = 0x2A0808,
36
-
.chipver0 = 0x2A080C,
31
+
const struct register_map cronus_register_map __initdata = {
32
+
.eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
33
+
.eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
34
+
.eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
35
+
36
+
.chipver3 = {.phys = CRONUS_ADDR(0x2A0800)},
37
+
.chipver2 = {.phys = CRONUS_ADDR(0x2A0804)},
38
+
.chipver1 = {.phys = CRONUS_ADDR(0x2A0808)},
39
+
.chipver0 = {.phys = CRONUS_ADDR(0x2A080C)},
37
40
38
41
/* The registers of IRBlaster */
39
-
.uart1_intstat = 0x2A1800,
40
-
.uart1_inten = 0x2A1804,
41
-
.uart1_config1 = 0x2A1808,
42
-
.uart1_config2 = 0x2A180C,
43
-
.uart1_divisorhi = 0x2A1810,
44
-
.uart1_divisorlo = 0x2A1814,
45
-
.uart1_data = 0x2A1818,
46
-
.uart1_status = 0x2A181C,
42
+
.uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)},
43
+
.uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)},
44
+
.uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)},
45
+
.uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)},
46
+
.uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)},
47
+
.uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)},
48
+
.uart1_data = {.phys = CRONUS_ADDR(0x2A1818)},
49
+
.uart1_status = {.phys = CRONUS_ADDR(0x2A181C)},
47
50
48
-
.int_stat_3 = 0x2A2800,
49
-
.int_stat_2 = 0x2A2804,
50
-
.int_stat_1 = 0x2A2808,
51
-
.int_stat_0 = 0x2A280C,
52
-
.int_config = 0x2A2810,
53
-
.int_int_scan = 0x2A2818,
54
-
.ien_int_3 = 0x2A2830,
55
-
.ien_int_2 = 0x2A2834,
56
-
.ien_int_1 = 0x2A2838,
57
-
.ien_int_0 = 0x2A283C,
58
-
.int_level_3_3 = 0x2A2880,
59
-
.int_level_3_2 = 0x2A2884,
60
-
.int_level_3_1 = 0x2A2888,
61
-
.int_level_3_0 = 0x2A288C,
62
-
.int_level_2_3 = 0x2A2890,
63
-
.int_level_2_2 = 0x2A2894,
64
-
.int_level_2_1 = 0x2A2898,
65
-
.int_level_2_0 = 0x2A289C,
66
-
.int_level_1_3 = 0x2A28A0,
67
-
.int_level_1_2 = 0x2A28A4,
68
-
.int_level_1_1 = 0x2A28A8,
69
-
.int_level_1_0 = 0x2A28AC,
70
-
.int_level_0_3 = 0x2A28B0,
71
-
.int_level_0_2 = 0x2A28B4,
72
-
.int_level_0_1 = 0x2A28B8,
73
-
.int_level_0_0 = 0x2A28BC,
74
-
.int_docsis_en = 0x2A28F4,
51
+
.int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)},
52
+
.int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)},
53
+
.int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)},
54
+
.int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)},
55
+
.int_config = {.phys = CRONUS_ADDR(0x2A2810)},
56
+
.int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)},
57
+
.ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)},
58
+
.ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)},
59
+
.ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)},
60
+
.ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)},
61
+
.int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)},
62
+
.int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)},
63
+
.int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)},
64
+
.int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)},
65
+
.int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)},
66
+
.int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)},
67
+
.int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)},
68
+
.int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)},
69
+
.int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)},
70
+
.int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)},
71
+
.int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)},
72
+
.int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)},
73
+
.int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)},
74
+
.int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)},
75
+
.int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)},
76
+
.int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)},
77
+
.int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
75
78
76
-
.mips_pll_setup = 0x1C0000,
77
-
.usb_fs = 0x1C0018,
78
-
.test_bus = 0x1C00CC,
79
-
.crt_spare = 0x1c00d4,
80
-
.usb2_ohci_int_mask = 0x20000C,
81
-
.usb2_strap = 0x200014,
82
-
.ehci_hcapbase = 0x21FE00,
83
-
.ohci_hc_revision = 0x1E0000,
84
-
.bcm1_bs_lmi_steer = 0x2E0008,
85
-
.usb2_control = 0x2E004C,
86
-
.usb2_stbus_obc = 0x21FF00,
87
-
.usb2_stbus_mess_size = 0x21FF04,
88
-
.usb2_stbus_chunk_size = 0x21FF08,
79
+
.mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
80
+
.usb_fs = {.phys = CRONUS_ADDR(0x1C0018)},
81
+
.test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
82
+
.crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
83
+
.usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
84
+
.usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
85
+
.ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
86
+
.ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)},
87
+
.bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
88
+
.usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
89
+
.usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
90
+
.usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)},
91
+
.usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)},
89
92
90
-
.pcie_regs = 0x220000,
91
-
.tim_ch = 0x2A2C10,
92
-
.tim_cl = 0x2A2C14,
93
-
.gpio_dout = 0x2A2C20,
94
-
.gpio_din = 0x2A2C24,
95
-
.gpio_dir = 0x2A2C2C,
96
-
.watchdog = 0x2A2C30,
97
-
.front_panel = 0x2A3800,
93
+
.pcie_regs = {.phys = CRONUS_ADDR(0x220000)},
94
+
.tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)},
95
+
.tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)},
96
+
.gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)},
97
+
.gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)},
98
+
.gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)},
99
+
.watchdog = {.phys = CRONUS_ADDR(0x2A2C30)},
100
+
.front_panel = {.phys = CRONUS_ADDR(0x2A3800)},
98
101
};
+67
-64
arch/mips/powertv/asic/asic-zeus.c
+67
-64
arch/mips/powertv/asic/asic-zeus.c
···
23
23
* Description: Defines the platform resources for the SA settop.
24
24
*/
25
25
26
+
#include <linux/init.h>
26
27
#include <asm/mach-powertv/asic.h>
27
28
28
-
const struct register_map zeus_register_map = {
29
-
.eic_slow0_strt_add = 0x000000,
30
-
.eic_cfg_bits = 0x000038,
31
-
.eic_ready_status = 0x00004c,
29
+
#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x))
32
30
33
-
.chipver3 = 0x280800,
34
-
.chipver2 = 0x280804,
35
-
.chipver1 = 0x280808,
36
-
.chipver0 = 0x28080c,
31
+
const struct register_map zeus_register_map __initdata = {
32
+
.eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)},
33
+
.eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)},
34
+
.eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
35
+
36
+
.chipver3 = {.phys = ZEUS_ADDR(0x280800)},
37
+
.chipver2 = {.phys = ZEUS_ADDR(0x280804)},
38
+
.chipver1 = {.phys = ZEUS_ADDR(0x280808)},
39
+
.chipver0 = {.phys = ZEUS_ADDR(0x28080c)},
37
40
38
41
/* The registers of IRBlaster */
39
-
.uart1_intstat = 0x281800,
40
-
.uart1_inten = 0x281804,
41
-
.uart1_config1 = 0x281808,
42
-
.uart1_config2 = 0x28180C,
43
-
.uart1_divisorhi = 0x281810,
44
-
.uart1_divisorlo = 0x281814,
45
-
.uart1_data = 0x281818,
46
-
.uart1_status = 0x28181C,
42
+
.uart1_intstat = {.phys = ZEUS_ADDR(0x281800)},
43
+
.uart1_inten = {.phys = ZEUS_ADDR(0x281804)},
44
+
.uart1_config1 = {.phys = ZEUS_ADDR(0x281808)},
45
+
.uart1_config2 = {.phys = ZEUS_ADDR(0x28180C)},
46
+
.uart1_divisorhi = {.phys = ZEUS_ADDR(0x281810)},
47
+
.uart1_divisorlo = {.phys = ZEUS_ADDR(0x281814)},
48
+
.uart1_data = {.phys = ZEUS_ADDR(0x281818)},
49
+
.uart1_status = {.phys = ZEUS_ADDR(0x28181C)},
47
50
48
-
.int_stat_3 = 0x282800,
49
-
.int_stat_2 = 0x282804,
50
-
.int_stat_1 = 0x282808,
51
-
.int_stat_0 = 0x28280c,
52
-
.int_config = 0x282810,
53
-
.int_int_scan = 0x282818,
54
-
.ien_int_3 = 0x282830,
55
-
.ien_int_2 = 0x282834,
56
-
.ien_int_1 = 0x282838,
57
-
.ien_int_0 = 0x28283c,
58
-
.int_level_3_3 = 0x282880,
59
-
.int_level_3_2 = 0x282884,
60
-
.int_level_3_1 = 0x282888,
61
-
.int_level_3_0 = 0x28288c,
62
-
.int_level_2_3 = 0x282890,
63
-
.int_level_2_2 = 0x282894,
64
-
.int_level_2_1 = 0x282898,
65
-
.int_level_2_0 = 0x28289c,
66
-
.int_level_1_3 = 0x2828a0,
67
-
.int_level_1_2 = 0x2828a4,
68
-
.int_level_1_1 = 0x2828a8,
69
-
.int_level_1_0 = 0x2828ac,
70
-
.int_level_0_3 = 0x2828b0,
71
-
.int_level_0_2 = 0x2828b4,
72
-
.int_level_0_1 = 0x2828b8,
73
-
.int_level_0_0 = 0x2828bc,
74
-
.int_docsis_en = 0x2828F4,
51
+
.int_stat_3 = {.phys = ZEUS_ADDR(0x282800)},
52
+
.int_stat_2 = {.phys = ZEUS_ADDR(0x282804)},
53
+
.int_stat_1 = {.phys = ZEUS_ADDR(0x282808)},
54
+
.int_stat_0 = {.phys = ZEUS_ADDR(0x28280c)},
55
+
.int_config = {.phys = ZEUS_ADDR(0x282810)},
56
+
.int_int_scan = {.phys = ZEUS_ADDR(0x282818)},
57
+
.ien_int_3 = {.phys = ZEUS_ADDR(0x282830)},
58
+
.ien_int_2 = {.phys = ZEUS_ADDR(0x282834)},
59
+
.ien_int_1 = {.phys = ZEUS_ADDR(0x282838)},
60
+
.ien_int_0 = {.phys = ZEUS_ADDR(0x28283c)},
61
+
.int_level_3_3 = {.phys = ZEUS_ADDR(0x282880)},
62
+
.int_level_3_2 = {.phys = ZEUS_ADDR(0x282884)},
63
+
.int_level_3_1 = {.phys = ZEUS_ADDR(0x282888)},
64
+
.int_level_3_0 = {.phys = ZEUS_ADDR(0x28288c)},
65
+
.int_level_2_3 = {.phys = ZEUS_ADDR(0x282890)},
66
+
.int_level_2_2 = {.phys = ZEUS_ADDR(0x282894)},
67
+
.int_level_2_1 = {.phys = ZEUS_ADDR(0x282898)},
68
+
.int_level_2_0 = {.phys = ZEUS_ADDR(0x28289c)},
69
+
.int_level_1_3 = {.phys = ZEUS_ADDR(0x2828a0)},
70
+
.int_level_1_2 = {.phys = ZEUS_ADDR(0x2828a4)},
71
+
.int_level_1_1 = {.phys = ZEUS_ADDR(0x2828a8)},
72
+
.int_level_1_0 = {.phys = ZEUS_ADDR(0x2828ac)},
73
+
.int_level_0_3 = {.phys = ZEUS_ADDR(0x2828b0)},
74
+
.int_level_0_2 = {.phys = ZEUS_ADDR(0x2828b4)},
75
+
.int_level_0_1 = {.phys = ZEUS_ADDR(0x2828b8)},
76
+
.int_level_0_0 = {.phys = ZEUS_ADDR(0x2828bc)},
77
+
.int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
75
78
76
-
.mips_pll_setup = 0x1a0000,
77
-
.usb_fs = 0x1a0018,
78
-
.test_bus = 0x1a0238,
79
-
.crt_spare = 0x1a0090,
80
-
.usb2_ohci_int_mask = 0x1e000c,
81
-
.usb2_strap = 0x1e0014,
82
-
.ehci_hcapbase = 0x1FFE00,
83
-
.ohci_hc_revision = 0x1FFC00,
84
-
.bcm1_bs_lmi_steer = 0x2C0008,
85
-
.usb2_control = 0x2c01a0,
86
-
.usb2_stbus_obc = 0x1FFF00,
87
-
.usb2_stbus_mess_size = 0x1FFF04,
88
-
.usb2_stbus_chunk_size = 0x1FFF08,
79
+
.mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
80
+
.usb_fs = {.phys = ZEUS_ADDR(0x1a0018)},
81
+
.test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
82
+
.crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
83
+
.usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
84
+
.usb2_strap = {.phys = ZEUS_ADDR(0x1e0014)},
85
+
.ehci_hcapbase = {.phys = ZEUS_ADDR(0x1FFE00)},
86
+
.ohci_hc_revision = {.phys = ZEUS_ADDR(0x1FFC00)},
87
+
.bcm1_bs_lmi_steer = {.phys = ZEUS_ADDR(0x2C0008)},
88
+
.usb2_control = {.phys = ZEUS_ADDR(0x2c01a0)},
89
+
.usb2_stbus_obc = {.phys = ZEUS_ADDR(0x1FFF00)},
90
+
.usb2_stbus_mess_size = {.phys = ZEUS_ADDR(0x1FFF04)},
91
+
.usb2_stbus_chunk_size = {.phys = ZEUS_ADDR(0x1FFF08)},
89
92
90
-
.pcie_regs = 0x200000,
91
-
.tim_ch = 0x282C10,
92
-
.tim_cl = 0x282C14,
93
-
.gpio_dout = 0x282c20,
94
-
.gpio_din = 0x282c24,
95
-
.gpio_dir = 0x282c2C,
96
-
.watchdog = 0x282c30,
97
-
.front_panel = 0x283800,
93
+
.pcie_regs = {.phys = ZEUS_ADDR(0x200000)},
94
+
.tim_ch = {.phys = ZEUS_ADDR(0x282C10)},
95
+
.tim_cl = {.phys = ZEUS_ADDR(0x282C14)},
96
+
.gpio_dout = {.phys = ZEUS_ADDR(0x282c20)},
97
+
.gpio_din = {.phys = ZEUS_ADDR(0x282c24)},
98
+
.gpio_dir = {.phys = ZEUS_ADDR(0x282c2C)},
99
+
.watchdog = {.phys = ZEUS_ADDR(0x282c30)},
100
+
.front_panel = {.phys = ZEUS_ADDR(0x283800)},
98
101
};
+19
-27
arch/mips/powertv/asic/asic_devices.c
+19
-27
arch/mips/powertv/asic/asic_devices.c
···
67
67
68
68
unsigned int platform_features;
69
69
unsigned int platform_family;
70
-
const struct register_map *register_map;
71
-
EXPORT_SYMBOL(register_map); /* Exported for testing */
70
+
struct register_map _asic_register_map;
71
+
EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */
72
72
unsigned long asic_phy_base;
73
73
unsigned long asic_base;
74
74
EXPORT_SYMBOL(asic_base); /* Exported for testing */
···
418
418
{
419
419
}
420
420
421
+
static void __init set_register_map(unsigned long phys_base,
422
+
const struct register_map *map)
423
+
{
424
+
asic_phy_base = phys_base;
425
+
_asic_register_map = *map;
426
+
register_map_virtualize(&_asic_register_map);
427
+
asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE);
428
+
}
429
+
421
430
/**
422
431
* configure_platform - configuration based on platform type.
423
432
*/
···
440
431
case FAMILY_1500VZF:
441
432
platform_features = FFS_CAPABLE;
442
433
asic = ASIC_CALLIOPE;
443
-
asic_phy_base = CALLIOPE_IO_BASE;
444
-
register_map = &calliope_register_map;
445
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
446
-
ASIC_IO_SIZE);
434
+
set_register_map(CALLIOPE_IO_BASE, &calliope_register_map);
447
435
448
436
if (platform_family == FAMILY_1500VZE) {
449
437
gp_resources = non_dvr_vze_calliope_resources;
···
461
455
platform_features = FFS_CAPABLE | PCIE_CAPABLE |
462
456
DISPLAY_CAPABLE;
463
457
asic = ASIC_ZEUS;
464
-
asic_phy_base = ZEUS_IO_BASE;
465
-
register_map = &zeus_register_map;
466
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
467
-
ASIC_IO_SIZE);
458
+
set_register_map(ZEUS_IO_BASE, &zeus_register_map);
468
459
gp_resources = non_dvr_zeus_resources;
469
460
470
461
pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
···
474
471
/* The settop has PCIE but it isn't used, so don't advertise
475
472
* it*/
476
473
platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
477
-
asic_phy_base = CRONUS_IO_BASE; /* same as Cronus */
478
-
register_map = &cronus_register_map; /* same as Cronus */
479
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
480
-
ASIC_IO_SIZE);
481
-
gp_resources = non_dvr_cronuslite_resources;
482
474
483
475
/* ASIC version will determine if this is a real CronusLite or
484
476
* Castrati(Cronus) */
···
487
489
else
488
490
asic = ASIC_CRONUSLITE;
489
491
492
+
/* Cronus and Cronus Lite have the same register map */
493
+
set_register_map(CRONUS_IO_BASE, &cronus_register_map);
494
+
gp_resources = non_dvr_cronuslite_resources;
490
495
pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
491
496
"chipversion=0x%08X\n",
492
497
(asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
···
499
498
case FAMILY_4600VZA:
500
499
platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
501
500
asic = ASIC_CRONUS;
502
-
asic_phy_base = CRONUS_IO_BASE;
503
-
register_map = &cronus_register_map;
504
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
505
-
ASIC_IO_SIZE);
501
+
set_register_map(CRONUS_IO_BASE, &cronus_register_map);
506
502
gp_resources = non_dvr_cronus_resources;
507
503
508
504
pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
···
510
512
platform_features = DVR_CAPABLE | PCIE_CAPABLE |
511
513
DISPLAY_CAPABLE;
512
514
asic = ASIC_ZEUS;
513
-
asic_phy_base = ZEUS_IO_BASE;
514
-
register_map = &zeus_register_map;
515
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
516
-
ASIC_IO_SIZE);
515
+
set_register_map(ZEUS_IO_BASE, &zeus_register_map);
517
516
gp_resources = dvr_zeus_resources;
518
517
519
518
pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
···
521
526
platform_features = DVR_CAPABLE | PCIE_CAPABLE |
522
527
DISPLAY_CAPABLE;
523
528
asic = ASIC_CRONUS;
524
-
asic_phy_base = CRONUS_IO_BASE;
525
-
register_map = &cronus_register_map;
526
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
527
-
ASIC_IO_SIZE);
529
+
set_register_map(CRONUS_IO_BASE, &cronus_register_map);
528
530
gp_resources = dvr_cronus_resources;
529
531
530
532
pr_info("Platform: 8600/Vz Class B - CRONUS, "