clk: qcom: clk-alpha-pll: Add HUAYRA_2290 support

Commit 134b55b7e19f ("clk: qcom: support Huayra type Alpha PLL")
introduced an entry to the alpha offsets array, but diving into QCM2290
downstream and some documentation, it turned out that the name Huayra
apparently has been used quite liberally across many chips, even with
noticeably different hardware.

Introduce another set of offsets and a new configure function for the
Huayra PLL found on QCM2290. This is required e.g. for the consumers
of GPUCC_PLL0 to properly start.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-2-4bc0c19da4af@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Konrad Dybcio and committed by

Bjorn Andersson 2 years ago d4d74e4b ea5594aa

+50

2 changed files

expand all

drivers

clk

qcom

clk-alpha-pll.c

clk-alpha-pll.h

+47

drivers/clk/qcom/clk-alpha-pll.c

··· 93 93 [PLL_OFF_TEST_CTL] = 0x30, 94 94 [PLL_OFF_TEST_CTL_U] = 0x34, 95 95 }, 96 + [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { 97 + [PLL_OFF_L_VAL] = 0x04, 98 + [PLL_OFF_ALPHA_VAL] = 0x08, 99 + [PLL_OFF_USER_CTL] = 0x0c, 100 + [PLL_OFF_CONFIG_CTL] = 0x10, 101 + [PLL_OFF_CONFIG_CTL_U] = 0x14, 102 + [PLL_OFF_CONFIG_CTL_U1] = 0x18, 103 + [PLL_OFF_TEST_CTL] = 0x1c, 104 + [PLL_OFF_TEST_CTL_U] = 0x20, 105 + [PLL_OFF_TEST_CTL_U1] = 0x24, 106 + [PLL_OFF_OPMODE] = 0x28, 107 + [PLL_OFF_STATUS] = 0x38, 108 + }, 96 109 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 97 110 [PLL_OFF_L_VAL] = 0x04, 98 111 [PLL_OFF_ALPHA_VAL] = 0x08, ··· 800 787 801 788 return clamp(rate, min_freq, max_freq); 802 789 } 790 + 791 + void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 792 + const struct alpha_pll_config *config) 793 + { 794 + u32 val; 795 + 796 + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 797 + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 798 + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 799 + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 800 + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 801 + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 802 + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 803 + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 804 + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 805 + 806 + /* Set PLL_BYPASSNL */ 807 + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 808 + regmap_read(regmap, PLL_MODE(pll), &val); 809 + 810 + /* Wait 5 us between setting BYPASS and deasserting reset */ 811 + udelay(5); 812 + 813 + /* Take PLL out from reset state */ 814 + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 815 + regmap_read(regmap, PLL_MODE(pll), &val); 816 + 817 + /* Wait 50us for PLL_LOCK_DET bit to go high */ 818 + usleep_range(50, 55); 819 + 820 + /* Enable PLL output */ 821 + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 822 + } 823 + EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); 803 824 804 825 static unsigned long 805 826 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)

drivers/clk/qcom/clk-alpha-pll.h

··· 16 16 CLK_ALPHA_PLL_TYPE_DEFAULT, 17 17 CLK_ALPHA_PLL_TYPE_HUAYRA, 18 18 CLK_ALPHA_PLL_TYPE_HUAYRA_APSS, 19 + CLK_ALPHA_PLL_TYPE_HUAYRA_2290, 19 20 CLK_ALPHA_PLL_TYPE_BRAMMO, 20 21 CLK_ALPHA_PLL_TYPE_FABIA, 21 22 CLK_ALPHA_PLL_TYPE_TRION, ··· 195 194 196 195 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 197 196 const struct alpha_pll_config *config); 197 + void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 198 + const struct alpha_pll_config *config); 198 199 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 199 200 const struct alpha_pll_config *config); 200 201 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

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