pwm: pwm-mediatek: Pass PWM_CK_26M_SEL from platform data

In preparation for adding support for new SoCs, remove variable
has_ck_26m_sel from pwm_mediatek_of_data and replace it with a
u16 pwm_ck_26m_sel_reg, meant to hold the register offset for
PWM_CK_26M_SEL.

Also, since the reg offset is guaranteed to never be zero, the
logic to check for "has_ck_26m_sel" is changed to check if the
register offset in pwm_ck_26m_sel_reg is more than zero.

Analogously, when writing, use the register offset from platform
data instead of using the PWM_CK_26M_SEL definition.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250623120118.109170-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by

Uwe Kleine-König 11 months ago d4f1e7a2 3bb99489

+9 -15

1 changed file

expand all

drivers

pwm

pwm-mediatek.c

+9 -15

drivers/pwm/pwm-mediatek.c

··· 36 36 struct pwm_mediatek_of_data { 37 37 unsigned int num_pwms; 38 38 bool pwm45_fixup; 39 - bool has_ck_26m_sel; 39 + u16 pwm_ck_26m_sel_reg; 40 40 const unsigned int *reg_offset; 41 41 }; 42 42 ··· 136 136 } 137 137 138 138 /* Make sure we use the bus clock and not the 26MHz clock */ 139 - if (pc->soc->has_ck_26m_sel) 140 - writel(0, pc->regs + PWM_CK_26M_SEL); 139 + if (pc->soc->pwm_ck_26m_sel_reg) 140 + writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg); 141 141 142 142 /* Using resolution in picosecond gets accuracy higher */ 143 143 resolution = (u64)NSEC_PER_SEC * 1000; ··· 294 294 static const struct pwm_mediatek_of_data mt2712_pwm_data = { 295 295 .num_pwms = 8, 296 296 .pwm45_fixup = false, 297 - .has_ck_26m_sel = false, 298 297 .reg_offset = mtk_pwm_reg_offset_v1, 299 298 }; 300 299 301 300 static const struct pwm_mediatek_of_data mt6795_pwm_data = { 302 301 .num_pwms = 7, 303 302 .pwm45_fixup = false, 304 - .has_ck_26m_sel = false, 305 303 .reg_offset = mtk_pwm_reg_offset_v1, 306 304 }; 307 305 308 306 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 309 307 .num_pwms = 6, 310 308 .pwm45_fixup = false, 311 - .has_ck_26m_sel = true, 309 + .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 312 310 .reg_offset = mtk_pwm_reg_offset_v1, 313 311 }; 314 312 315 313 static const struct pwm_mediatek_of_data mt7623_pwm_data = { 316 314 .num_pwms = 5, 317 315 .pwm45_fixup = true, 318 - .has_ck_26m_sel = false, 319 316 .reg_offset = mtk_pwm_reg_offset_v1, 320 317 }; 321 318 322 319 static const struct pwm_mediatek_of_data mt7628_pwm_data = { 323 320 .num_pwms = 4, 324 321 .pwm45_fixup = true, 325 - .has_ck_26m_sel = false, 326 322 .reg_offset = mtk_pwm_reg_offset_v1, 327 323 }; 328 324 329 325 static const struct pwm_mediatek_of_data mt7629_pwm_data = { 330 326 .num_pwms = 1, 331 327 .pwm45_fixup = false, 332 - .has_ck_26m_sel = false, 333 328 .reg_offset = mtk_pwm_reg_offset_v1, 334 329 }; 335 330 336 331 static const struct pwm_mediatek_of_data mt7981_pwm_data = { 337 332 .num_pwms = 3, 338 333 .pwm45_fixup = false, 339 - .has_ck_26m_sel = true, 334 + .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 340 335 .reg_offset = mtk_pwm_reg_offset_v2, 341 336 }; 342 337 343 338 static const struct pwm_mediatek_of_data mt7986_pwm_data = { 344 339 .num_pwms = 2, 345 340 .pwm45_fixup = false, 346 - .has_ck_26m_sel = true, 341 + .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 347 342 .reg_offset = mtk_pwm_reg_offset_v1, 348 343 }; 349 344 350 345 static const struct pwm_mediatek_of_data mt7988_pwm_data = { 351 346 .num_pwms = 8, 352 347 .pwm45_fixup = false, 353 - .has_ck_26m_sel = false, 354 348 .reg_offset = mtk_pwm_reg_offset_v2, 355 349 }; 356 350 357 351 static const struct pwm_mediatek_of_data mt8183_pwm_data = { 358 352 .num_pwms = 4, 359 353 .pwm45_fixup = false, 360 - .has_ck_26m_sel = true, 354 + .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 361 355 .reg_offset = mtk_pwm_reg_offset_v1, 362 356 }; 363 357 364 358 static const struct pwm_mediatek_of_data mt8365_pwm_data = { 365 359 .num_pwms = 3, 366 360 .pwm45_fixup = false, 367 - .has_ck_26m_sel = true, 361 + .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 368 362 .reg_offset = mtk_pwm_reg_offset_v1, 369 363 }; 370 364 371 365 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 372 366 .num_pwms = 5, 373 367 .pwm45_fixup = false, 374 - .has_ck_26m_sel = true, 368 + .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 375 369 .reg_offset = mtk_pwm_reg_offset_v1, 376 370 }; 377 371

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