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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller

Add device tree bindings for the Black Sesame Technologies
DWCMSHC SDHCI controller used in C1200 SoC.

The binding describes a Synopsys DesignWare Cores Mobile Storage
Host Controller with BST-specific extensions including:
- Two register regions (core SDHCI and CRM registers)
- Optional memory-region for bounce buffer support
- Fixed clock input

Signed-off-by: Ge Gordon <gordon.ge@bst.ai>
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

authored by

Albert Yang and committed by
Ulf Hansson d5159623 1e9f43a1

+70
+70
Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mmc/bst,c1200-sdhci.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Black Sesame Technologies DWCMSHC SDHCI Controller 8 + 9 + maintainers: 10 + - Ge Gordon <gordon.ge@bst.ai> 11 + 12 + allOf: 13 + - $ref: sdhci-common.yaml# 14 + 15 + properties: 16 + compatible: 17 + const: bst,c1200-sdhci 18 + 19 + reg: 20 + items: 21 + - description: Core SDHCI registers 22 + - description: CRM registers 23 + 24 + interrupts: 25 + maxItems: 1 26 + 27 + clocks: 28 + maxItems: 1 29 + 30 + clock-names: 31 + items: 32 + - const: core 33 + 34 + memory-region: 35 + maxItems: 1 36 + 37 + dma-coherent: true 38 + 39 + required: 40 + - compatible 41 + - reg 42 + - interrupts 43 + - clocks 44 + - clock-names 45 + 46 + unevaluatedProperties: false 47 + 48 + examples: 49 + - | 50 + #include <dt-bindings/interrupt-controller/arm-gic.h> 51 + #include <dt-bindings/interrupt-controller/irq.h> 52 + 53 + bus { 54 + #address-cells = <2>; 55 + #size-cells = <2>; 56 + 57 + mmc@22200000 { 58 + compatible = "bst,c1200-sdhci"; 59 + reg = <0x0 0x22200000 0x0 0x1000>, 60 + <0x0 0x23006000 0x0 0x1000>; 61 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 62 + clocks = <&clk_mmc>; 63 + clock-names = "core"; 64 + memory-region = <&mmc0_reserved>; 65 + max-frequency = <200000000>; 66 + bus-width = <8>; 67 + non-removable; 68 + dma-coherent; 69 + }; 70 + };