Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Will Deacon:
"These are almost exclusively related to CPU errata in CPUs from
Broadcom and Qualcomm where the workarounds were either not being
enabled when they should have been or enabled when they shouldn't have
been.
The only "interesting" fix is ensuring that writeable, shared mappings
are initially mapped as clean since we inadvertently broke the logic
back in v4.14 and then noticed the problem via code inspection the
other day.
The only critical issue we have outstanding is a sporadic NULL
dereference in the scheduler, which doesn't appear to be
arm64-specific and PeterZ is tearing his hair out over it at the
moment.
Summary:
- Enable CPU errata workarounds for Broadcom Brahma-B53
- Enable CPU errata workarounds for Qualcomm Hydra/Kryo CPUs
- Fix initial dirty status of writeable, shared mappings"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core
arm64: Brahma-B53 is SSB and spectre v2 safe
arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core
arm64: cpufeature: Enable Qualcomm Falkor errata 1009 for Kryo
arm64: cpufeature: Enable Qualcomm Falkor/Kryo errata 1003
arm64: Ensure VM_WRITE|VM_SHARED ptes are clean by default
+64
-19
+6
-1
Documentation/arm64/silicon-errata.rst
+6
-1
Documentation/arm64/silicon-errata.rst
···
91
91
| ARM | MMU-500 | #841119,826419 | N/A |
92
92
+----------------+-----------------+-----------------+-----------------------------+
93
93
+----------------+-----------------+-----------------+-----------------------------+
94
+
| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 |
95
+
+----------------+-----------------+-----------------+-----------------------------+
96
+
| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 |
97
+
+----------------+-----------------+-----------------+-----------------------------+
98
+
+----------------+-----------------+-----------------+-----------------------------+
94
99
| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
95
100
+----------------+-----------------+-----------------+-----------------------------+
96
101
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
···
131
126
+----------------+-----------------+-----------------+-----------------------------+
132
127
| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
133
128
+----------------+-----------------+-----------------+-----------------------------+
134
-
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
129
+
| Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
135
130
+----------------+-----------------+-----------------+-----------------------------+
136
131
| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
137
132
+----------------+-----------------+-----------------+-----------------------------+
+2
arch/arm64/include/asm/cputype.h
+2
arch/arm64/include/asm/cputype.h
···
79
79
#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
80
80
#define CAVIUM_CPU_PART_THUNDERX2 0x0AF
81
81
82
+
#define BRCM_CPU_PART_BRAHMA_B53 0x100
82
83
#define BRCM_CPU_PART_VULCAN 0x516
83
84
84
85
#define QCOM_CPU_PART_FALKOR_V1 0x800
···
106
105
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
107
106
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
108
107
#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
108
+
#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
109
109
#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
110
110
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
111
111
#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
+8
-7
arch/arm64/include/asm/pgtable-prot.h
+8
-7
arch/arm64/include/asm/pgtable-prot.h
···
32
32
#define PROT_DEFAULT (_PROT_DEFAULT | PTE_MAYBE_NG)
33
33
#define PROT_SECT_DEFAULT (_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
34
34
35
-
#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
36
-
#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
37
-
#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
38
-
#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
39
-
#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
35
+
#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
36
+
#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
37
+
#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
38
+
#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
39
+
#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
40
40
41
41
#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
42
42
#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
···
80
80
#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)
81
81
82
82
#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
83
-
#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
84
-
#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
83
+
/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
84
+
#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
85
+
#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
85
86
#define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
86
87
#define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
87
88
#define PAGE_EXECONLY __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
+48
-11
arch/arm64/kernel/cpu_errata.c
+48
-11
arch/arm64/kernel/cpu_errata.c
···
489
489
MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
490
490
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
491
491
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
492
+
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
492
493
{},
493
494
};
494
495
···
574
573
MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
575
574
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
576
575
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
576
+
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
577
577
{ /* sentinel */ }
578
578
};
579
579
···
661
659
#endif
662
660
663
661
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
664
-
665
-
static const struct midr_range arm64_repeat_tlbi_cpus[] = {
662
+
static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
666
663
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
667
-
MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0),
664
+
{
665
+
ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
666
+
},
667
+
{
668
+
.midr_range.model = MIDR_QCOM_KRYO,
669
+
.matches = is_kryo_midr,
670
+
},
668
671
#endif
669
672
#ifdef CONFIG_ARM64_ERRATUM_1286807
670
-
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
673
+
{
674
+
ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
675
+
},
671
676
#endif
672
677
{},
673
678
};
674
-
675
679
#endif
676
680
677
681
#ifdef CONFIG_CAVIUM_ERRATUM_27456
···
745
737
};
746
738
#endif
747
739
740
+
#ifdef CONFIG_ARM64_ERRATUM_845719
741
+
static const struct midr_range erratum_845719_list[] = {
742
+
/* Cortex-A53 r0p[01234] */
743
+
MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
744
+
/* Brahma-B53 r0p[0] */
745
+
MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
746
+
{},
747
+
};
748
+
#endif
749
+
750
+
#ifdef CONFIG_ARM64_ERRATUM_843419
751
+
static const struct arm64_cpu_capabilities erratum_843419_list[] = {
752
+
{
753
+
/* Cortex-A53 r0p[01234] */
754
+
.matches = is_affected_midr_range,
755
+
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
756
+
MIDR_FIXED(0x4, BIT(8)),
757
+
},
758
+
{
759
+
/* Brahma-B53 r0p[0] */
760
+
.matches = is_affected_midr_range,
761
+
ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
762
+
},
763
+
{},
764
+
};
765
+
#endif
766
+
748
767
const struct arm64_cpu_capabilities arm64_errata[] = {
749
768
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
750
769
{
···
803
768
#endif
804
769
#ifdef CONFIG_ARM64_ERRATUM_843419
805
770
{
806
-
/* Cortex-A53 r0p[01234] */
807
771
.desc = "ARM erratum 843419",
808
772
.capability = ARM64_WORKAROUND_843419,
809
-
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
810
-
MIDR_FIXED(0x4, BIT(8)),
773
+
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
774
+
.matches = cpucap_multi_entry_cap_matches,
775
+
.match_list = erratum_843419_list,
811
776
},
812
777
#endif
813
778
#ifdef CONFIG_ARM64_ERRATUM_845719
814
779
{
815
-
/* Cortex-A53 r0p[01234] */
816
780
.desc = "ARM erratum 845719",
817
781
.capability = ARM64_WORKAROUND_845719,
818
-
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
782
+
ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
819
783
},
820
784
#endif
821
785
#ifdef CONFIG_CAVIUM_ERRATUM_23154
···
850
816
{
851
817
.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
852
818
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
819
+
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
853
820
.matches = cpucap_multi_entry_cap_matches,
854
821
.match_list = qcom_erratum_1003_list,
855
822
},
···
859
824
{
860
825
.desc = "Qualcomm erratum 1009, ARM erratum 1286807",
861
826
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
862
-
ERRATA_MIDR_RANGE_LIST(arm64_repeat_tlbi_cpus),
827
+
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
828
+
.matches = cpucap_multi_entry_cap_matches,
829
+
.match_list = arm64_repeat_tlbi_list,
863
830
},
864
831
#endif
865
832
#ifdef CONFIG_ARM64_ERRATUM_858921