iio: filter: admv8818: fix range calculation

Search for the minimum error while ensuring that the LPF corner
frequency is greater than the target, and the HPF corner frequency
is lower than the target

This fixes issues where the range calculations were suboptimal.

Add two new DTS properties to set the margin between the input frequency
and the calculated corner frequency

Below is a generated table of the differences between the old algorithm
and the new. This is a sweep from 0 to 20 GHz in 10 MHz steps.
=== HPF ===
freq = 1750 MHz, 3db: bypass => 1750 MHz
freq = 3400 MHz, 3db: 3310 => 3400 MHz
freq = 3410 MHz, 3db: 3310 => 3400 MHz
freq = 3420 MHz, 3db: 3310 => 3400 MHz
freq = 3660 MHz, 3db: 3550 => 3656 MHz
freq = 6600 MHz, 3db: 6479 => 6600 MHz
freq = 6610 MHz, 3db: 6479 => 6600 MHz
freq = 6620 MHz, 3db: 6479 => 6600 MHz
freq = 6630 MHz, 3db: 6479 => 6600 MHz
freq = 6640 MHz, 3db: 6479 => 6600 MHz
freq = 6650 MHz, 3db: 6479 => 6600 MHz
freq = 6660 MHz, 3db: 6479 => 6600 MHz
freq = 6670 MHz, 3db: 6479 => 6600 MHz
freq = 6680 MHz, 3db: 6479 => 6600 MHz
freq = 6690 MHz, 3db: 6479 => 6600 MHz
freq = 6700 MHz, 3db: 6479 => 6600 MHz
freq = 6710 MHz, 3db: 6479 => 6600 MHz
freq = 6720 MHz, 3db: 6479 => 6600 MHz
freq = 6730 MHz, 3db: 6479 => 6600 MHz
freq = 6960 MHz, 3db: 6736 => 6960 MHz
freq = 6970 MHz, 3db: 6736 => 6960 MHz
freq = 6980 MHz, 3db: 6736 => 6960 MHz
freq = 6990 MHz, 3db: 6736 => 6960 MHz
freq = 7320 MHz, 3db: 7249 => 7320 MHz
freq = 7330 MHz, 3db: 7249 => 7320 MHz
freq = 7340 MHz, 3db: 7249 => 7320 MHz
freq = 7350 MHz, 3db: 7249 => 7320 MHz
freq = 7360 MHz, 3db: 7249 => 7320 MHz
freq = 7370 MHz, 3db: 7249 => 7320 MHz
freq = 7380 MHz, 3db: 7249 => 7320 MHz
freq = 7390 MHz, 3db: 7249 => 7320 MHz
freq = 7400 MHz, 3db: 7249 => 7320 MHz
freq = 7410 MHz, 3db: 7249 => 7320 MHz
freq = 7420 MHz, 3db: 7249 => 7320 MHz
freq = 7430 MHz, 3db: 7249 => 7320 MHz
freq = 7440 MHz, 3db: 7249 => 7320 MHz
freq = 7450 MHz, 3db: 7249 => 7320 MHz
freq = 7460 MHz, 3db: 7249 => 7320 MHz
freq = 7470 MHz, 3db: 7249 => 7320 MHz
freq = 7480 MHz, 3db: 7249 => 7320 MHz
freq = 7490 MHz, 3db: 7249 => 7320 MHz
freq = 7500 MHz, 3db: 7249 => 7320 MHz
freq = 12500 MHz, 3db: 12000 => 12500 MHz

=== LPF ===
freq = 2050 MHz, 3db: bypass => 2050 MHz
freq = 2170 MHz, 3db: 2290 => 2170 MHz
freq = 2290 MHz, 3db: 2410 => 2290 MHz
freq = 2410 MHz, 3db: 2530 => 2410 MHz
freq = 2530 MHz, 3db: 2650 => 2530 MHz
freq = 2650 MHz, 3db: 2770 => 2650 MHz
freq = 2770 MHz, 3db: 2890 => 2770 MHz
freq = 2890 MHz, 3db: 3010 => 2890 MHz
freq = 3010 MHz, 3db: 3130 => 3010 MHz
freq = 3130 MHz, 3db: 3250 => 3130 MHz
freq = 3250 MHz, 3db: 3370 => 3250 MHz
freq = 3260 MHz, 3db: 3370 => 3350 MHz
freq = 3270 MHz, 3db: 3370 => 3350 MHz
freq = 3280 MHz, 3db: 3370 => 3350 MHz
freq = 3290 MHz, 3db: 3370 => 3350 MHz
freq = 3300 MHz, 3db: 3370 => 3350 MHz
freq = 3310 MHz, 3db: 3370 => 3350 MHz
freq = 3320 MHz, 3db: 3370 => 3350 MHz
freq = 3330 MHz, 3db: 3370 => 3350 MHz
freq = 3340 MHz, 3db: 3370 => 3350 MHz
freq = 3350 MHz, 3db: 3370 => 3350 MHz
freq = 3370 MHz, 3db: 3490 => 3370 MHz
freq = 3490 MHz, 3db: 3610 => 3490 MHz
freq = 3610 MHz, 3db: 3730 => 3610 MHz
freq = 3730 MHz, 3db: 3850 => 3730 MHz
freq = 3850 MHz, 3db: 3870 => 3850 MHz
freq = 3870 MHz, 3db: 4130 => 3870 MHz
freq = 4130 MHz, 3db: 4390 => 4130 MHz
freq = 4390 MHz, 3db: 4650 => 4390 MHz
freq = 4650 MHz, 3db: 4910 => 4650 MHz
freq = 4910 MHz, 3db: 5170 => 4910 MHz
freq = 5170 MHz, 3db: 5430 => 5170 MHz
freq = 5430 MHz, 3db: 5690 => 5430 MHz
freq = 5690 MHz, 3db: 5950 => 5690 MHz
freq = 5950 MHz, 3db: 6210 => 5950 MHz
freq = 6210 MHz, 3db: 6470 => 6210 MHz
freq = 6470 MHz, 3db: 6730 => 6470 MHz
freq = 6730 MHz, 3db: 6990 => 6730 MHz
freq = 6990 MHz, 3db: 7250 => 6990 MHz
freq = 7000 MHz, 3db: 7250 => 7000 MHz
freq = 7250 MHz, 3db: 7400 => 7250 MHz
freq = 7400 MHz, 3db: 7800 => 7400 MHz
freq = 7800 MHz, 3db: 8200 => 7800 MHz
freq = 8200 MHz, 3db: 8600 => 8200 MHz
freq = 8600 MHz, 3db: 9000 => 8600 MHz
freq = 9000 MHz, 3db: 9400 => 9000 MHz
freq = 9400 MHz, 3db: 9800 => 9400 MHz
freq = 9800 MHz, 3db: 10200 => 9800 MHz
freq = 10200 MHz, 3db: 10600 => 10200 MHz
freq = 10600 MHz, 3db: 11000 => 10600 MHz
freq = 11000 MHz, 3db: 11400 => 11000 MHz
freq = 11400 MHz, 3db: 11800 => 11400 MHz
freq = 11800 MHz, 3db: 12200 => 11800 MHz
freq = 12200 MHz, 3db: 12600 => 12200 MHz
freq = 12210 MHz, 3db: 12600 => 12550 MHz
freq = 12220 MHz, 3db: 12600 => 12550 MHz
freq = 12230 MHz, 3db: 12600 => 12550 MHz
freq = 12240 MHz, 3db: 12600 => 12550 MHz
freq = 12250 MHz, 3db: 12600 => 12550 MHz
freq = 12260 MHz, 3db: 12600 => 12550 MHz
freq = 12270 MHz, 3db: 12600 => 12550 MHz
freq = 12280 MHz, 3db: 12600 => 12550 MHz
freq = 12290 MHz, 3db: 12600 => 12550 MHz
freq = 12300 MHz, 3db: 12600 => 12550 MHz
freq = 12310 MHz, 3db: 12600 => 12550 MHz
freq = 12320 MHz, 3db: 12600 => 12550 MHz
freq = 12330 MHz, 3db: 12600 => 12550 MHz
freq = 12340 MHz, 3db: 12600 => 12550 MHz
freq = 12350 MHz, 3db: 12600 => 12550 MHz
freq = 12360 MHz, 3db: 12600 => 12550 MHz
freq = 12370 MHz, 3db: 12600 => 12550 MHz
freq = 12380 MHz, 3db: 12600 => 12550 MHz
freq = 12390 MHz, 3db: 12600 => 12550 MHz
freq = 12400 MHz, 3db: 12600 => 12550 MHz
freq = 12410 MHz, 3db: 12600 => 12550 MHz
freq = 12420 MHz, 3db: 12600 => 12550 MHz
freq = 12430 MHz, 3db: 12600 => 12550 MHz
freq = 12440 MHz, 3db: 12600 => 12550 MHz
freq = 12450 MHz, 3db: 12600 => 12550 MHz
freq = 12460 MHz, 3db: 12600 => 12550 MHz
freq = 12470 MHz, 3db: 12600 => 12550 MHz
freq = 12480 MHz, 3db: 12600 => 12550 MHz
freq = 12490 MHz, 3db: 12600 => 12550 MHz
freq = 12500 MHz, 3db: 12600 => 12550 MHz
freq = 12510 MHz, 3db: 12600 => 12550 MHz
freq = 12520 MHz, 3db: 12600 => 12550 MHz
freq = 12530 MHz, 3db: 12600 => 12550 MHz
freq = 12540 MHz, 3db: 12600 => 12550 MHz
freq = 12550 MHz, 3db: 12600 => 12550 MHz
freq = 12600 MHz, 3db: 13000 => 12600 MHz
freq = 12610 MHz, 3db: 13000 => 12970 MHz
freq = 12620 MHz, 3db: 13000 => 12970 MHz
freq = 12630 MHz, 3db: 13000 => 12970 MHz
freq = 12640 MHz, 3db: 13000 => 12970 MHz
freq = 12650 MHz, 3db: 13000 => 12970 MHz
freq = 12660 MHz, 3db: 13000 => 12970 MHz
freq = 12670 MHz, 3db: 13000 => 12970 MHz
freq = 12680 MHz, 3db: 13000 => 12970 MHz
freq = 12690 MHz, 3db: 13000 => 12970 MHz
freq = 12700 MHz, 3db: 13000 => 12970 MHz
freq = 12710 MHz, 3db: 13000 => 12970 MHz
freq = 12720 MHz, 3db: 13000 => 12970 MHz
freq = 12730 MHz, 3db: 13000 => 12970 MHz
freq = 12740 MHz, 3db: 13000 => 12970 MHz
freq = 12750 MHz, 3db: 13000 => 12970 MHz
freq = 12760 MHz, 3db: 13000 => 12970 MHz
freq = 12770 MHz, 3db: 13000 => 12970 MHz
freq = 12780 MHz, 3db: 13000 => 12970 MHz
freq = 12790 MHz, 3db: 13000 => 12970 MHz
freq = 12800 MHz, 3db: 13000 => 12970 MHz
freq = 12810 MHz, 3db: 13000 => 12970 MHz
freq = 12820 MHz, 3db: 13000 => 12970 MHz
freq = 12830 MHz, 3db: 13000 => 12970 MHz
freq = 12840 MHz, 3db: 13000 => 12970 MHz
freq = 12850 MHz, 3db: 13000 => 12970 MHz
freq = 12860 MHz, 3db: 13000 => 12970 MHz
freq = 12870 MHz, 3db: 13000 => 12970 MHz
freq = 12880 MHz, 3db: 13000 => 12970 MHz
freq = 12890 MHz, 3db: 13000 => 12970 MHz
freq = 12900 MHz, 3db: 13000 => 12970 MHz
freq = 12910 MHz, 3db: 13000 => 12970 MHz
freq = 12920 MHz, 3db: 13000 => 12970 MHz
freq = 12930 MHz, 3db: 13000 => 12970 MHz
freq = 12940 MHz, 3db: 13000 => 12970 MHz
freq = 12950 MHz, 3db: 13000 => 12970 MHz
freq = 12960 MHz, 3db: 13000 => 12970 MHz
freq = 12970 MHz, 3db: 13000 => 12970 MHz
freq = 13000 MHz, 3db: 13390 => 13000 MHz
freq = 13390 MHz, 3db: 13810 => 13390 MHz
freq = 13810 MHz, 3db: 14230 => 13810 MHz
freq = 14230 MHz, 3db: 14650 => 14230 MHz
freq = 14650 MHz, 3db: 15070 => 14650 MHz
freq = 15070 MHz, 3db: 15490 => 15070 MHz
freq = 15490 MHz, 3db: 15910 => 15490 MHz
freq = 15910 MHz, 3db: 16330 => 15910 MHz
freq = 16330 MHz, 3db: 16750 => 16330 MHz
freq = 16750 MHz, 3db: 17170 => 16750 MHz
freq = 17170 MHz, 3db: 17590 => 17170 MHz
freq = 17590 MHz, 3db: 18010 => 17590 MHz
freq = 18010 MHz, 3db: 18430 => 18010 MHz
freq = 18430 MHz, 3db: 18850 => 18430 MHz
freq = 18850 MHz, 3db: bypass => 18850 MHz

Fixes: f34fe888ad05 ("iio:filter:admv8818: add support for ADMV8818")
Signed-off-by: Sam Winchenbach <swinchenbach@arka.org>
Link: https://patch.msgid.link/20250328174831.227202-5-sam.winchenbach@framepointer.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Sam Winchenbach and committed by

Jonathan Cameron 1 year ago d542db70 fb6009a2

+154 -55

1 changed file

expand all

drivers

iio

filter

admv8818.c

+154 -55

drivers/iio/filter/admv8818.c

··· 14 14 #include <linux/mod_devicetable.h> 15 15 #include <linux/mutex.h> 16 16 #include <linux/notifier.h> 17 + #include <linux/property.h> 17 18 #include <linux/regmap.h> 18 19 #include <linux/spi/spi.h> 19 20 #include <linux/units.h> ··· 71 70 #define ADMV8818_HPF_WR0_MSK GENMASK(7, 4) 72 71 #define ADMV8818_LPF_WR0_MSK GENMASK(3, 0) 73 72 73 + #define ADMV8818_BAND_BYPASS 0 74 + #define ADMV8818_BAND_MIN 1 75 + #define ADMV8818_BAND_MAX 4 76 + #define ADMV8818_BAND_CORNER_LOW 0 77 + #define ADMV8818_BAND_CORNER_HIGH 1 78 + 79 + #define ADMV8818_STATE_MIN 0 80 + #define ADMV8818_STATE_MAX 15 81 + #define ADMV8818_NUM_STATES 16 82 + 74 83 enum { 75 84 ADMV8818_BW_FREQ, 76 85 ADMV8818_CENTER_FREQ ··· 101 90 struct mutex lock; 102 91 unsigned int filter_mode; 103 92 u64 cf_hz; 93 + u64 lpf_margin_hz; 94 + u64 hpf_margin_hz; 104 95 }; 105 96 106 - static const unsigned long long freq_range_hpf[4][2] = { 97 + static const unsigned long long freq_range_hpf[5][2] = { 98 + {0ULL, 0ULL}, /* bypass */ 107 99 {1750000000ULL, 3550000000ULL}, 108 100 {3400000000ULL, 7250000000ULL}, 109 101 {6600000000, 12000000000}, 110 102 {12500000000, 19900000000} 111 103 }; 112 104 113 - static const unsigned long long freq_range_lpf[4][2] = { 105 + static const unsigned long long freq_range_lpf[5][2] = { 106 + {U64_MAX, U64_MAX}, /* bypass */ 114 107 {2050000000ULL, 3850000000ULL}, 115 108 {3350000000ULL, 7250000000ULL}, 116 109 {7000000000, 13000000000}, ··· 136 121 137 122 static int __admv8818_hpf_select(struct admv8818_state *st, u64 freq) 138 123 { 139 - unsigned int hpf_step = 0, hpf_band = 0, i, j; 140 - u64 freq_step; 141 - int ret; 124 + int band, state, ret; 125 + unsigned int hpf_state = ADMV8818_STATE_MIN, hpf_band = ADMV8818_BAND_BYPASS; 126 + u64 freq_error, min_freq_error, freq_corner, freq_step; 142 127 143 - if (freq < freq_range_hpf[0][0]) 128 + if (freq < freq_range_hpf[ADMV8818_BAND_MIN][ADMV8818_BAND_CORNER_LOW]) 144 129 goto hpf_write; 145 130 146 - if (freq > freq_range_hpf[3][1]) { 147 - hpf_step = 15; 148 - hpf_band = 4; 149 - 131 + if (freq >= freq_range_hpf[ADMV8818_BAND_MAX][ADMV8818_BAND_CORNER_HIGH]) { 132 + hpf_state = ADMV8818_STATE_MAX; 133 + hpf_band = ADMV8818_BAND_MAX; 150 134 goto hpf_write; 151 - } 152 - 153 - for (i = 0; i < 4; i++) { 154 - freq_step = div_u64((freq_range_hpf[i][1] - 155 - freq_range_hpf[i][0]), 15); 156 - 157 - if (freq > freq_range_hpf[i][0] && 158 - (freq < freq_range_hpf[i][1] + freq_step)) { 159 - hpf_band = i + 1; 160 - 161 - for (j = 1; j <= 16; j++) { 162 - if (freq < (freq_range_hpf[i][0] + (freq_step * j))) { 163 - hpf_step = j - 1; 164 - break; 165 - } 166 - } 167 - break; 168 - } 169 135 } 170 136 171 137 /* Close HPF frequency gap between 12 and 12.5 GHz */ 172 138 if (freq >= 12000ULL * HZ_PER_MHZ && freq < 12500ULL * HZ_PER_MHZ) { 139 + hpf_state = ADMV8818_STATE_MAX; 173 140 hpf_band = 3; 174 - hpf_step = 15; 141 + goto hpf_write; 142 + } 143 + 144 + min_freq_error = U64_MAX; 145 + for (band = ADMV8818_BAND_MIN; band <= ADMV8818_BAND_MAX; band++) { 146 + /* 147 + * This (and therefore all other ranges) have a corner 148 + * frequency higher than the target frequency. 149 + */ 150 + if (freq_range_hpf[band][ADMV8818_BAND_CORNER_LOW] > freq) 151 + break; 152 + 153 + freq_step = freq_range_hpf[band][ADMV8818_BAND_CORNER_HIGH] - 154 + freq_range_hpf[band][ADMV8818_BAND_CORNER_LOW]; 155 + freq_step = div_u64(freq_step, ADMV8818_NUM_STATES - 1); 156 + 157 + for (state = ADMV8818_STATE_MIN; state <= ADMV8818_STATE_MAX; state++) { 158 + freq_corner = freq_range_hpf[band][ADMV8818_BAND_CORNER_LOW] + 159 + freq_step * state; 160 + 161 + /* 162 + * This (and therefore all other states) have a corner 163 + * frequency higher than the target frequency. 164 + */ 165 + if (freq_corner > freq) 166 + break; 167 + 168 + freq_error = freq - freq_corner; 169 + if (freq_error < min_freq_error) { 170 + min_freq_error = freq_error; 171 + hpf_state = state; 172 + hpf_band = band; 173 + } 174 + } 175 175 } 176 176 177 177 hpf_write: ··· 200 170 201 171 return regmap_update_bits(st->regmap, ADMV8818_REG_WR0_FILTER, 202 172 ADMV8818_HPF_WR0_MSK, 203 - FIELD_PREP(ADMV8818_HPF_WR0_MSK, hpf_step)); 173 + FIELD_PREP(ADMV8818_HPF_WR0_MSK, hpf_state)); 204 174 } 205 175 206 176 static int admv8818_hpf_select(struct admv8818_state *st, u64 freq) ··· 216 186 217 187 static int __admv8818_lpf_select(struct admv8818_state *st, u64 freq) 218 188 { 219 - unsigned int lpf_step = 0, lpf_band = 0, i, j; 220 - u64 freq_step; 221 - int ret; 189 + int band, state, ret; 190 + unsigned int lpf_state = ADMV8818_STATE_MIN, lpf_band = ADMV8818_BAND_BYPASS; 191 + u64 freq_error, min_freq_error, freq_corner, freq_step; 222 192 223 - if (freq > freq_range_lpf[3][1]) 193 + if (freq > freq_range_lpf[ADMV8818_BAND_MAX][ADMV8818_BAND_CORNER_HIGH]) 224 194 goto lpf_write; 225 195 226 - if (freq < freq_range_lpf[0][0]) { 227 - lpf_band = 1; 228 - 196 + if (freq < freq_range_lpf[ADMV8818_BAND_MIN][ADMV8818_BAND_CORNER_LOW]) { 197 + lpf_state = ADMV8818_STATE_MIN; 198 + lpf_band = ADMV8818_BAND_MIN; 229 199 goto lpf_write; 230 200 } 231 201 232 - for (i = 0; i < 4; i++) { 233 - if (freq > freq_range_lpf[i][0] && freq < freq_range_lpf[i][1]) { 234 - lpf_band = i + 1; 235 - freq_step = div_u64((freq_range_lpf[i][1] - freq_range_lpf[i][0]), 15); 236 - 237 - for (j = 0; j <= 15; j++) { 238 - if (freq < (freq_range_lpf[i][0] + (freq_step * j))) { 239 - lpf_step = j; 240 - break; 241 - } 242 - } 202 + min_freq_error = U64_MAX; 203 + for (band = ADMV8818_BAND_MAX; band >= ADMV8818_BAND_MIN; --band) { 204 + /* 205 + * At this point the highest corner frequency of 206 + * all remaining ranges is below the target. 207 + * LPF corner should be >= the target. 208 + */ 209 + if (freq > freq_range_lpf[band][ADMV8818_BAND_CORNER_HIGH]) 243 210 break; 211 + 212 + freq_step = freq_range_lpf[band][ADMV8818_BAND_CORNER_HIGH] - 213 + freq_range_lpf[band][ADMV8818_BAND_CORNER_LOW]; 214 + freq_step = div_u64(freq_step, ADMV8818_NUM_STATES - 1); 215 + 216 + for (state = ADMV8818_STATE_MAX; state >= ADMV8818_STATE_MIN; --state) { 217 + 218 + freq_corner = freq_range_lpf[band][ADMV8818_BAND_CORNER_LOW] + 219 + state * freq_step; 220 + 221 + /* 222 + * At this point all other states in range will 223 + * place the corner frequency below the target 224 + * LPF corner should >= the target. 225 + */ 226 + if (freq > freq_corner) 227 + break; 228 + 229 + freq_error = freq_corner - freq; 230 + if (freq_error < min_freq_error) { 231 + min_freq_error = freq_error; 232 + lpf_state = state; 233 + lpf_band = band; 234 + } 244 235 } 245 236 } 246 237 ··· 276 225 277 226 return regmap_update_bits(st->regmap, ADMV8818_REG_WR0_FILTER, 278 227 ADMV8818_LPF_WR0_MSK, 279 - FIELD_PREP(ADMV8818_LPF_WR0_MSK, lpf_step)); 228 + FIELD_PREP(ADMV8818_LPF_WR0_MSK, lpf_state)); 280 229 } 281 230 282 231 static int admv8818_lpf_select(struct admv8818_state *st, u64 freq) ··· 293 242 static int admv8818_rfin_band_select(struct admv8818_state *st) 294 243 { 295 244 int ret; 245 + u64 hpf_corner_target, lpf_corner_target; 296 246 297 247 st->cf_hz = clk_get_rate(st->clkin); 298 248 249 + /* Check for underflow */ 250 + if (st->cf_hz > st->hpf_margin_hz) 251 + hpf_corner_target = st->cf_hz - st->hpf_margin_hz; 252 + else 253 + hpf_corner_target = 0; 254 + 255 + /* Check for overflow */ 256 + lpf_corner_target = st->cf_hz + st->lpf_margin_hz; 257 + if (lpf_corner_target < st->cf_hz) 258 + lpf_corner_target = U64_MAX; 259 + 299 260 mutex_lock(&st->lock); 300 261 301 - ret = __admv8818_hpf_select(st, st->cf_hz); 262 + ret = __admv8818_hpf_select(st, hpf_corner_target); 302 263 if (ret) 303 264 goto exit; 304 265 305 - ret = __admv8818_lpf_select(st, st->cf_hz); 266 + ret = __admv8818_lpf_select(st, lpf_corner_target); 306 267 exit: 307 268 mutex_unlock(&st->lock); 308 269 return ret; ··· 341 278 342 279 hpf_state = FIELD_GET(ADMV8818_HPF_WR0_MSK, data); 343 280 344 - *hpf_freq = div_u64(freq_range_hpf[hpf_band - 1][1] - freq_range_hpf[hpf_band - 1][0], 15); 345 - *hpf_freq = freq_range_hpf[hpf_band - 1][0] + (*hpf_freq * hpf_state); 281 + *hpf_freq = freq_range_hpf[hpf_band][ADMV8818_BAND_CORNER_HIGH] - 282 + freq_range_hpf[hpf_band][ADMV8818_BAND_CORNER_LOW]; 283 + *hpf_freq = div_u64(*hpf_freq, ADMV8818_NUM_STATES - 1); 284 + *hpf_freq = freq_range_hpf[hpf_band][ADMV8818_BAND_CORNER_LOW] + 285 + (*hpf_freq * hpf_state); 346 286 347 287 return ret; 348 288 } ··· 382 316 383 317 lpf_state = FIELD_GET(ADMV8818_LPF_WR0_MSK, data); 384 318 385 - *lpf_freq = div_u64(freq_range_lpf[lpf_band - 1][1] - freq_range_lpf[lpf_band - 1][0], 15); 386 - *lpf_freq = freq_range_lpf[lpf_band - 1][0] + (*lpf_freq * lpf_state); 319 + *lpf_freq = freq_range_lpf[lpf_band][ADMV8818_BAND_CORNER_HIGH] - 320 + freq_range_lpf[lpf_band][ADMV8818_BAND_CORNER_LOW]; 321 + *lpf_freq = div_u64(*lpf_freq, ADMV8818_NUM_STATES - 1); 322 + *lpf_freq = freq_range_lpf[lpf_band][ADMV8818_BAND_CORNER_LOW] + 323 + (*lpf_freq * lpf_state); 387 324 388 325 return ret; 389 326 } ··· 710 641 return devm_add_action_or_reset(&spi->dev, admv8818_clk_notifier_unreg, st); 711 642 } 712 643 644 + static int admv8818_read_properties(struct admv8818_state *st) 645 + { 646 + struct spi_device *spi = st->spi; 647 + u32 mhz; 648 + int ret; 649 + 650 + ret = device_property_read_u32(&spi->dev, "adi,lpf-margin-mhz", &mhz); 651 + if (ret == 0) 652 + st->lpf_margin_hz = (u64)mhz * HZ_PER_MHZ; 653 + else if (ret == -EINVAL) 654 + st->lpf_margin_hz = 0; 655 + else 656 + return ret; 657 + 658 + 659 + ret = device_property_read_u32(&spi->dev, "adi,hpf-margin-mhz", &mhz); 660 + if (ret == 0) 661 + st->hpf_margin_hz = (u64)mhz * HZ_PER_MHZ; 662 + else if (ret == -EINVAL) 663 + st->hpf_margin_hz = 0; 664 + else if (ret < 0) 665 + return ret; 666 + 667 + return 0; 668 + } 669 + 713 670 static int admv8818_probe(struct spi_device *spi) 714 671 { 715 672 struct iio_dev *indio_dev; ··· 766 671 return ret; 767 672 768 673 mutex_init(&st->lock); 674 + 675 + ret = admv8818_read_properties(st); 676 + if (ret) 677 + return ret; 769 678 770 679 ret = admv8818_init(st); 771 680 if (ret)

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