tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
first SE, which supports a 4-wire UART configuration suitable for
applications such as HS-UART.

Note that the required initialization for this SE is not handled by the
bootloader. Therefore, add the SE node in the device tree but keep it
reserved. Enable it once Linux gains support for configuring the SE,
allowing to use in relevant RDPs.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250812-ipq5424_hsuart-v4-1-f1faa7704ea9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Kathiravan Thirumoorthy and committed by
Bjorn Andersson d56ddcee 393d69df

+27
+18
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
··· 224 224 }; 225 225 }; 226 226 227 + uart0_pins: uart0-default-state { 228 + pins = "gpio10", "gpio11", "gpio12", "gpio13"; 229 + function = "uart0"; 230 + drive-strength = <8>; 231 + bias-pull-down; 232 + }; 233 + 227 234 pcie2_default_state: pcie2-default-state { 228 235 pins = "gpio31"; 229 236 function = "gpio"; ··· 244 237 drive-strength = <8>; 245 238 bias-pull-up; 246 239 }; 240 + }; 241 + 242 + &uart0 { 243 + pinctrl-0 = <&uart0_pins>; 244 + pinctrl-names = "default"; 245 + /* 246 + * The required initialization for this SE is not handled by the 247 + * bootloader. Therefore, keep the device in "reserved" state until 248 + * linux gains support for configuring the SE. 249 + */ 250 + status = "reserved"; 247 251 }; 248 252 249 253 &uart1 {
+9
arch/arm64/boot/dts/qcom/ipq5424.dtsi
··· 442 442 #address-cells = <2>; 443 443 #size-cells = <2>; 444 444 445 + uart0: serial@1a80000 { 446 + compatible = "qcom,geni-uart"; 447 + reg = <0 0x01a80000 0 0x4000>; 448 + clocks = <&gcc GCC_QUPV3_UART0_CLK>; 449 + clock-names = "se"; 450 + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 451 + status = "disabled"; 452 + }; 453 + 445 454 uart1: serial@1a84000 { 446 455 compatible = "qcom,geni-debug-uart"; 447 456 reg = <0 0x01a84000 0 0x4000>;