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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'dmaengine-fix2-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine fixes from Vinod Koul:
- dw-edma fixes to improve driver and remote HDMA setup
- fsl-edma fixes for SoC hange, irq init and byte calculations and
sparse fixes
- idxd: safe user copy of completion record fix
- ptdma: consistent DMA mask fix
* tag 'dmaengine-fix2-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
dmaengine: ptdma: use consistent DMA masks
dmaengine: fsl-qdma: add __iomem and struct in union to fix sparse warning
dmaengine: idxd: Ensure safe user copy of completion record
dmaengine: fsl-edma: correct max_segment_size setting
dmaengine: idxd: Remove shadow Event Log head stored in idxd
dmaengine: fsl-edma: correct calculation of 'nbytes' in multi-fifo scenario
dmaengine: fsl-qdma: init irq after reg initialization
dmaengine: fsl-qdma: fix SoC may hang on 16 byte unaligned read
dmaengine: dw-edma: eDMA: Add sync read before starting the DMA transfer in remote setup
dmaengine: dw-edma: HDMA: Add sync read before starting the DMA transfer in remote setup
dmaengine: dw-edma: Add HDMA remote interrupt configuration
dmaengine: dw-edma: HDMA_V0_REMOTEL_STOP_INT_EN typo fix
dmaengine: dw-edma: Fix wrong interrupt bit set for HDMA
dmaengine: dw-edma: Fix the ch_count hdma callback
+86
-48
+17
drivers/dma/dw-edma/dw-edma-v0-core.c
+17
drivers/dma/dw-edma/dw-edma-v0-core.c
···
346
346
dw_edma_v0_write_ll_link(chunk, i, control, chunk->ll_region.paddr);
347
347
}
348
348
349
+
static void dw_edma_v0_sync_ll_data(struct dw_edma_chunk *chunk)
350
+
{
351
+
/*
352
+
* In case of remote eDMA engine setup, the DW PCIe RP/EP internal
353
+
* configuration registers and application memory are normally accessed
354
+
* over different buses. Ensure LL-data reaches the memory before the
355
+
* doorbell register is toggled by issuing the dummy-read from the remote
356
+
* LL memory in a hope that the MRd TLP will return only after the
357
+
* last MWr TLP is completed
358
+
*/
359
+
if (!(chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL))
360
+
readl(chunk->ll_region.vaddr.io);
361
+
}
362
+
349
363
static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
350
364
{
351
365
struct dw_edma_chan *chan = chunk->chan;
···
426
412
SET_CH_32(dw, chan->dir, chan->id, llp.msb,
427
413
upper_32_bits(chunk->ll_region.paddr));
428
414
}
415
+
416
+
dw_edma_v0_sync_ll_data(chunk);
417
+
429
418
/* Doorbell */
430
419
SET_RW_32(dw, chan->dir, doorbell,
431
420
FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id));
+26
-13
drivers/dma/dw-edma/dw-hdma-v0-core.c
+26
-13
drivers/dma/dw-edma/dw-hdma-v0-core.c
···
65
65
66
66
static u16 dw_hdma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
67
67
{
68
-
u32 num_ch = 0;
69
-
int id;
70
-
71
-
for (id = 0; id < HDMA_V0_MAX_NR_CH; id++) {
72
-
if (GET_CH_32(dw, id, dir, ch_en) & BIT(0))
73
-
num_ch++;
74
-
}
75
-
76
-
if (num_ch > HDMA_V0_MAX_NR_CH)
77
-
num_ch = HDMA_V0_MAX_NR_CH;
78
-
79
-
return (u16)num_ch;
68
+
/*
69
+
* The HDMA IP have no way to know the number of hardware channels
70
+
* available, we set it to maximum channels and let the platform
71
+
* set the right number of channels.
72
+
*/
73
+
return HDMA_V0_MAX_NR_CH;
80
74
}
81
75
82
76
static enum dma_status dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan)
···
222
228
dw_hdma_v0_write_ll_link(chunk, i, control, chunk->ll_region.paddr);
223
229
}
224
230
231
+
static void dw_hdma_v0_sync_ll_data(struct dw_edma_chunk *chunk)
232
+
{
233
+
/*
234
+
* In case of remote HDMA engine setup, the DW PCIe RP/EP internal
235
+
* configuration registers and application memory are normally accessed
236
+
* over different buses. Ensure LL-data reaches the memory before the
237
+
* doorbell register is toggled by issuing the dummy-read from the remote
238
+
* LL memory in a hope that the MRd TLP will return only after the
239
+
* last MWr TLP is completed
240
+
*/
241
+
if (!(chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL))
242
+
readl(chunk->ll_region.vaddr.io);
243
+
}
244
+
225
245
static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
226
246
{
227
247
struct dw_edma_chan *chan = chunk->chan;
···
250
242
/* Interrupt enable&unmask - done, abort */
251
243
tmp = GET_CH_32(dw, chan->dir, chan->id, int_setup) |
252
244
HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK |
253
-
HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_LOCAL_STOP_INT_EN;
245
+
HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_LOCAL_ABORT_INT_EN;
246
+
if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL))
247
+
tmp |= HDMA_V0_REMOTE_STOP_INT_EN | HDMA_V0_REMOTE_ABORT_INT_EN;
254
248
SET_CH_32(dw, chan->dir, chan->id, int_setup, tmp);
255
249
/* Channel control */
256
250
SET_CH_32(dw, chan->dir, chan->id, control1, HDMA_V0_LINKLIST_EN);
···
266
256
/* Set consumer cycle */
267
257
SET_CH_32(dw, chan->dir, chan->id, cycle_sync,
268
258
HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT);
259
+
260
+
dw_hdma_v0_sync_ll_data(chunk);
261
+
269
262
/* Doorbell */
270
263
SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START);
271
264
}
+1
-1
drivers/dma/dw-edma/dw-hdma-v0-regs.h
+1
-1
drivers/dma/dw-edma/dw-hdma-v0-regs.h
···
15
15
#define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6)
16
16
#define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5)
17
17
#define HDMA_V0_LOCAL_STOP_INT_EN BIT(4)
18
-
#define HDMA_V0_REMOTEL_STOP_INT_EN BIT(3)
18
+
#define HDMA_V0_REMOTE_STOP_INT_EN BIT(3)
19
19
#define HDMA_V0_ABORT_INT_MASK BIT(2)
20
20
#define HDMA_V0_STOP_INT_MASK BIT(0)
21
21
#define HDMA_V0_LINKLIST_EN BIT(0)
+1
-1
drivers/dma/fsl-edma-common.c
+1
-1
drivers/dma/fsl-edma-common.c
···
503
503
if (fsl_chan->is_multi_fifo) {
504
504
/* set mloff to support multiple fifo */
505
505
burst = cfg->direction == DMA_DEV_TO_MEM ?
506
-
cfg->src_addr_width : cfg->dst_addr_width;
506
+
cfg->src_maxburst : cfg->dst_maxburst;
507
507
nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4));
508
508
/* enable DMLOE/SMLOE */
509
509
if (cfg->direction == DMA_MEM_TO_DEV) {
+3
-2
drivers/dma/fsl-edma-common.h
+3
-2
drivers/dma/fsl-edma-common.h
···
30
30
#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
31
31
#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
32
32
33
-
#define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0))
34
-
#define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0))
33
+
#define EDMA_TCD_ITER_MASK GENMASK(14, 0)
34
+
#define EDMA_TCD_CITER_CITER(x) ((x) & EDMA_TCD_ITER_MASK)
35
+
#define EDMA_TCD_BITER_BITER(x) ((x) & EDMA_TCD_ITER_MASK)
35
36
36
37
#define EDMA_TCD_CSR_START BIT(0)
37
38
#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
+3
-1
drivers/dma/fsl-edma-main.c
+3
-1
drivers/dma/fsl-edma-main.c
···
10
10
*/
11
11
12
12
#include <dt-bindings/dma/fsl-edma.h>
13
+
#include <linux/bitfield.h>
13
14
#include <linux/module.h>
14
15
#include <linux/interrupt.h>
15
16
#include <linux/clk.h>
···
583
582
DMAENGINE_ALIGN_32_BYTES;
584
583
585
584
/* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
586
-
dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff);
585
+
dma_set_max_seg_size(fsl_edma->dma_dev.dev,
586
+
FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK));
587
587
588
588
fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
589
589
+20
-20
drivers/dma/fsl-qdma.c
+20
-20
drivers/dma/fsl-qdma.c
···
109
109
#define FSL_QDMA_CMD_WTHROTL_OFFSET 20
110
110
#define FSL_QDMA_CMD_DSEN_OFFSET 19
111
111
#define FSL_QDMA_CMD_LWC_OFFSET 16
112
+
#define FSL_QDMA_CMD_PF BIT(17)
112
113
113
114
/* Field definition for Descriptor status */
114
115
#define QDMA_CCDF_STATUS_RTE BIT(5)
···
160
159
u8 addr_hi;
161
160
u8 __reserved1[2];
162
161
u8 cfg8b_w1;
162
+
} __packed;
163
+
struct {
164
+
__le32 __reserved2;
165
+
__le32 cmd;
163
166
} __packed;
164
167
__le64 data;
165
168
};
···
359
354
static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
360
355
dma_addr_t dst, dma_addr_t src, u32 len)
361
356
{
362
-
u32 cmd;
363
357
struct fsl_qdma_format *sdf, *ddf;
364
358
struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
365
359
···
387
383
/* This entry is the last entry. */
388
384
qdma_csgf_set_f(csgf_dest, len);
389
385
/* Descriptor Buffer */
390
-
cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
391
-
FSL_QDMA_CMD_RWTTYPE_OFFSET);
392
-
sdf->data = QDMA_SDDF_CMD(cmd);
386
+
sdf->cmd = cpu_to_le32((FSL_QDMA_CMD_RWTTYPE << FSL_QDMA_CMD_RWTTYPE_OFFSET) |
387
+
FSL_QDMA_CMD_PF);
393
388
394
-
cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
395
-
FSL_QDMA_CMD_RWTTYPE_OFFSET);
396
-
cmd |= cpu_to_le32(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
397
-
ddf->data = QDMA_SDDF_CMD(cmd);
389
+
ddf->cmd = cpu_to_le32((FSL_QDMA_CMD_RWTTYPE << FSL_QDMA_CMD_RWTTYPE_OFFSET) |
390
+
(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET));
398
391
}
399
392
400
393
/*
···
625
624
626
625
static int
627
626
fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,
628
-
void *block,
627
+
__iomem void *block,
629
628
int id)
630
629
{
631
630
bool duplicate;
···
1197
1196
if (!fsl_qdma->queue)
1198
1197
return -ENOMEM;
1199
1198
1200
-
ret = fsl_qdma_irq_init(pdev, fsl_qdma);
1201
-
if (ret)
1202
-
return ret;
1203
-
1204
1199
fsl_qdma->irq_base = platform_get_irq_byname(pdev, "qdma-queue0");
1205
1200
if (fsl_qdma->irq_base < 0)
1206
1201
return fsl_qdma->irq_base;
···
1235
1238
1236
1239
platform_set_drvdata(pdev, fsl_qdma);
1237
1240
1238
-
ret = dma_async_device_register(&fsl_qdma->dma_dev);
1239
-
if (ret) {
1240
-
dev_err(&pdev->dev,
1241
-
"Can't register NXP Layerscape qDMA engine.\n");
1242
-
return ret;
1243
-
}
1244
-
1245
1241
ret = fsl_qdma_reg_init(fsl_qdma);
1246
1242
if (ret) {
1247
1243
dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
1244
+
return ret;
1245
+
}
1246
+
1247
+
ret = fsl_qdma_irq_init(pdev, fsl_qdma);
1248
+
if (ret)
1249
+
return ret;
1250
+
1251
+
ret = dma_async_device_register(&fsl_qdma->dma_dev);
1252
+
if (ret) {
1253
+
dev_err(&pdev->dev, "Can't register NXP Layerscape qDMA engine.\n");
1248
1254
return ret;
1249
1255
}
1250
1256
+1
-1
drivers/dma/idxd/cdev.c
+1
-1
drivers/dma/idxd/cdev.c
+1
-1
drivers/dma/idxd/debugfs.c
+1
-1
drivers/dma/idxd/debugfs.c
-1
drivers/dma/idxd/idxd.h
-1
drivers/dma/idxd/idxd.h
+12
-3
drivers/dma/idxd/init.c
+12
-3
drivers/dma/idxd/init.c
···
343
343
static int idxd_init_evl(struct idxd_device *idxd)
344
344
{
345
345
struct device *dev = &idxd->pdev->dev;
346
+
unsigned int evl_cache_size;
346
347
struct idxd_evl *evl;
348
+
const char *idxd_name;
347
349
348
350
if (idxd->hw.gen_cap.evl_support == 0)
349
351
return 0;
···
357
355
spin_lock_init(&evl->lock);
358
356
evl->size = IDXD_EVL_SIZE_MIN;
359
357
360
-
idxd->evl_cache = kmem_cache_create(dev_name(idxd_confdev(idxd)),
361
-
sizeof(struct idxd_evl_fault) + evl_ent_size(idxd),
362
-
0, 0, NULL);
358
+
idxd_name = dev_name(idxd_confdev(idxd));
359
+
evl_cache_size = sizeof(struct idxd_evl_fault) + evl_ent_size(idxd);
360
+
/*
361
+
* Since completion record in evl_cache will be copied to user
362
+
* when handling completion record page fault, need to create
363
+
* the cache suitable for user copy.
364
+
*/
365
+
idxd->evl_cache = kmem_cache_create_usercopy(idxd_name, evl_cache_size,
366
+
0, 0, 0, evl_cache_size,
367
+
NULL);
363
368
if (!idxd->evl_cache) {
364
369
kfree(evl);
365
370
return -ENOMEM;
+1
-2
drivers/dma/idxd/irq.c
+1
-2
drivers/dma/idxd/irq.c
···
367
367
/* Clear interrupt pending bit */
368
368
iowrite32(evl_status.bits_upper32,
369
369
idxd->reg_base + IDXD_EVLSTATUS_OFFSET + sizeof(u32));
370
-
h = evl->head;
371
370
evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
372
371
t = evl_status.tail;
372
+
h = evl_status.head;
373
373
size = idxd->evl->size;
374
374
375
375
while (h != t) {
···
378
378
h = (h + 1) % size;
379
379
}
380
380
381
-
evl->head = h;
382
381
evl_status.head = h;
383
382
iowrite32(evl_status.bits_lower32, idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
384
383
spin_unlock(&evl->lock);