Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pmdomain-v7.0-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain fixes from Ulf Hansson:
- imx: Prevent hang at power down for imx8mp-blk-ctrl
- thead: Fix buffer overflow for TH1520 AON driver
- Change Ulf Hansson's email
* tag 'pmdomain-v7.0-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm:
MAINTAINERS, mailmap: Change Ulf Hansson's email
pmdomain: imx8mp-blk-ctrl: Keep the NOC_HDCP clock enabled
firmware: thead: Fix buffer overflow and use standard endian macros
+13
-92
+2
.mailmap
+2
.mailmap
···
849
849
Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko@ursulin.net>
850
850
Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws>
851
851
Tzung-Bi Shih <tzungbi@kernel.org> <tzungbi@google.com>
852
+
Ulf Hansson <ulfh@kernel.org> <ulf.hansson@linaro.org>
853
+
Ulf Hansson <ulfh@kernel.org> <ulf.hansson@stericsson.com>
852
854
Umang Jain <uajain@igalia.com> <umang.jain@ideasonboard.com>
853
855
Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
854
856
Uwe Kleine-König <u.kleine-koenig@baylibre.com> <ukleinek@baylibre.com>
+7
-7
MAINTAINERS
+7
-7
MAINTAINERS
···
6717
6717
CPUIDLE DRIVER - ARM PSCI
6718
6718
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
6719
6719
M: Sudeep Holla <sudeep.holla@kernel.org>
6720
-
M: Ulf Hansson <ulf.hansson@linaro.org>
6720
+
M: Ulf Hansson <ulfh@kernel.org>
6721
6721
L: linux-pm@vger.kernel.org
6722
6722
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6723
6723
S: Supported
···
6725
6725
F: drivers/cpuidle/cpuidle-psci.c
6726
6726
6727
6727
CPUIDLE DRIVER - ARM PSCI PM DOMAIN
6728
-
M: Ulf Hansson <ulf.hansson@linaro.org>
6728
+
M: Ulf Hansson <ulfh@kernel.org>
6729
6729
L: linux-pm@vger.kernel.org
6730
6730
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6731
6731
S: Supported
···
6734
6734
F: drivers/cpuidle/cpuidle-psci.h
6735
6735
6736
6736
CPUIDLE DRIVER - DT IDLE PM DOMAIN
6737
-
M: Ulf Hansson <ulf.hansson@linaro.org>
6737
+
M: Ulf Hansson <ulfh@kernel.org>
6738
6738
L: linux-pm@vger.kernel.org
6739
6739
S: Supported
6740
6740
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git
···
10730
10730
F: drivers/i2c/muxes/i2c-demux-pinctrl.c
10731
10731
10732
10732
GENERIC PM DOMAINS
10733
-
M: Ulf Hansson <ulf.hansson@linaro.org>
10733
+
M: Ulf Hansson <ulfh@kernel.org>
10734
10734
L: linux-pm@vger.kernel.org
10735
10735
S: Supported
10736
10736
F: Documentation/devicetree/bindings/power/power?domain*
···
18090
18090
F: include/linux/spi/mmc_spi.h
18091
18091
18092
18092
MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM
18093
-
M: Ulf Hansson <ulf.hansson@linaro.org>
18093
+
M: Ulf Hansson <ulfh@kernel.org>
18094
18094
L: linux-mmc@vger.kernel.org
18095
18095
S: Maintained
18096
18096
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git
···
24696
24696
SONY MEMORYSTICK SUBSYSTEM
24697
24697
M: Maxim Levitsky <maximlevitsky@gmail.com>
24698
24698
M: Alex Dubov <oakad@yahoo.com>
24699
-
M: Ulf Hansson <ulf.hansson@linaro.org>
24699
+
M: Ulf Hansson <ulfh@kernel.org>
24700
24700
L: linux-mmc@vger.kernel.org
24701
24701
S: Maintained
24702
24702
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git
···
27615
27615
F: drivers/video/fbdev/uvesafb.*
27616
27616
27617
27617
Ux500 CLOCK DRIVERS
27618
-
M: Ulf Hansson <ulf.hansson@linaro.org>
27618
+
M: Ulf Hansson <ulfh@kernel.org>
27619
27619
L: linux-clk@vger.kernel.org
27620
27620
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
27621
27621
S: Maintained
+3
-4
drivers/firmware/thead,th1520-aon.c
+3
-4
drivers/firmware/thead,th1520-aon.c
···
170
170
hdr->func = TH1520_AON_PM_FUNC_SET_RESOURCE_POWER_MODE;
171
171
hdr->size = TH1520_AON_RPC_MSG_NUM;
172
172
173
-
RPC_SET_BE16(&msg.resource, 0, rsrc);
174
-
RPC_SET_BE16(&msg.resource, 2,
175
-
(power_on ? TH1520_AON_PM_PW_MODE_ON :
176
-
TH1520_AON_PM_PW_MODE_OFF));
173
+
msg.resource = cpu_to_be16(rsrc);
174
+
msg.mode = cpu_to_be16(power_on ? TH1520_AON_PM_PW_MODE_ON :
175
+
TH1520_AON_PM_PW_MODE_OFF);
177
176
178
177
ret = th1520_aon_call_rpc(aon_chan, &msg);
179
178
if (ret)
+1
-7
drivers/pmdomain/imx/imx8mp-blk-ctrl.c
+1
-7
drivers/pmdomain/imx/imx8mp-blk-ctrl.c
···
352
352
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
353
353
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
354
354
break;
355
-
case IMX8MP_HDMIBLK_PD_HDCP:
356
-
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
357
-
break;
358
355
case IMX8MP_HDMIBLK_PD_HRV:
359
356
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
360
357
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
···
405
408
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
406
409
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
407
410
break;
408
-
case IMX8MP_HDMIBLK_PD_HDCP:
409
-
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
410
-
break;
411
411
case IMX8MP_HDMIBLK_PD_HRV:
412
412
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
413
413
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
···
433
439
regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
434
440
regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
435
441
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
436
-
BIT(0) | BIT(1) | BIT(10));
442
+
BIT(0) | BIT(1) | BIT(10) | BIT(11));
437
443
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
438
444
439
445
/*
-74
include/linux/firmware/thead/thead,th1520-aon.h
-74
include/linux/firmware/thead/thead,th1520-aon.h
···
97
97
#define RPC_GET_SVC_FLAG_ACK_TYPE(MESG) (((MESG)->svc & 0x40) >> 6)
98
98
#define RPC_SET_SVC_FLAG_ACK_TYPE(MESG, ACK) ((MESG)->svc |= (ACK) << 6)
99
99
100
-
#define RPC_SET_BE64(MESG, OFFSET, SET_DATA) \
101
-
do { \
102
-
u8 *data = (u8 *)(MESG); \
103
-
u64 _offset = (OFFSET); \
104
-
u64 _set_data = (SET_DATA); \
105
-
data[_offset + 7] = _set_data & 0xFF; \
106
-
data[_offset + 6] = (_set_data & 0xFF00) >> 8; \
107
-
data[_offset + 5] = (_set_data & 0xFF0000) >> 16; \
108
-
data[_offset + 4] = (_set_data & 0xFF000000) >> 24; \
109
-
data[_offset + 3] = (_set_data & 0xFF00000000) >> 32; \
110
-
data[_offset + 2] = (_set_data & 0xFF0000000000) >> 40; \
111
-
data[_offset + 1] = (_set_data & 0xFF000000000000) >> 48; \
112
-
data[_offset + 0] = (_set_data & 0xFF00000000000000) >> 56; \
113
-
} while (0)
114
-
115
-
#define RPC_SET_BE32(MESG, OFFSET, SET_DATA) \
116
-
do { \
117
-
u8 *data = (u8 *)(MESG); \
118
-
u64 _offset = (OFFSET); \
119
-
u64 _set_data = (SET_DATA); \
120
-
data[_offset + 3] = (_set_data) & 0xFF; \
121
-
data[_offset + 2] = (_set_data & 0xFF00) >> 8; \
122
-
data[_offset + 1] = (_set_data & 0xFF0000) >> 16; \
123
-
data[_offset + 0] = (_set_data & 0xFF000000) >> 24; \
124
-
} while (0)
125
-
126
-
#define RPC_SET_BE16(MESG, OFFSET, SET_DATA) \
127
-
do { \
128
-
u8 *data = (u8 *)(MESG); \
129
-
u64 _offset = (OFFSET); \
130
-
u64 _set_data = (SET_DATA); \
131
-
data[_offset + 1] = (_set_data) & 0xFF; \
132
-
data[_offset + 0] = (_set_data & 0xFF00) >> 8; \
133
-
} while (0)
134
-
135
-
#define RPC_SET_U8(MESG, OFFSET, SET_DATA) \
136
-
do { \
137
-
u8 *data = (u8 *)(MESG); \
138
-
data[OFFSET] = (SET_DATA) & 0xFF; \
139
-
} while (0)
140
-
141
-
#define RPC_GET_BE64(MESG, OFFSET, PTR) \
142
-
do { \
143
-
u8 *data = (u8 *)(MESG); \
144
-
u64 _offset = (OFFSET); \
145
-
*(u32 *)(PTR) = \
146
-
(data[_offset + 7] | data[_offset + 6] << 8 | \
147
-
data[_offset + 5] << 16 | data[_offset + 4] << 24 | \
148
-
data[_offset + 3] << 32 | data[_offset + 2] << 40 | \
149
-
data[_offset + 1] << 48 | data[_offset + 0] << 56); \
150
-
} while (0)
151
-
152
-
#define RPC_GET_BE32(MESG, OFFSET, PTR) \
153
-
do { \
154
-
u8 *data = (u8 *)(MESG); \
155
-
u64 _offset = (OFFSET); \
156
-
*(u32 *)(PTR) = \
157
-
(data[_offset + 3] | data[_offset + 2] << 8 | \
158
-
data[_offset + 1] << 16 | data[_offset + 0] << 24); \
159
-
} while (0)
160
-
161
-
#define RPC_GET_BE16(MESG, OFFSET, PTR) \
162
-
do { \
163
-
u8 *data = (u8 *)(MESG); \
164
-
u64 _offset = (OFFSET); \
165
-
*(u16 *)(PTR) = (data[_offset + 1] | data[_offset + 0] << 8); \
166
-
} while (0)
167
-
168
-
#define RPC_GET_U8(MESG, OFFSET, PTR) \
169
-
do { \
170
-
u8 *data = (u8 *)(MESG); \
171
-
*(u8 *)(PTR) = (data[OFFSET]); \
172
-
} while (0)
173
-
174
100
/*
175
101
* Defines for SC PM Power Mode
176
102
*/