tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x

On Navi1x, the SPM golden settings are lost after GFXOFF
enter/exit, so reconfiguration is needed. Make the
configuration code as an interface for future use.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Tianci.Yin and committed by
Alex Deucher d58fe3cf 66459e1d

+27 -9
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
··· 216 216 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if); 217 217 int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status); 218 218 void (*reset_ras_error_count) (struct amdgpu_device *adev); 219 + void (*init_spm_golden)(struct amdgpu_device *adev); 219 220 }; 220 221 221 222 struct sq_work { ··· 325 324 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 326 325 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 327 326 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 327 + #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 328 328 329 329 /** 330 330 * amdgpu_gfx_create_bitmask - create a bitmask
+25 -9
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 3307 3307 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3308 3308 } 3309 3309 3310 + static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3311 + { 3312 + switch (adev->asic_type) { 3313 + case CHIP_NAVI10: 3314 + soc15_program_register_sequence(adev, 3315 + golden_settings_gc_rlc_spm_10_0_nv10, 3316 + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3317 + break; 3318 + case CHIP_NAVI14: 3319 + soc15_program_register_sequence(adev, 3320 + golden_settings_gc_rlc_spm_10_1_nv14, 3321 + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3322 + break; 3323 + case CHIP_NAVI12: 3324 + soc15_program_register_sequence(adev, 3325 + golden_settings_gc_rlc_spm_10_1_2_nv12, 3326 + (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3327 + break; 3328 + default: 3329 + break; 3330 + } 3331 + } 3332 + 3310 3333 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3311 3334 { 3312 3335 switch (adev->asic_type) { ··· 3340 3317 soc15_program_register_sequence(adev, 3341 3318 golden_settings_gc_10_0_nv10, 3342 3319 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3343 - soc15_program_register_sequence(adev, 3344 - golden_settings_gc_rlc_spm_10_0_nv10, 3345 - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3346 3320 break; 3347 3321 case CHIP_NAVI14: 3348 3322 soc15_program_register_sequence(adev, ··· 3348 3328 soc15_program_register_sequence(adev, 3349 3329 golden_settings_gc_10_1_nv14, 3350 3330 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3351 - soc15_program_register_sequence(adev, 3352 - golden_settings_gc_rlc_spm_10_1_nv14, 3353 - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3354 3331 break; 3355 3332 case CHIP_NAVI12: 3356 3333 soc15_program_register_sequence(adev, ··· 3356 3339 soc15_program_register_sequence(adev, 3357 3340 golden_settings_gc_10_1_2_nv12, 3358 3341 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3359 - soc15_program_register_sequence(adev, 3360 - golden_settings_gc_rlc_spm_10_1_2_nv12, 3361 - (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3362 3342 break; 3363 3343 case CHIP_SIENNA_CICHLID: 3364 3344 soc15_program_register_sequence(adev, ··· 3374 3360 default: 3375 3361 break; 3376 3362 } 3363 + gfx_v10_0_init_spm_golden_registers(adev); 3377 3364 } 3378 3365 3379 3366 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) ··· 4164 4149 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4165 4150 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4166 4151 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4152 + .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4167 4153 }; 4168 4154 4169 4155 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)