Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A few driver fixes for tegra, rockchip, and st SoCs and a two-liner in
the framework to avoid oops when get_parent ops return out of range
values on tegra platforms"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
clk: check for invalid parent index of orphans in __clk_init()
clk: tegra: dfll: Properly protect OPP list
clk: rockchip: add critical clock for rk3368
+25
-12
+2
-1
drivers/clk/clk.c
+2
-1
drivers/clk/clk.c
···
2437
2437
hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
2438
2438
if (orphan->num_parents && orphan->ops->get_parent) {
2439
2439
i = orphan->ops->get_parent(orphan->hw);
2440
-
if (!strcmp(core->name, orphan->parent_names[i]))
2440
+
if (i >= 0 && i < orphan->num_parents &&
2441
+
!strcmp(core->name, orphan->parent_names[i]))
2441
2442
clk_core_reparent(orphan, core);
2442
2443
continue;
2443
2444
}
+6
drivers/clk/rockchip/clk-rk3368.c
+6
drivers/clk/rockchip/clk-rk3368.c
···
818
818
GATE(0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
819
819
};
820
820
821
+
static const char *const rk3368_critical_clocks[] __initconst = {
822
+
"pclk_pd_pmu",
823
+
};
824
+
821
825
static void __init rk3368_clk_init(struct device_node *np)
822
826
{
823
827
void __iomem *reg_base;
···
866
862
RK3368_GRF_SOC_STATUS0);
867
863
rockchip_clk_register_branches(rk3368_clk_branches,
868
864
ARRAY_SIZE(rk3368_clk_branches));
865
+
rockchip_clk_protect_critical(rk3368_critical_clocks,
866
+
ARRAY_SIZE(rk3368_critical_clocks));
869
867
870
868
rockchip_clk_register_armclk(ARMCLKB, "armclkb",
871
869
mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
+4
-4
drivers/clk/st/clkgen-fsyn.c
+4
-4
drivers/clk/st/clkgen-fsyn.c
···
307
307
.get_rate = clk_fs660c32_dig_get_rate,
308
308
};
309
309
310
-
static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
310
+
static const struct clkgen_quadfs_data st_fs660c32_C = {
311
311
.nrst_present = true,
312
312
.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
313
313
CLKGEN_FIELD(0x2f0, 0x1, 1),
···
350
350
.get_rate = clk_fs660c32_dig_get_rate,
351
351
};
352
352
353
-
static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
353
+
static const struct clkgen_quadfs_data st_fs660c32_D = {
354
354
.nrst_present = true,
355
355
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
356
356
CLKGEN_FIELD(0x2a0, 0x1, 1),
···
1077
1077
},
1078
1078
{
1079
1079
.compatible = "st,stih407-quadfs660-C",
1080
-
.data = &st_fs660c32_C_407
1080
+
.data = &st_fs660c32_C
1081
1081
},
1082
1082
{
1083
1083
.compatible = "st,stih407-quadfs660-D",
1084
-
.data = &st_fs660c32_D_407
1084
+
.data = &st_fs660c32_D
1085
1085
},
1086
1086
{}
1087
1087
};
+6
-6
drivers/clk/st/clkgen-pll.c
+6
-6
drivers/clk/st/clkgen-pll.c
···
193
193
.ops = &stm_pll3200c32_ops,
194
194
};
195
195
196
-
static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
196
+
static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
197
197
/* 407 C0 PLL0 */
198
198
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
199
199
.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
···
205
205
.ops = &stm_pll3200c32_ops,
206
206
};
207
207
208
-
static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
208
+
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
209
209
/* 407 C0 PLL1 */
210
210
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
211
211
.locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
···
624
624
.data = &st_pll3200c32_407_a0,
625
625
},
626
626
{
627
-
.compatible = "st,stih407-plls-c32-c0_0",
628
-
.data = &st_pll3200c32_407_c0_0,
627
+
.compatible = "st,plls-c32-cx_0",
628
+
.data = &st_pll3200c32_cx_0,
629
629
},
630
630
{
631
-
.compatible = "st,stih407-plls-c32-c0_1",
632
-
.data = &st_pll3200c32_407_c0_1,
631
+
.compatible = "st,plls-c32-cx_1",
632
+
.data = &st_pll3200c32_cx_1,
633
633
},
634
634
{
635
635
.compatible = "st,stih407-plls-c32-a9",
+7
-1
drivers/clk/tegra/clk-dfll.c
+7
-1
drivers/clk/tegra/clk-dfll.c
···
682
682
struct dev_pm_opp *opp;
683
683
int i, uv;
684
684
685
+
rcu_read_lock();
686
+
685
687
opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
686
-
if (IS_ERR(opp))
688
+
if (IS_ERR(opp)) {
689
+
rcu_read_unlock();
687
690
return PTR_ERR(opp);
691
+
}
688
692
uv = dev_pm_opp_get_voltage(opp);
693
+
694
+
rcu_read_unlock();
689
695
690
696
for (i = 0; i < td->i2c_lut_size; i++) {
691
697
if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv)