Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-fix-v6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A series of fixes that came in since the merge window, the main thing
being the fixes Andy did for DMA sync where we were calling into the
DMA API in suprising ways and causing issues as a result, the main
thing being confusing the IOMMU code.
We've also got some fairly important fixes for the stm32 driver, it
supports a wide range of hardware and some optimisations that were
done recently have broken on some systems, and a fix to prevent
glitched signals on the bus in the cadence driver"
* tag 'spi-fix-v6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: stm32: Don't warn about spurious interrupts
spi: Assign dummy scatterlist to unidirectional transfers
spi: cadence: Ensure data lines set to low during dummy-cycle period
spi: stm32: Revert change that enabled controller before asserting CS
spi: Check if transfer is mapped before calling DMA sync APIs
spi: Don't mark message DMA mapped when no transfer in it is
+54
-13
+15
-5
drivers/spi/spi-cadence-xspi.c
+15
-5
drivers/spi/spi-cadence-xspi.c
···
145
145
#define CDNS_XSPI_STIG_DONE_FLAG BIT(0)
146
146
#define CDNS_XSPI_TRD_STATUS 0x0104
147
147
148
+
#define MODE_NO_OF_BYTES GENMASK(25, 24)
149
+
#define MODEBYTES_COUNT 1
150
+
148
151
/* Helper macros for filling command registers */
149
152
#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \
150
153
FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \
···
160
157
FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \
161
158
FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF))
162
159
163
-
#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op) ( \
160
+
#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, modebytes) ( \
164
161
FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \
165
162
FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \
163
+
FIELD_PREP(MODE_NO_OF_BYTES, modebytes) | \
166
164
FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes))
167
165
168
166
#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \
···
177
173
#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \
178
174
FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF)
179
175
180
-
#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \
176
+
#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes) ( \
181
177
FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \
182
178
((op)->data.nbytes >> 16) & 0xffff) | \
183
179
FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \
184
180
(op)->dummy.buswidth != 0 ? \
185
-
(((op)->dummy.nbytes * 8) / (op)->dummy.buswidth) : \
181
+
(((dummybytes) * 8) / (op)->dummy.buswidth) : \
186
182
0))
187
183
188
184
#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \
···
355
351
u32 cmd_regs[6];
356
352
u32 cmd_status;
357
353
int ret;
354
+
int dummybytes = op->dummy.nbytes;
358
355
359
356
ret = cdns_xspi_wait_for_controller_idle(cdns_xspi);
360
357
if (ret < 0)
···
370
365
memset(cmd_regs, 0, sizeof(cmd_regs));
371
366
cmd_regs[1] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase);
372
367
cmd_regs[2] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op);
373
-
cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op);
368
+
if (dummybytes != 0) {
369
+
cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 1);
370
+
dummybytes--;
371
+
} else {
372
+
cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 0);
373
+
}
374
374
cmd_regs[4] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op,
375
375
cdns_xspi->cur_cs);
376
376
···
385
375
cmd_regs[0] = CDNS_XSPI_STIG_DONE_FLAG;
386
376
cmd_regs[1] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op);
387
377
cmd_regs[2] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op);
388
-
cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op);
378
+
cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes);
389
379
cmd_regs[4] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op,
390
380
cdns_xspi->cur_cs);
391
381
+13
-3
drivers/spi/spi-stm32.c
+13
-3
drivers/spi/spi-stm32.c
···
1016
1016
static irqreturn_t stm32fx_spi_irq_thread(int irq, void *dev_id)
1017
1017
{
1018
1018
struct spi_controller *ctrl = dev_id;
1019
+
struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1019
1020
1020
1021
spi_finalize_current_transfer(ctrl);
1022
+
stm32fx_spi_disable(spi);
1021
1023
1022
1024
return IRQ_HANDLED;
1023
1025
}
···
1057
1055
mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
1058
1056
1059
1057
if (!(sr & mask)) {
1060
-
dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
1058
+
dev_vdbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
1061
1059
sr, ier);
1062
1060
spin_unlock_irqrestore(&spi->lock, flags);
1063
1061
return IRQ_NONE;
···
1187
1185
~clrb) | setb,
1188
1186
spi->base + spi->cfg->regs->cpol.reg);
1189
1187
1190
-
stm32_spi_enable(spi);
1191
-
1192
1188
spin_unlock_irqrestore(&spi->lock, flags);
1193
1189
1194
1190
return 0;
···
1204
1204
1205
1205
if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1206
1206
spi_finalize_current_transfer(spi->ctrl);
1207
+
stm32fx_spi_disable(spi);
1207
1208
}
1208
1209
}
1209
1210
···
1219
1218
struct stm32_spi *spi = data;
1220
1219
1221
1220
spi_finalize_current_transfer(spi->ctrl);
1221
+
spi->cfg->disable(spi);
1222
1222
}
1223
1223
1224
1224
/**
···
1307
1305
1308
1306
stm32_spi_set_bits(spi, STM32FX_SPI_CR2, cr2);
1309
1307
1308
+
stm32_spi_enable(spi);
1309
+
1310
1310
/* starting data transfer when buffer is loaded */
1311
1311
if (spi->tx_buf)
1312
1312
spi->cfg->write_tx(spi);
···
1345
1341
1346
1342
spin_lock_irqsave(&spi->lock, flags);
1347
1343
1344
+
stm32_spi_enable(spi);
1345
+
1348
1346
/* Be sure to have data in fifo before starting data transfer */
1349
1347
if (spi->tx_buf)
1350
1348
stm32h7_spi_write_txfifo(spi);
···
1378
1372
*/
1379
1373
stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_ERRIE);
1380
1374
}
1375
+
1376
+
stm32_spi_enable(spi);
1381
1377
}
1382
1378
1383
1379
/**
···
1412
1404
ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
1413
1405
1414
1406
stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1407
+
1408
+
stm32_spi_enable(spi);
1415
1409
1416
1410
if (STM32_SPI_HOST_MODE(spi))
1417
1411
stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
+26
-5
drivers/spi/spi.c
+26
-5
drivers/spi/spi.c
···
1220
1220
spi_unmap_buf_attrs(ctlr, dev, sgt, dir, 0);
1221
1221
}
1222
1222
1223
+
/* Dummy SG for unidirect transfers */
1224
+
static struct scatterlist dummy_sg = {
1225
+
.page_link = SG_END,
1226
+
};
1227
+
1223
1228
static int __spi_map_msg(struct spi_controller *ctlr, struct spi_message *msg)
1224
1229
{
1225
1230
struct device *tx_dev, *rx_dev;
···
1248
1243
else
1249
1244
rx_dev = ctlr->dev.parent;
1250
1245
1246
+
ret = -ENOMSG;
1251
1247
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1252
1248
/* The sync is done before each transfer. */
1253
1249
unsigned long attrs = DMA_ATTR_SKIP_CPU_SYNC;
···
1263
1257
attrs);
1264
1258
if (ret != 0)
1265
1259
return ret;
1260
+
} else {
1261
+
xfer->tx_sg.sgl = &dummy_sg;
1266
1262
}
1267
1263
1268
1264
if (xfer->rx_buf != NULL) {
···
1278
1270
1279
1271
return ret;
1280
1272
}
1273
+
} else {
1274
+
xfer->rx_sg.sgl = &dummy_sg;
1281
1275
}
1282
1276
}
1277
+
/* No transfer has been mapped, bail out with success */
1278
+
if (ret)
1279
+
return 0;
1283
1280
1284
1281
ctlr->cur_rx_dma_dev = rx_dev;
1285
1282
ctlr->cur_tx_dma_dev = tx_dev;
···
1320
1307
return 0;
1321
1308
}
1322
1309
1323
-
static void spi_dma_sync_for_device(struct spi_controller *ctlr,
1310
+
static void spi_dma_sync_for_device(struct spi_controller *ctlr, struct spi_message *msg,
1324
1311
struct spi_transfer *xfer)
1325
1312
{
1326
1313
struct device *rx_dev = ctlr->cur_rx_dma_dev;
···
1329
1316
if (!ctlr->cur_msg_mapped)
1330
1317
return;
1331
1318
1319
+
if (!ctlr->can_dma(ctlr, msg->spi, xfer))
1320
+
return;
1321
+
1332
1322
dma_sync_sgtable_for_device(tx_dev, &xfer->tx_sg, DMA_TO_DEVICE);
1333
1323
dma_sync_sgtable_for_device(rx_dev, &xfer->rx_sg, DMA_FROM_DEVICE);
1334
1324
}
1335
1325
1336
-
static void spi_dma_sync_for_cpu(struct spi_controller *ctlr,
1326
+
static void spi_dma_sync_for_cpu(struct spi_controller *ctlr, struct spi_message *msg,
1337
1327
struct spi_transfer *xfer)
1338
1328
{
1339
1329
struct device *rx_dev = ctlr->cur_rx_dma_dev;
1340
1330
struct device *tx_dev = ctlr->cur_tx_dma_dev;
1341
1331
1342
1332
if (!ctlr->cur_msg_mapped)
1333
+
return;
1334
+
1335
+
if (!ctlr->can_dma(ctlr, msg->spi, xfer))
1343
1336
return;
1344
1337
1345
1338
dma_sync_sgtable_for_cpu(rx_dev, &xfer->rx_sg, DMA_FROM_DEVICE);
···
1365
1346
}
1366
1347
1367
1348
static void spi_dma_sync_for_device(struct spi_controller *ctrl,
1349
+
struct spi_message *msg,
1368
1350
struct spi_transfer *xfer)
1369
1351
{
1370
1352
}
1371
1353
1372
1354
static void spi_dma_sync_for_cpu(struct spi_controller *ctrl,
1355
+
struct spi_message *msg,
1373
1356
struct spi_transfer *xfer)
1374
1357
{
1375
1358
}
···
1643
1622
reinit_completion(&ctlr->xfer_completion);
1644
1623
1645
1624
fallback_pio:
1646
-
spi_dma_sync_for_device(ctlr, xfer);
1625
+
spi_dma_sync_for_device(ctlr, msg, xfer);
1647
1626
ret = ctlr->transfer_one(ctlr, msg->spi, xfer);
1648
1627
if (ret < 0) {
1649
-
spi_dma_sync_for_cpu(ctlr, xfer);
1628
+
spi_dma_sync_for_cpu(ctlr, msg, xfer);
1650
1629
1651
1630
if (ctlr->cur_msg_mapped &&
1652
1631
(xfer->error & SPI_TRANS_FAIL_NO_START)) {
···
1671
1650
msg->status = ret;
1672
1651
}
1673
1652
1674
-
spi_dma_sync_for_cpu(ctlr, xfer);
1653
+
spi_dma_sync_for_cpu(ctlr, msg, xfer);
1675
1654
} else {
1676
1655
if (xfer->len)
1677
1656
dev_err(&msg->spi->dev,