Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'phy-fixes-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy fixes from Vinod Koul:
- Qualcomm QMP driver fixes for null deref on suspend, bogus supplies
fix and reset entries fix
- BCM usb driver init array fix
- cadence array offset fix
- starfive link configuration fix
- config dependency fix for rockchip driver
- freescale reset signal fix before pll lock
- tegra driver fix for error pointer check
* tag 'phy-fixes-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
phy: tegra: xusb: Add error pointer check in xusb.c
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix X1E80100 resets entries
phy: freescale: imx8m-pcie: Do CMN_RST just before PHY PLL lock check
phy: phy-rockchip-samsung-hdptx: Depend on CONFIG_COMMON_CLK
phy: ti: phy-j721e-wiz: fix usxgmii configuration
phy: starfive: jh7110-usb: Fix link configuration to controller
phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies
phy: qcom: qmp-combo: move driver data initialisation earlier
phy: qcom: qmp-usbc: fix NULL-deref on runtime suspend
phy: qcom: qmp-usb-legacy: fix NULL-deref on runtime suspend
phy: qcom: qmp-usb: fix NULL-deref on runtime suspend
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: add missing x1e80100 pipediv2 clocks
phy: usb: disable COMMONONN for dual mode
phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register
phy: usb: Fix missing elements in BCM4908 USB init array
+59
-28
+3
-2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+3
-2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
···
154
154
- qcom,sm8550-qmp-gen4x2-pcie-phy
155
155
- qcom,sm8650-qmp-gen3x2-pcie-phy
156
156
- qcom,sm8650-qmp-gen4x2-pcie-phy
157
-
- qcom,x1e80100-qmp-gen3x2-pcie-phy
158
-
- qcom,x1e80100-qmp-gen4x2-pcie-phy
159
157
then:
160
158
properties:
161
159
clocks:
···
169
171
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
170
172
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
171
173
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
174
+
- qcom,x1e80100-qmp-gen3x2-pcie-phy
175
+
- qcom,x1e80100-qmp-gen4x2-pcie-phy
172
176
- qcom,x1e80100-qmp-gen4x4-pcie-phy
173
177
then:
174
178
properties:
···
201
201
- qcom,sm8550-qmp-gen4x2-pcie-phy
202
202
- qcom,sm8650-qmp-gen4x2-pcie-phy
203
203
- qcom,x1e80100-qmp-gen4x2-pcie-phy
204
+
- qcom,x1e80100-qmp-gen4x4-pcie-phy
204
205
then:
205
206
properties:
206
207
resets:
+9
-3
drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c
+9
-3
drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c
···
153
153
} else {
154
154
USB_CTRL_SET(ctrl, USB_PM, XHC_SOFT_RESETB);
155
155
/* Required for COMMONONN to be set */
156
-
USB_XHCI_GBL_UNSET(xhci_gbl, GUSB2PHYCFG, U2_FREECLK_EXISTS);
156
+
if (params->supported_port_modes != USB_CTLR_MODE_DRD)
157
+
USB_XHCI_GBL_UNSET(xhci_gbl, GUSB2PHYCFG,
158
+
U2_FREECLK_EXISTS);
157
159
}
158
160
}
159
161
···
330
328
/* 1 millisecond - for USB clocks to settle down */
331
329
usleep_range(1000, 2000);
332
330
333
-
/* Disable PHY when port is suspended */
334
-
USB_CTRL_SET(ctrl, P0_U2PHY_CFG1, COMMONONN);
331
+
/*
332
+
* Disable PHY when port is suspended
333
+
* Does not work in DRD mode
334
+
*/
335
+
if (params->supported_port_modes != USB_CTLR_MODE_DRD)
336
+
USB_CTRL_SET(ctrl, P0_U2PHY_CFG1, COMMONONN);
335
337
336
338
usb_wake_enable_7216(params, false);
337
339
usb_init_common(params);
+2
drivers/phy/broadcom/phy-brcm-usb-init.c
+2
drivers/phy/broadcom/phy-brcm-usb-init.c
···
220
220
0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
221
221
0, /* USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
222
222
0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
223
+
0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK */
224
+
0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK */
223
225
0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
224
226
0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
225
227
0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
+11
-10
drivers/phy/cadence/phy-cadence-sierra.c
+11
-10
drivers/phy/cadence/phy-cadence-sierra.c
···
174
174
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
175
175
#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
176
176
#define SIERRA_DEQ_TAU_CTRL3_PREG 0x152
177
-
#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158
177
+
#define SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG 0x158
178
178
#define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG 0x159
179
+
#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x15C
179
180
#define SIERRA_DEQ_PICTRL_PREG 0x161
180
181
#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170
181
182
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171
···
1734
1733
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1735
1734
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1736
1735
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1737
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1736
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
1738
1737
{0x002B, SIERRA_CPI_TRIM_PREG},
1739
1738
{0x0003, SIERRA_EPI_CTRL_PREG},
1740
1739
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
···
1798
1797
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1799
1798
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1800
1799
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1801
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1800
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
1802
1801
{0x002B, SIERRA_CPI_TRIM_PREG},
1803
1802
{0x0003, SIERRA_EPI_CTRL_PREG},
1804
1803
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
···
1875
1874
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1876
1875
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1877
1876
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1878
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1877
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
1879
1878
{0x002B, SIERRA_CPI_TRIM_PREG},
1880
1879
{0x0003, SIERRA_EPI_CTRL_PREG},
1881
1880
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
···
1942
1941
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1943
1942
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1944
1943
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1945
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1944
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
1946
1945
{0x002B, SIERRA_CPI_TRIM_PREG},
1947
1946
{0x0003, SIERRA_EPI_CTRL_PREG},
1948
1947
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
···
2013
2012
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2014
2013
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2015
2014
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2016
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2015
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2017
2016
{0x002B, SIERRA_CPI_TRIM_PREG},
2018
2017
{0x0003, SIERRA_EPI_CTRL_PREG},
2019
2018
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
···
2080
2079
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2081
2080
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2082
2081
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2083
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2082
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2084
2083
{0x002B, SIERRA_CPI_TRIM_PREG},
2085
2084
{0x0003, SIERRA_EPI_CTRL_PREG},
2086
2085
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
···
2141
2140
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2142
2141
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2143
2142
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2144
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2143
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2145
2144
{0x002B, SIERRA_CPI_TRIM_PREG},
2146
2145
{0x0003, SIERRA_EPI_CTRL_PREG},
2147
2146
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
···
2216
2215
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2217
2216
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2218
2217
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2219
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2218
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2220
2219
{0x002B, SIERRA_CPI_TRIM_PREG},
2221
2220
{0x0003, SIERRA_EPI_CTRL_PREG},
2222
2221
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
···
2285
2284
{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2286
2285
{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2287
2286
{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2288
-
{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2287
+
{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2289
2288
{0x002B, SIERRA_CPI_TRIM_PREG},
2290
2289
{0x0003, SIERRA_EPI_CTRL_PREG},
2291
2290
{0x803F, SIERRA_SDFILT_H2L_A_PREG},
+5
-5
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+5
-5
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
···
141
141
IMX8MM_GPR_PCIE_REF_CLK_PLL);
142
142
usleep_range(100, 200);
143
143
144
-
/* Do the PHY common block reset */
145
-
regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
146
-
IMX8MM_GPR_PCIE_CMN_RST,
147
-
IMX8MM_GPR_PCIE_CMN_RST);
148
-
149
144
switch (imx8_phy->drvdata->variant) {
150
145
case IMX8MP:
151
146
reset_control_deassert(imx8_phy->perst);
···
150
155
usleep_range(200, 500);
151
156
break;
152
157
}
158
+
159
+
/* Do the PHY common block reset */
160
+
regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
161
+
IMX8MM_GPR_PCIE_CMN_RST,
162
+
IMX8MM_GPR_PCIE_CMN_RST);
153
163
154
164
/* Polling to check the phy is ready or not. */
155
165
ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+1
-2
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+1
-2
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
···
3673
3673
return -ENOMEM;
3674
3674
3675
3675
qmp->dev = dev;
3676
+
dev_set_drvdata(dev, qmp);
3676
3677
3677
3678
qmp->orientation = TYPEC_ORIENTATION_NORMAL;
3678
3679
···
3749
3748
}
3750
3749
3751
3750
phy_set_drvdata(qmp->dp_phy, qmp);
3752
-
3753
-
dev_set_drvdata(dev, qmp);
3754
3751
3755
3752
if (usb_np == dev->of_node)
3756
3753
phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate);
+4
-4
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+4
-4
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
3661
3661
3662
3662
.reset_list = sdm845_pciephy_reset_l,
3663
3663
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3664
-
.vreg_list = sm8550_qmp_phy_vreg_l,
3665
-
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3664
+
.vreg_list = qmp_phy_vreg_l,
3665
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3666
3666
.regs = pciephy_v6_regs_layout,
3667
3667
3668
3668
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
···
3695
3695
3696
3696
.reset_list = sdm845_pciephy_reset_l,
3697
3697
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3698
-
.vreg_list = sm8550_qmp_phy_vreg_l,
3699
-
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3698
+
.vreg_list = qmp_phy_vreg_l,
3699
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3700
3700
.regs = pciephy_v6_regs_layout,
3701
3701
3702
3702
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+1
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
+1
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
+1
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+1
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+1
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+1
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+1
drivers/phy/rockchip/Kconfig
+1
drivers/phy/rockchip/Kconfig
+16
drivers/phy/starfive/phy-jh7110-usb.c
+16
drivers/phy/starfive/phy-jh7110-usb.c
···
10
10
#include <linux/clk.h>
11
11
#include <linux/err.h>
12
12
#include <linux/io.h>
13
+
#include <linux/mfd/syscon.h>
13
14
#include <linux/module.h>
14
15
#include <linux/phy/phy.h>
15
16
#include <linux/platform_device.h>
17
+
#include <linux/regmap.h>
16
18
#include <linux/usb/of.h>
17
19
18
20
#define USB_125M_CLK_RATE 125000000
19
21
#define USB_LS_KEEPALIVE_OFF 0x4
20
22
#define USB_LS_KEEPALIVE_ENABLE BIT(4)
21
23
24
+
#define USB_PDRSTN_SPLIT BIT(17)
25
+
#define SYSCON_USB_SPLIT_OFFSET 0x18
26
+
22
27
struct jh7110_usb2_phy {
23
28
struct phy *phy;
24
29
void __iomem *regs;
30
+
struct regmap *sys_syscon;
25
31
struct clk *usb_125m_clk;
26
32
struct clk *app_125m;
27
33
enum phy_mode mode;
···
66
60
phy->mode = mode;
67
61
usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE));
68
62
}
63
+
64
+
/* Connect usb 2.0 phy mode */
65
+
regmap_update_bits(phy->sys_syscon, SYSCON_USB_SPLIT_OFFSET,
66
+
USB_PDRSTN_SPLIT, USB_PDRSTN_SPLIT);
69
67
70
68
return 0;
71
69
}
···
138
128
139
129
phy_set_drvdata(phy->phy, phy);
140
130
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
131
+
132
+
phy->sys_syscon =
133
+
syscon_regmap_lookup_by_compatible("starfive,jh7110-sys-syscon");
134
+
if (IS_ERR(phy->sys_syscon))
135
+
return dev_err_probe(dev, PTR_ERR(phy->sys_syscon),
136
+
"Failed to get sys-syscon\n");
141
137
142
138
return PTR_ERR_OR_ZERO(phy_provider);
143
139
}
+2
drivers/phy/tegra/xusb.c
+2
drivers/phy/tegra/xusb.c
+2
-2
drivers/phy/ti/phy-j721e-wiz.c
+2
-2
drivers/phy/ti/phy-j721e-wiz.c
···
450
450
} else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
451
451
ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
452
452
ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
453
-
ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
454
-
mode = LANE_MODE_GEN1;
453
+
ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x2);
454
+
mode = LANE_MODE_GEN2;
455
455
} else {
456
456
continue;
457
457
}