tjh.dev / kernel
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Merge tag 'drm-fixes-2025-11-15' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Weekly fixes, amdgpu and vmwgfx making up the most of it, along with
panthor and i915/xe.

Seems about right for this time of development, nothing major
outstanding.

client:
- Fix description of module parameter

panthor:
- Flush writes before mapping buffers

vmwgfx:
- Improve command validation
- Improve ref counting
- Fix cursor-plane support

amdgpu:
- Disallow P2P DMA for GC 12 DCC surfaces
- ctx error handling fix
- UserQ fixes
- VRR fix
- ISP fix
- JPEG 5.0.1 fix

amdkfd:
- Save area check fix
- Fix GPU mappings for APU after prefetch

i915:
- Fix PSR's pipe to vblank conversion
- Disable Panel Replay on MST links

xe:
- New HW workarounds affecting PTL and WCL platforms

* tag 'drm-fixes-2025-11-15' of https://gitlab.freedesktop.org/drm/kernel:
drm/client: fix MODULE_PARM_DESC string for "active"
drm/i915/dp_mst: Disable Panel Replay
drm/amdkfd: Fix GPU mappings for APU after prefetch
drm/amdkfd: relax checks for over allocation of save area
drm/amdgpu/jpeg: Add parse_cs for JPEG5_0_1
drm/amd/amdgpu: Ensure isp_kernel_buffer_alloc() creates a new BO
drm/amd/display: Allow VRR params change if unsynced with the stream
drm/amdgpu: fix lock warning in amdgpu_userq_fence_driver_process
drm/amdgpu: jump to the correct label on failure
drm/amdgpu: disable peer-to-peer access for DCC-enabled GC12 VRAM surfaces
drm/xe/xe3lpg: Extend Wa_15016589081 for xe3lpg
drm/xe/xe3: Extend wa_14023061436
drm/xe/xe3: Add WA_14024681466 for Xe3_LPG
drm/i915/psr: fix pipe to vblank conversion
drm/panthor: Flush shmem writes before mapping buffers CPU-uncached
drm/vmwgfx: Restore Guest-Backed only cursor plane support
drm/vmwgfx: Use kref in vmw_bo_dirty
drm/vmwgfx: Validate command header size against SVGA_CMD_MAX_DATASIZE

Linus Torvalds d5c1b4b4 ccc00118

+102 -20
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
··· 236 236 r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, 237 237 &num_scheds, &scheds); 238 238 if (r) 239 - goto cleanup_entity; 239 + goto error_free_entity; 240 240 } 241 241 242 242 /* disable load balance if the hw engine retains context among dependent jobs */
+12
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
··· 82 82 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 83 83 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 84 84 85 + /* 86 + * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+. 87 + * Such buffers cannot be safely accessed over P2P due to device-local 88 + * compression metadata. Fallback to system-memory path instead. 89 + * Device supports GFX12 (GC 12.x or newer) 90 + * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag 91 + * 92 + */ 93 + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0) && 94 + bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) 95 + attach->peer2peer = false; 96 + 85 97 if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && 86 98 pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) 87 99 attach->peer2peer = false;
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
··· 280 280 if (ret) 281 281 return ret; 282 282 283 + /* Ensure *bo is NULL so a new BO will be created */ 284 + *bo = NULL; 283 285 ret = amdgpu_bo_create_kernel(adev, 284 286 size, 285 287 ISP_MC_ADDR_ALIGN,
+3 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
··· 151 151 { 152 152 struct amdgpu_userq_fence *userq_fence, *tmp; 153 153 struct dma_fence *fence; 154 + unsigned long flags; 154 155 u64 rptr; 155 156 int i; 156 157 157 158 if (!fence_drv) 158 159 return; 159 160 161 + spin_lock_irqsave(&fence_drv->fence_list_lock, flags); 160 162 rptr = amdgpu_userq_fence_read(fence_drv); 161 163 162 - spin_lock(&fence_drv->fence_list_lock); 163 164 list_for_each_entry_safe(userq_fence, tmp, &fence_drv->fences, link) { 164 165 fence = &userq_fence->base; 165 166 ··· 175 174 list_del(&userq_fence->link); 176 175 dma_fence_put(fence); 177 176 } 178 - spin_unlock(&fence_drv->fence_list_lock); 177 + spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); 179 178 } 180 179 181 180 void amdgpu_userq_fence_driver_destroy(struct kref *ref)
+1
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
··· 878 878 .get_rptr = jpeg_v5_0_1_dec_ring_get_rptr, 879 879 .get_wptr = jpeg_v5_0_1_dec_ring_get_wptr, 880 880 .set_wptr = jpeg_v5_0_1_dec_ring_set_wptr, 881 + .parse_cs = amdgpu_jpeg_dec_parse_cs, 881 882 .emit_frame_size = 882 883 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 883 884 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+6 -6
drivers/gpu/drm/amd/amdkfd/kfd_queue.c
··· 297 297 goto out_err_unreserve; 298 298 } 299 299 300 - if (properties->ctx_save_restore_area_size != topo_dev->node_props.cwsr_size) { 301 - pr_debug("queue cwsr size 0x%x not equal to node cwsr size 0x%x\n", 300 + if (properties->ctx_save_restore_area_size < topo_dev->node_props.cwsr_size) { 301 + pr_debug("queue cwsr size 0x%x not sufficient for node cwsr size 0x%x\n", 302 302 properties->ctx_save_restore_area_size, 303 303 topo_dev->node_props.cwsr_size); 304 304 err = -EINVAL; 305 305 goto out_err_unreserve; 306 306 } 307 307 308 - total_cwsr_size = (topo_dev->node_props.cwsr_size + topo_dev->node_props.debug_memory_size) 309 - * NUM_XCC(pdd->dev->xcc_mask); 308 + total_cwsr_size = (properties->ctx_save_restore_area_size + 309 + topo_dev->node_props.debug_memory_size) * NUM_XCC(pdd->dev->xcc_mask); 310 310 total_cwsr_size = ALIGN(total_cwsr_size, PAGE_SIZE); 311 311 312 312 err = kfd_queue_buffer_get(vm, (void *)properties->ctx_save_restore_area_address, ··· 352 352 topo_dev = kfd_topology_device_by_id(pdd->dev->id); 353 353 if (!topo_dev) 354 354 return -EINVAL; 355 - total_cwsr_size = (topo_dev->node_props.cwsr_size + topo_dev->node_props.debug_memory_size) 356 - * NUM_XCC(pdd->dev->xcc_mask); 355 + total_cwsr_size = (properties->ctx_save_restore_area_size + 356 + topo_dev->node_props.debug_memory_size) * NUM_XCC(pdd->dev->xcc_mask); 357 357 total_cwsr_size = ALIGN(total_cwsr_size, PAGE_SIZE); 358 358 359 359 kfd_queue_buffer_svm_put(pdd, properties->ctx_save_restore_area_address, total_cwsr_size);
+2
drivers/gpu/drm/amd/amdkfd/kfd_svm.c
··· 3687 3687 svm_range_apply_attrs(p, prange, nattr, attrs, &update_mapping); 3688 3688 /* TODO: unmap ranges from GPU that lost access */ 3689 3689 } 3690 + update_mapping |= !p->xnack_enabled && !list_empty(&remap_list); 3691 + 3690 3692 list_for_each_entry_safe(prange, next, &remove_list, update_list) { 3691 3693 pr_debug("unlink old 0x%p prange 0x%p [0x%lx 0x%lx]\n", 3692 3694 prange->svms, prange, prange->start,
+11
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
··· 1260 1260 update_v_total_for_static_ramp( 1261 1261 core_freesync, stream, in_out_vrr); 1262 1262 } 1263 + 1264 + /* 1265 + * If VRR is inactive, set vtotal min and max to nominal vtotal 1266 + */ 1267 + if (in_out_vrr->state == VRR_STATE_INACTIVE) { 1268 + in_out_vrr->adjust.v_total_min = 1269 + mod_freesync_calc_v_total_from_refresh(stream, 1270 + in_out_vrr->max_refresh_in_uhz); 1271 + in_out_vrr->adjust.v_total_max = in_out_vrr->adjust.v_total_min; 1272 + return; 1273 + } 1263 1274 } 1264 1275 1265 1276 unsigned long long mod_freesync_calc_nominal_field_rate(
+2 -2
drivers/gpu/drm/clients/drm_client_setup.c
··· 13 13 static char drm_client_default[16] = CONFIG_DRM_CLIENT_DEFAULT; 14 14 module_param_string(active, drm_client_default, sizeof(drm_client_default), 0444); 15 15 MODULE_PARM_DESC(active, 16 - "Choose which drm client to start, default is" 17 - CONFIG_DRM_CLIENT_DEFAULT "]"); 16 + "Choose which drm client to start, default is " 17 + CONFIG_DRM_CLIENT_DEFAULT); 18 18 19 19 /** 20 20 * drm_client_setup() - Setup in-kernel DRM clients
+6 -1
drivers/gpu/drm/i915/display/intel_psr.c
··· 585 585 struct intel_display *display = to_intel_display(intel_dp); 586 586 int ret; 587 587 588 + /* TODO: Enable Panel Replay on MST once it's properly implemented. */ 589 + if (intel_dp->mst_detect == DRM_DP_MST) 590 + return; 591 + 588 592 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 589 593 &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd)); 590 594 if (ret < 0) ··· 892 888 { 893 889 struct intel_display *display = to_intel_display(intel_dp); 894 890 u32 current_dc_state = intel_display_power_get_current_dc_state(display); 895 - struct drm_vblank_crtc *vblank = &display->drm->vblank[intel_dp->psr.pipe]; 891 + struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe); 892 + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 896 893 897 894 return (current_dc_state != DC_STATE_EN_UPTO_DC5 && 898 895 current_dc_state != DC_STATE_EN_UPTO_DC6) ||
+18
drivers/gpu/drm/panthor/panthor_gem.c
··· 288 288 289 289 panthor_gem_debugfs_set_usage_flags(bo, 0); 290 290 291 + /* If this is a write-combine mapping, we query the sgt to force a CPU 292 + * cache flush (dma_map_sgtable() is called when the sgt is created). 293 + * This ensures the zero-ing is visible to any uncached mapping created 294 + * by vmap/mmap. 295 + * FIXME: Ideally this should be done when pages are allocated, not at 296 + * BO creation time. 297 + */ 298 + if (shmem->map_wc) { 299 + struct sg_table *sgt; 300 + 301 + sgt = drm_gem_shmem_get_pages_sgt(shmem); 302 + if (IS_ERR(sgt)) { 303 + ret = PTR_ERR(sgt); 304 + goto out_put_gem; 305 + } 306 + } 307 + 291 308 /* 292 309 * Allocate an id of idr table where the obj is registered 293 310 * and handle has the id what user can see. ··· 313 296 if (!ret) 314 297 *size = bo->base.base.size; 315 298 299 + out_put_gem: 316 300 /* drop reference from allocate - handle holds it now. */ 317 301 drm_gem_object_put(&shmem->base); 318 302
+15 -1
drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c
··· 100 100 if (vmw->has_mob) { 101 101 if ((vmw->capabilities2 & SVGA_CAP2_CURSOR_MOB) != 0) 102 102 return VMW_CURSOR_UPDATE_MOB; 103 + else 104 + return VMW_CURSOR_UPDATE_GB_ONLY; 103 105 } 104 - 106 + drm_warn_once(&vmw->drm, "Unknown Cursor Type!\n"); 105 107 return VMW_CURSOR_UPDATE_NONE; 106 108 } 107 109 ··· 141 139 { 142 140 switch (update_type) { 143 141 case VMW_CURSOR_UPDATE_LEGACY: 142 + case VMW_CURSOR_UPDATE_GB_ONLY: 144 143 case VMW_CURSOR_UPDATE_NONE: 145 144 return 0; 146 145 case VMW_CURSOR_UPDATE_MOB: ··· 626 623 if (!surface || vps->cursor.legacy.id == surface->snooper.id) 627 624 vps->cursor.update_type = VMW_CURSOR_UPDATE_NONE; 628 625 break; 626 + case VMW_CURSOR_UPDATE_GB_ONLY: 629 627 case VMW_CURSOR_UPDATE_MOB: { 630 628 bo = vmw_user_object_buffer(&vps->uo); 631 629 if (bo) { ··· 741 737 vmw_cursor_plane_atomic_update(struct drm_plane *plane, 742 738 struct drm_atomic_state *state) 743 739 { 740 + struct vmw_bo *bo; 744 741 struct drm_plane_state *new_state = 745 742 drm_atomic_get_new_plane_state(state, plane); 746 743 struct drm_plane_state *old_state = ··· 766 761 break; 767 762 case VMW_CURSOR_UPDATE_MOB: 768 763 vmw_cursor_update_mob(dev_priv, vps); 764 + break; 765 + case VMW_CURSOR_UPDATE_GB_ONLY: 766 + bo = vmw_user_object_buffer(&vps->uo); 767 + if (bo) 768 + vmw_send_define_cursor_cmd(dev_priv, bo->map.virtual, 769 + vps->base.crtc_w, 770 + vps->base.crtc_h, 771 + vps->base.hotspot_x, 772 + vps->base.hotspot_y); 769 773 break; 770 774 case VMW_CURSOR_UPDATE_NONE: 771 775 /* do nothing */
+1
drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.h
··· 33 33 enum vmw_cursor_update_type { 34 34 VMW_CURSOR_UPDATE_NONE = 0, 35 35 VMW_CURSOR_UPDATE_LEGACY, 36 + VMW_CURSOR_UPDATE_GB_ONLY, 36 37 VMW_CURSOR_UPDATE_MOB, 37 38 }; 38 39
+5
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
··· 3668 3668 3669 3669 3670 3670 cmd_id = header->id; 3671 + if (header->size > SVGA_CMD_MAX_DATASIZE) { 3672 + VMW_DEBUG_USER("SVGA3D command: %d is too big.\n", 3673 + cmd_id + SVGA_3D_CMD_BASE); 3674 + return -E2BIG; 3675 + } 3671 3676 *size = header->size + sizeof(SVGA3dCmdHeader); 3672 3677 3673 3678 cmd_id -= SVGA_3D_CMD_BASE;
+5 -7
drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c
··· 32 32 33 33 /** 34 34 * struct vmw_bo_dirty - Dirty information for buffer objects 35 + * @ref_count: Reference count for this structure. Must be first member! 35 36 * @start: First currently dirty bit 36 37 * @end: Last currently dirty bit + 1 37 38 * @method: The currently used dirty method 38 39 * @change_count: Number of consecutive method change triggers 39 - * @ref_count: Reference count for this structure 40 40 * @bitmap_size: The size of the bitmap in bits. Typically equal to the 41 41 * nuber of pages in the bo. 42 42 * @bitmap: A bitmap where each bit represents a page. A set bit means a 43 43 * dirty page. 44 44 */ 45 45 struct vmw_bo_dirty { 46 + struct kref ref_count; 46 47 unsigned long start; 47 48 unsigned long end; 48 49 enum vmw_bo_dirty_method method; 49 50 unsigned int change_count; 50 - unsigned int ref_count; 51 51 unsigned long bitmap_size; 52 52 unsigned long bitmap[]; 53 53 }; ··· 221 221 int ret; 222 222 223 223 if (dirty) { 224 - dirty->ref_count++; 224 + kref_get(&dirty->ref_count); 225 225 return 0; 226 226 } 227 227 ··· 235 235 dirty->bitmap_size = num_pages; 236 236 dirty->start = dirty->bitmap_size; 237 237 dirty->end = 0; 238 - dirty->ref_count = 1; 238 + kref_init(&dirty->ref_count); 239 239 if (num_pages < PAGE_SIZE / sizeof(pte_t)) { 240 240 dirty->method = VMW_BO_DIRTY_PAGETABLE; 241 241 } else { ··· 274 274 { 275 275 struct vmw_bo_dirty *dirty = vbo->dirty; 276 276 277 - if (dirty && --dirty->ref_count == 0) { 278 - kvfree(dirty); 277 + if (dirty && kref_put(&dirty->ref_count, (void *)kvfree)) 279 278 vbo->dirty = NULL; 280 - } 281 279 } 282 280 283 281 /**
+1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
··· 168 168 169 169 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED) 170 170 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 171 + #define FAST_CLEAR_VALIGN_FIX REG_BIT(13) 171 172 172 173 #define XE2LPM_CCCHKNREG1 XE_REG(0x82a8) 173 174
+11
drivers/gpu/drm/xe/xe_wa.c
··· 679 679 }, 680 680 { XE_RTP_NAME("14023061436"), 681 681 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 682 + FUNC(xe_rtp_match_first_render_or_compute), OR, 683 + GRAPHICS_VERSION_RANGE(3003, 3005), 682 684 FUNC(xe_rtp_match_first_render_or_compute)), 683 685 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 684 686 }, ··· 917 915 { XE_RTP_NAME("22021007897"), 918 916 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3003), ENGINE_CLASS(RENDER)), 919 917 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 918 + }, 919 + { XE_RTP_NAME("14024681466"), 920 + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 921 + XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX)) 922 + }, 923 + { XE_RTP_NAME("15016589081"), 924 + XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 925 + ENGINE_CLASS(RENDER)), 926 + XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 920 927 }, 921 928 }; 922 929