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linux
dt-bindings: clock: add Intel Agilex5 clock manager
Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.
Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
authored by
Niravkumar L Rabara
and committed by
Dinh Nguyen
d5f0942b
2a29fe83
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Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
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Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel SoCFPGA Agilex5 clock manager
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maintainers:
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- Dinh Nguyen <dinguyen@kernel.org>
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description:
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The Intel Agilex5 Clock Manager is an integrated clock controller, which
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generates and supplies clock to all the modules.
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properties:
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compatible:
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const: intel,agilex5-clkmgr
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clkmgr: clock-controller@10d10000 {
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compatible = "intel,agilex5-clkmgr";
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reg = <0x10d10000 0x1000>;
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#clock-cells = <1>;
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};
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...
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include/dt-bindings/clock/intel,agilex5-clkmgr.h
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include/dt-bindings/clock/intel,agilex5-clkmgr.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (C) 2023, Intel Corporation
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*/
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#ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
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#define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
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/* fixed rate clocks */
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#define AGILEX5_OSC1 0
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#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1
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#define AGILEX5_CB_INTOSC_LS_CLK 2
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#define AGILEX5_F2S_FREE_CLK 3
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/* PLL clocks */
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#define AGILEX5_MAIN_PLL_CLK 4
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#define AGILEX5_MAIN_PLL_C0_CLK 5
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#define AGILEX5_MAIN_PLL_C1_CLK 6
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#define AGILEX5_MAIN_PLL_C2_CLK 7
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#define AGILEX5_MAIN_PLL_C3_CLK 8
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#define AGILEX5_PERIPH_PLL_CLK 9
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#define AGILEX5_PERIPH_PLL_C0_CLK 10
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#define AGILEX5_PERIPH_PLL_C1_CLK 11
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#define AGILEX5_PERIPH_PLL_C2_CLK 12
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#define AGILEX5_PERIPH_PLL_C3_CLK 13
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#define AGILEX5_CORE0_FREE_CLK 14
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#define AGILEX5_CORE1_FREE_CLK 15
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#define AGILEX5_CORE2_FREE_CLK 16
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#define AGILEX5_CORE3_FREE_CLK 17
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#define AGILEX5_DSU_FREE_CLK 18
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#define AGILEX5_BOOT_CLK 19
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/* fixed factor clocks */
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#define AGILEX5_L3_MAIN_FREE_CLK 20
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#define AGILEX5_NOC_FREE_CLK 21
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#define AGILEX5_S2F_USR0_CLK 22
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#define AGILEX5_NOC_CLK 23
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#define AGILEX5_EMAC_A_FREE_CLK 24
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#define AGILEX5_EMAC_B_FREE_CLK 25
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#define AGILEX5_EMAC_PTP_FREE_CLK 26
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#define AGILEX5_GPIO_DB_FREE_CLK 27
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#define AGILEX5_S2F_USER0_FREE_CLK 28
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#define AGILEX5_S2F_USER1_FREE_CLK 29
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#define AGILEX5_PSI_REF_FREE_CLK 30
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#define AGILEX5_USB31_FREE_CLK 31
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/* Gate clocks */
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#define AGILEX5_CORE0_CLK 32
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#define AGILEX5_CORE1_CLK 33
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#define AGILEX5_CORE2_CLK 34
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#define AGILEX5_CORE3_CLK 35
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#define AGILEX5_MPU_CLK 36
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#define AGILEX5_MPU_PERIPH_CLK 37
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#define AGILEX5_MPU_CCU_CLK 38
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#define AGILEX5_L4_MAIN_CLK 39
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#define AGILEX5_L4_MP_CLK 40
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#define AGILEX5_L4_SYS_FREE_CLK 41
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#define AGILEX5_L4_SP_CLK 42
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#define AGILEX5_CS_AT_CLK 43
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#define AGILEX5_CS_TRACE_CLK 44
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#define AGILEX5_CS_PDBG_CLK 45
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#define AGILEX5_EMAC1_CLK 47
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#define AGILEX5_EMAC2_CLK 48
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#define AGILEX5_EMAC_PTP_CLK 49
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#define AGILEX5_GPIO_DB_CLK 50
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#define AGILEX5_S2F_USER0_CLK 51
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#define AGILEX5_S2F_USER1_CLK 52
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#define AGILEX5_PSI_REF_CLK 53
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#define AGILEX5_USB31_SUSPEND_CLK 54
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#define AGILEX5_EMAC0_CLK 46
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#define AGILEX5_USB31_BUS_CLK_EARLY 55
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#define AGILEX5_USB2OTG_HCLK 56
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#define AGILEX5_SPIM_0_CLK 57
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#define AGILEX5_SPIM_1_CLK 58
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#define AGILEX5_SPIS_0_CLK 59
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#define AGILEX5_SPIS_1_CLK 60
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#define AGILEX5_DMA_CORE_CLK 61
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#define AGILEX5_DMA_HS_CLK 62
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#define AGILEX5_I3C_0_CORE_CLK 63
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#define AGILEX5_I3C_1_CORE_CLK 64
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#define AGILEX5_I2C_0_PCLK 65
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#define AGILEX5_I2C_1_PCLK 66
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#define AGILEX5_I2C_EMAC0_PCLK 67
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#define AGILEX5_I2C_EMAC1_PCLK 68
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#define AGILEX5_I2C_EMAC2_PCLK 69
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#define AGILEX5_UART_0_PCLK 70
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#define AGILEX5_UART_1_PCLK 71
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#define AGILEX5_SPTIMER_0_PCLK 72
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#define AGILEX5_SPTIMER_1_PCLK 73
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#define AGILEX5_DFI_CLK 74
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#define AGILEX5_NAND_NF_CLK 75
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#define AGILEX5_NAND_BCH_CLK 76
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#define AGILEX5_SDMMC_SDPHY_REG_CLK 77
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#define AGILEX5_SDMCLK 78
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#define AGILEX5_SOFTPHY_REG_PCLK 79
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#define AGILEX5_SOFTPHY_PHY_CLK 80
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#define AGILEX5_SOFTPHY_CTRL_CLK 81
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#define AGILEX5_NUM_CLKS 82
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#endif /* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */