Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: only init tap_delay ucode when it's included in ucode binary
Not all the gfx10 variants need to integrate
global tap_delay and per se tap_delay firmwares
Only init tap_delay ucode when it does include in
rlc ucode binary so driver doesn't send a null buffer
to psp for firmware loading
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Hawking Zhang
and committed by
Alex Deucher
d5f476ed
b3235e86
+35
-25
+35
-25
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+35
-25
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
4274
4274
4275
4275
}
4276
4276
4277
-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
4278
-
info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
4279
-
info->fw = adev->gfx.rlc_fw;
4280
-
adev->firmware.fw_size +=
4281
-
ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
4277
+
if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {
4278
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
4279
+
info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
4280
+
info->fw = adev->gfx.rlc_fw;
4281
+
adev->firmware.fw_size +=
4282
+
ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
4283
+
}
4282
4284
4283
-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
4284
-
info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
4285
-
info->fw = adev->gfx.rlc_fw;
4286
-
adev->firmware.fw_size +=
4287
-
ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
4285
+
if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {
4286
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
4287
+
info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
4288
+
info->fw = adev->gfx.rlc_fw;
4289
+
adev->firmware.fw_size +=
4290
+
ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
4291
+
}
4288
4292
4289
-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
4290
-
info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
4291
-
info->fw = adev->gfx.rlc_fw;
4292
-
adev->firmware.fw_size +=
4293
-
ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
4293
+
if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {
4294
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
4295
+
info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
4296
+
info->fw = adev->gfx.rlc_fw;
4297
+
adev->firmware.fw_size +=
4298
+
ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
4299
+
}
4294
4300
4295
-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
4296
-
info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
4297
-
info->fw = adev->gfx.rlc_fw;
4298
-
adev->firmware.fw_size +=
4299
-
ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
4301
+
if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {
4302
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
4303
+
info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
4304
+
info->fw = adev->gfx.rlc_fw;
4305
+
adev->firmware.fw_size +=
4306
+
ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
4307
+
}
4300
4308
4301
-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
4302
-
info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
4303
-
info->fw = adev->gfx.rlc_fw;
4304
-
adev->firmware.fw_size +=
4305
-
ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
4309
+
if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {
4310
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
4311
+
info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
4312
+
info->fw = adev->gfx.rlc_fw;
4313
+
adev->firmware.fw_size +=
4314
+
ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
4315
+
}
4306
4316
4307
4317
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4308
4318
info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;