+35 -1

Documentation/devicetree/bindings/gpio/gpio-mmio.yaml

reviewed

··· 22 22 - brcm,bcm6345-gpio 23 23 - ni,169445-nand-gpio 24 24 - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller 25 25 + - intel,ixp4xx-expansion-bus-mmio-gpio 25 26 26 27 big-endian: true 27 28 ··· 90 89 description: 91 90 If this property is present, the controller cannot drive the GPIO lines. 92 91 92 92 + if: 93 93 + properties: 94 94 + compatible: 95 95 + contains: 96 96 + const: intel,ixp4xx-expansion-bus-mmio-gpio 97 97 + then: 98 98 + $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml# 99 99 + 100 100 + patternProperties: 101 101 + "^.+-hog(-[0-9]+)?$": 102 102 + type: object 103 103 + required: 104 104 + - gpio-hog 105 105 + 93 106 required: 94 107 - compatible 95 108 - reg ··· 111 96 - '#gpio-cells' 112 97 - gpio-controller 113 98 114 114 - additionalProperties: false 99 99 + unevaluatedProperties: false 115 100 116 101 examples: 117 102 - | ··· 140 125 native-endian; 141 126 gpio-controller; 142 127 #gpio-cells = <2>; 128 128 + }; 129 129 + 130 130 + bus@c4000000 { 131 131 + compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; 132 132 + reg = <0xc4000000 0x30>; 133 133 + native-endian; 134 134 + #address-cells = <2>; 135 135 + #size-cells = <1>; 136 136 + ranges = <0 0x0 0x50000000 0x01000000>; 137 137 + dma-ranges = <0 0x0 0x50000000 0x01000000>; 138 138 + gpio@1,0 { 139 139 + compatible = "intel,ixp4xx-expansion-bus-mmio-gpio"; 140 140 + gpio-controller; 141 141 + #gpio-cells = <2>; 142 142 + big-endian; 143 143 + reg = <1 0x00000000 0x2>; 144 144 + reg-names = "dat"; 145 145 + intel,ixp4xx-eb-write-enable = <1>; 146 146 + }; 143 147 };

+75 -5

Documentation/devicetree/bindings/gpio/gpio-mxs.yaml

reviewed

··· 18 18 19 19 properties: 20 20 compatible: 21 21 - enum: 22 22 - - fsl,imx23-pinctrl 23 23 - - fsl,imx28-pinctrl 21 21 + items: 22 22 + - enum: 23 23 + - fsl,imx23-pinctrl 24 24 + - fsl,imx28-pinctrl 25 25 + # Over 10 years old devices, driver use simple-bus to probe child gpio 26 26 + # Devices. Keep it as it to be compatible existed dts files. 27 27 + - const: simple-bus 24 28 25 29 '#address-cells': 26 30 const: 1 ··· 35 31 maxItems: 1 36 32 37 33 patternProperties: 38 38 - "gpio@[0-9]+$": 34 34 + "^(?!gpio@)[^@]+@[0-9]+$": 35 35 + type: object 36 36 + properties: 37 37 + fsl,pinmux-ids: 38 38 + $ref: /schemas/types.yaml#/definitions/uint32-array 39 39 + description: | 40 40 + An integer array. Each integer in the array specify a pin 41 41 + with given mux function, with bank, pin and mux packed as below. 42 42 + 43 43 + [15..12] : bank number 44 44 + [11..4] : pin number 45 45 + [3..0] : mux selection 46 46 + 47 47 + This integer with mux selection packed is used as an entity by both group 48 48 + and config nodes to identify a pin. The mux selection in the integer takes 49 49 + effects only on group node, and will get ignored by driver with config node, 50 50 + since config node is only meant to set up pin configurations. 51 51 + 52 52 + Valid values for these integers are listed below. 53 53 + 54 54 + reg: 55 55 + items: 56 56 + - description: | 57 57 + pin group index. NOTE: it is supposed wrong use reg property 58 58 + here. But it is over 10 years devices. Just keep it as it. 59 59 + 60 60 + fsl,drive-strength: 61 61 + $ref: /schemas/types.yaml#/definitions/uint32 62 62 + enum: [0, 1, 2, 3] 63 63 + description: | 64 64 + 0: MXS_DRIVE_4mA 65 65 + 1: MXS_DRIVE_8mA 66 66 + 2: MXS_DRIVE_12mA 67 67 + 3: MXS_DRIVE_16mA 68 68 + 69 69 + fsl,voltage: 70 70 + $ref: /schemas/types.yaml#/definitions/uint32 71 71 + enum: [0, 1] 72 72 + description: | 73 73 + 0: MXS_VOLTAGE_LOW - 1.8 V 74 74 + 1: MXS_VOLTAGE_HIGH - 3.3 V 75 75 + 76 76 + fsl,pull-up: 77 77 + $ref: /schemas/types.yaml#/definitions/uint32 78 78 + enum: [0, 1] 79 79 + description: | 80 80 + 0: MXS_PULL_DISABLE - Disable the internal pull-up 81 81 + 1: MXS_PULL_ENABLE - Enable the internal pull-up 82 82 + 83 83 + Note that when enabling the pull-up, the internal pad keeper gets disabled. 84 84 + Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up 85 85 + will only disable the internal pad keeper. 86 86 + 87 87 + required: 88 88 + - fsl,pinmux-ids 89 89 + 90 90 + additionalProperties: false 91 91 + 92 92 + "^gpio@[0-9]+$": 39 93 type: object 40 94 properties: 41 95 compatible: ··· 142 80 pinctrl@80018000 { 143 81 #address-cells = <1>; 144 82 #size-cells = <0>; 145 145 - compatible = "fsl,imx28-pinctrl"; 83 83 + compatible = "fsl,imx28-pinctrl", "simple-bus"; 146 84 reg = <0x80018000 0x2000>; 147 85 148 86 gpio@0 { ··· 193 131 #gpio-cells = <2>; 194 132 interrupt-controller; 195 133 #interrupt-cells = <2>; 134 134 + }; 135 135 + 136 136 + lcdif-apx4@5 { 137 137 + reg = <5>; 138 138 + fsl,pinmux-ids = <0x1181 0x1191>; 139 139 + fsl,drive-strength = <0>; 140 140 + fsl,voltage = <0>; 141 141 + fsl,pull-up = <0>; 196 142 }; 197 143 };

+27 -1

Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml

reviewed

··· 14 14 oneOf: 15 15 - enum: 16 16 - loongson,ls2k-gpio 17 17 + - loongson,ls2k0300-gpio 17 18 - loongson,ls2k0500-gpio0 18 19 - loongson,ls2k0500-gpio1 19 20 - loongson,ls2k2000-gpio0 ··· 37 36 38 37 ngpios: 39 38 minimum: 1 40 40 - maximum: 64 39 39 + maximum: 128 41 40 42 41 "#gpio-cells": 43 42 const: 2 ··· 50 49 minItems: 1 51 50 maxItems: 64 52 51 52 52 + "#interrupt-cells": 53 53 + const: 2 54 54 + 55 55 + interrupt-controller: true 56 56 + 57 57 + resets: 58 58 + maxItems: 1 59 59 + 53 60 required: 54 61 - compatible 55 62 - reg ··· 66 57 - gpio-controller 67 58 - gpio-ranges 68 59 - interrupts 60 60 + 61 61 + allOf: 62 62 + - if: 63 63 + properties: 64 64 + compatible: 65 65 + contains: 66 66 + const: loongson,ls2k0300-gpio 67 67 + then: 68 68 + required: 69 69 + - "#interrupt-cells" 70 70 + - interrupt-controller 71 71 + - resets 72 72 + else: 73 73 + properties: 74 74 + "#interrupts-cells": false 75 75 + interrupt-controller: false 76 76 + resets: false 69 77 70 78 additionalProperties: false 71 79

+3 -3

Documentation/devicetree/bindings/gpio/maxim,max31910.yaml

reviewed

··· 95 95 #gpio-cells = <2>; 96 96 97 97 maxim,modesel-gpios = <&gpio2 23>; 98 98 - maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; 99 99 - maxim,db0-gpios = <&gpio2 25>; 100 100 - maxim,db1-gpios = <&gpio2 26>; 98 98 + maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; 99 99 + maxim,db0-gpios = <&gpio2 25>; 100 100 + maxim,db1-gpios = <&gpio2 26>; 101 101 102 102 spi-max-frequency = <25000000>; 103 103 };

+83

Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/gpio/maxim,max7360-gpio.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Maxim MAX7360 GPIO controller 8 8 + 9 9 + maintainers: 10 10 + - Kamel Bouhara <kamel.bouhara@bootlin.com> 11 11 + - Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 12 12 + 13 13 + description: | 14 14 + Maxim MAX7360 GPIO controller, in MAX7360 chipset 15 15 + https://www.analog.com/en/products/max7360.html 16 16 + 17 17 + The device provides two series of GPIOs, referred here as GPIOs and GPOs. 18 18 + 19 19 + PORT0 to PORT7 pins can be used as GPIOs, with support for interrupts and 20 20 + constant-current mode. These pins will also be used by the rotary encoder and 21 21 + PWM functionalities. 22 22 + 23 23 + COL2 to COL7 pins can be used as GPOs, there is no input capability. COL pins 24 24 + will be partitioned, with the first pins being affected to the keypad 25 25 + functionality and the last ones as GPOs. 26 26 + 27 27 + properties: 28 28 + compatible: 29 29 + enum: 30 30 + - maxim,max7360-gpio 31 31 + - maxim,max7360-gpo 32 32 + 33 33 + gpio-controller: true 34 34 + 35 35 + "#gpio-cells": 36 36 + const: 2 37 37 + 38 38 + interrupt-controller: true 39 39 + 40 40 + "#interrupt-cells": 41 41 + const: 2 42 42 + 43 43 + maxim,constant-current-disable: 44 44 + $ref: /schemas/types.yaml#/definitions/uint32 45 45 + description: 46 46 + Bit field, each bit disables constant-current output of the associated 47 47 + GPIO, starting from the least significant bit for the first GPIO. 48 48 + maximum: 0xff 49 49 + 50 50 + required: 51 51 + - compatible 52 52 + - gpio-controller 53 53 + 54 54 + allOf: 55 55 + - if: 56 56 + properties: 57 57 + compatible: 58 58 + contains: 59 59 + enum: 60 60 + - maxim,max7360-gpio 61 61 + ngpios: false 62 62 + then: 63 63 + required: 64 64 + - interrupt-controller 65 65 + else: 66 66 + properties: 67 67 + interrupt-controller: false 68 68 + maxim,constant-current-disable: false 69 69 + 70 70 + additionalProperties: false 71 71 + 72 72 + examples: 73 73 + - | 74 74 + gpio { 75 75 + compatible = "maxim,max7360-gpio"; 76 76 + 77 77 + gpio-controller; 78 78 + #gpio-cells = <2>; 79 79 + maxim,constant-current-disable = <0x06>; 80 80 + 81 81 + interrupt-controller; 82 82 + #interrupt-cells = <2>; 83 83 + };

+2

Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml

reviewed

··· 85 85 - nvidia,tegra194-gpio-aon 86 86 - nvidia,tegra234-gpio 87 87 - nvidia,tegra234-gpio-aon 88 88 + - nvidia,tegra256-gpio 88 89 89 90 reg-names: 90 91 items: ··· 156 155 - nvidia,tegra186-gpio 157 156 - nvidia,tegra194-gpio 158 157 - nvidia,tegra234-gpio 158 158 + - nvidia,tegra256-gpio 159 159 then: 160 160 properties: 161 161 interrupts:

+1 -1

Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml

reviewed

··· 80 80 gpio@d4019000 { 81 81 compatible = "spacemit,k1-gpio"; 82 82 reg = <0xd4019000 0x800>; 83 83 - clocks =<&ccu 9>, <&ccu 61>; 83 83 + clocks = <&ccu 9>, <&ccu 61>; 84 84 clock-names = "core", "bus"; 85 85 gpio-controller; 86 86 #gpio-cells = <3>;

+1 -1

Documentation/devicetree/bindings/gpio/trivial-gpio.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: http://devicetree.org/schemas/trivial-gpio.yaml# 4 4 + $id: http://devicetree.org/schemas/gpio/trivial-gpio.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: Trivial 2-cell GPIO controllers

+191

Documentation/devicetree/bindings/mfd/maxim,max7360.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/mfd/maxim,max7360.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Maxim MAX7360 Keypad, Rotary encoder, PWM and GPIO controller 8 8 + 9 9 + maintainers: 10 10 + - Kamel Bouhara <kamel.bouhara@bootlin.com> 11 11 + - Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 12 12 + 13 13 + description: | 14 14 + Maxim MAX7360 device, with following functions: 15 15 + - keypad controller 16 16 + - rotary controller 17 17 + - GPIO and GPO controller 18 18 + - PWM controller 19 19 + 20 20 + https://www.analog.com/en/products/max7360.html 21 21 + 22 22 + allOf: 23 23 + - $ref: /schemas/input/matrix-keymap.yaml# 24 24 + - $ref: /schemas/input/input.yaml# 25 25 + 26 26 + properties: 27 27 + compatible: 28 28 + enum: 29 29 + - maxim,max7360 30 30 + 31 31 + reg: 32 32 + maxItems: 1 33 33 + 34 34 + interrupts: 35 35 + maxItems: 2 36 36 + 37 37 + interrupt-names: 38 38 + items: 39 39 + - const: inti 40 40 + - const: intk 41 41 + 42 42 + keypad-debounce-delay-ms: 43 43 + description: Keypad debounce delay in ms 44 44 + minimum: 9 45 45 + maximum: 40 46 46 + default: 9 47 47 + 48 48 + rotary-debounce-delay-ms: 49 49 + description: Rotary encoder debounce delay in ms 50 50 + minimum: 0 51 51 + maximum: 15 52 52 + default: 0 53 53 + 54 54 + linux,axis: 55 55 + $ref: /schemas/input/rotary-encoder.yaml#/properties/linux,axis 56 56 + 57 57 + rotary-encoder,relative-axis: 58 58 + $ref: /schemas/types.yaml#/definitions/flag 59 59 + description: 60 60 + Register a relative axis rather than an absolute one. 61 61 + 62 62 + rotary-encoder,steps: 63 63 + $ref: /schemas/types.yaml#/definitions/uint32 64 64 + default: 24 65 65 + description: 66 66 + Number of steps in a full turnaround of the 67 67 + encoder. Only relevant for absolute axis. Defaults to 24 which is a 68 68 + typical value for such devices. 69 69 + 70 70 + rotary-encoder,rollover: 71 71 + $ref: /schemas/types.yaml#/definitions/flag 72 72 + description: 73 73 + Automatic rollover when the rotary value becomes 74 74 + greater than the specified steps or smaller than 0. For absolute axis only. 75 75 + 76 76 + "#pwm-cells": 77 77 + const: 3 78 78 + 79 79 + gpio: 80 80 + $ref: /schemas/gpio/maxim,max7360-gpio.yaml# 81 81 + description: 82 82 + PORT0 to PORT7 general purpose input/output pins configuration. 83 83 + 84 84 + gpo: 85 85 + $ref: /schemas/gpio/maxim,max7360-gpio.yaml# 86 86 + description: > 87 87 + COL2 to COL7 general purpose output pins configuration. Allows to use 88 88 + unused keypad columns as outputs. 89 89 + 90 90 + The MAX7360 has 8 column lines and 6 of them can be used as GPOs. GPIOs 91 91 + numbers used for this gpio-controller node do correspond to the column 92 92 + numbers: values 0 and 1 are never valid, values from 2 to 7 might be valid 93 93 + depending on the value of the keypad,num-column property. 94 94 + 95 95 + patternProperties: 96 96 + '-pins$': 97 97 + type: object 98 98 + description: 99 99 + Pinctrl node's client devices use subnodes for desired pin configuration. 100 100 + Client device subnodes use below standard properties. 101 101 + $ref: /schemas/pinctrl/pincfg-node.yaml 102 102 + 103 103 + properties: 104 104 + pins: 105 105 + description: 106 106 + List of gpio pins affected by the properties specified in this 107 107 + subnode. 108 108 + items: 109 109 + pattern: '^(PORT[0-7]|ROTARY)$' 110 110 + minItems: 1 111 111 + maxItems: 8 112 112 + 113 113 + function: 114 114 + description: 115 115 + Specify the alternative function to be configured for the specified 116 116 + pins. 117 117 + enum: [gpio, pwm, rotary] 118 118 + 119 119 + additionalProperties: false 120 120 + 121 121 + required: 122 122 + - compatible 123 123 + - reg 124 124 + - interrupts 125 125 + - interrupt-names 126 126 + - linux,keymap 127 127 + - linux,axis 128 128 + - "#pwm-cells" 129 129 + - gpio 130 130 + - gpo 131 131 + 132 132 + unevaluatedProperties: false 133 133 + 134 134 + examples: 135 135 + - | 136 136 + #include <dt-bindings/input/input.h> 137 137 + #include <dt-bindings/interrupt-controller/arm-gic.h> 138 138 + 139 139 + i2c { 140 140 + #address-cells = <1>; 141 141 + #size-cells = <0>; 142 142 + 143 143 + io-expander@38 { 144 144 + compatible = "maxim,max7360"; 145 145 + reg = <0x38>; 146 146 + 147 147 + interrupt-parent = <&gpio1>; 148 148 + interrupts = <23 IRQ_TYPE_LEVEL_LOW>, 149 149 + <24 IRQ_TYPE_LEVEL_LOW>; 150 150 + interrupt-names = "inti", "intk"; 151 151 + 152 152 + keypad,num-rows = <8>; 153 153 + keypad,num-columns = <4>; 154 154 + linux,keymap = < 155 155 + MATRIX_KEY(0x00, 0x00, KEY_F5) 156 156 + MATRIX_KEY(0x01, 0x00, KEY_F4) 157 157 + MATRIX_KEY(0x02, 0x01, KEY_F6) 158 158 + >; 159 159 + keypad-debounce-delay-ms = <10>; 160 160 + autorepeat; 161 161 + 162 162 + rotary-debounce-delay-ms = <2>; 163 163 + linux,axis = <0>; /* REL_X */ 164 164 + rotary-encoder,relative-axis; 165 165 + 166 166 + #pwm-cells = <3>; 167 167 + 168 168 + max7360_gpio: gpio { 169 169 + compatible = "maxim,max7360-gpio"; 170 170 + 171 171 + gpio-controller; 172 172 + #gpio-cells = <2>; 173 173 + maxim,constant-current-disable = <0x06>; 174 174 + 175 175 + interrupt-controller; 176 176 + #interrupt-cells = <0x2>; 177 177 + }; 178 178 + 179 179 + max7360_gpo: gpo { 180 180 + compatible = "maxim,max7360-gpo"; 181 181 + 182 182 + gpio-controller; 183 183 + #gpio-cells = <2>; 184 184 + }; 185 185 + 186 186 + backlight_pins: backlight-pins { 187 187 + pins = "PORT2"; 188 188 + function = "pwm"; 189 189 + }; 190 190 + }; 191 191 + };

-127

Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt

reviewed

··· 1 1 - * Freescale MXS Pin Controller 2 2 - 3 3 - The pins controlled by mxs pin controller are organized in banks, each bank 4 4 - has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th 5 5 - function is GPIO. The configuration on the pins includes drive strength, 6 6 - voltage and pull-up. 7 7 - 8 8 - Required properties: 9 9 - - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" 10 10 - - reg: Should contain the register physical address and length for the 11 11 - pin controller. 12 12 - 13 13 - Please refer to pinctrl-bindings.txt in this directory for details of the 14 14 - common pinctrl bindings used by client devices. 15 15 - 16 16 - The node of mxs pin controller acts as a container for an arbitrary number of 17 17 - subnodes. Each of these subnodes represents some desired configuration for 18 18 - a group of pins, and only affects those parameters that are explicitly listed. 19 19 - In other words, a subnode that describes a drive strength parameter implies no 20 20 - information about pull-up. For this reason, even seemingly boolean values are 21 21 - actually tristates in this binding: unspecified, off, or on. Unspecified is 22 22 - represented as an absent property, and off/on are represented as integer 23 23 - values 0 and 1. 24 24 - 25 25 - Those subnodes under mxs pin controller node will fall into two categories. 26 26 - One is to set up a group of pins for a function, both mux selection and pin 27 27 - configurations, and it's called group node in the binding document. The other 28 28 - one is to adjust the pin configuration for some particular pins that need a 29 29 - different configuration than what is defined in group node. The binding 30 30 - document calls this type of node config node. 31 31 - 32 32 - On mxs, there is no hardware pin group. The pin group in this binding only 33 33 - means a group of pins put together for particular peripheral to work in 34 34 - particular function, like SSP0 functioning as mmc0-8bit. That said, the 35 35 - group node should include all the pins needed for one function rather than 36 36 - having these pins defined in several group nodes. It also means each of 37 37 - "pinctrl-*" phandle in client device node should only have one group node 38 38 - pointed in there, while the phandle can have multiple config node referenced 39 39 - there to adjust configurations for some pins in the group. 40 40 - 41 41 - Required subnode-properties: 42 42 - - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin 43 43 - with given mux function, with bank, pin and mux packed as below. 44 44 - 45 45 - [15..12] : bank number 46 46 - [11..4] : pin number 47 47 - [3..0] : mux selection 48 48 - 49 49 - This integer with mux selection packed is used as an entity by both group 50 50 - and config nodes to identify a pin. The mux selection in the integer takes 51 51 - effects only on group node, and will get ignored by driver with config node, 52 52 - since config node is only meant to set up pin configurations. 53 53 - 54 54 - Valid values for these integers are listed below. 55 55 - 56 56 - - reg: Should be the index of the group nodes for same function. This property 57 57 - is required only for group nodes, and should not be present in any config 58 58 - nodes. 59 59 - 60 60 - Optional subnode-properties: 61 61 - - fsl,drive-strength: Integer. 62 62 - 0: MXS_DRIVE_4mA 63 63 - 1: MXS_DRIVE_8mA 64 64 - 2: MXS_DRIVE_12mA 65 65 - 3: MXS_DRIVE_16mA 66 66 - - fsl,voltage: Integer. 67 67 - 0: MXS_VOLTAGE_LOW - 1.8 V 68 68 - 1: MXS_VOLTAGE_HIGH - 3.3 V 69 69 - - fsl,pull-up: Integer. 70 70 - 0: MXS_PULL_DISABLE - Disable the internal pull-up 71 71 - 1: MXS_PULL_ENABLE - Enable the internal pull-up 72 72 - 73 73 - Note that when enabling the pull-up, the internal pad keeper gets disabled. 74 74 - Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up 75 75 - will only disable the internal pad keeper. 76 76 - 77 77 - Examples: 78 78 - 79 79 - pinctrl@80018000 { 80 80 - #address-cells = <1>; 81 81 - #size-cells = <0>; 82 82 - compatible = "fsl,imx28-pinctrl"; 83 83 - reg = <0x80018000 2000>; 84 84 - 85 85 - mmc0_8bit_pins_a: mmc0-8bit@0 { 86 86 - reg = <0>; 87 87 - fsl,pinmux-ids = < 88 88 - MX28_PAD_SSP0_DATA0__SSP0_D0 89 89 - MX28_PAD_SSP0_DATA1__SSP0_D1 90 90 - MX28_PAD_SSP0_DATA2__SSP0_D2 91 91 - MX28_PAD_SSP0_DATA3__SSP0_D3 92 92 - MX28_PAD_SSP0_DATA4__SSP0_D4 93 93 - MX28_PAD_SSP0_DATA5__SSP0_D5 94 94 - MX28_PAD_SSP0_DATA6__SSP0_D6 95 95 - MX28_PAD_SSP0_DATA7__SSP0_D7 96 96 - MX28_PAD_SSP0_CMD__SSP0_CMD 97 97 - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 98 98 - MX28_PAD_SSP0_SCK__SSP0_SCK 99 99 - >; 100 100 - fsl,drive-strength = <MXS_DRIVE_4mA>; 101 101 - fsl,voltage = <MXS_VOLTAGE_HIGH>; 102 102 - fsl,pull-up = <MXS_PULL_ENABLE>; 103 103 - }; 104 104 - 105 105 - mmc_cd_cfg: mmc-cd-cfg { 106 106 - fsl,pinmux-ids = <MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT>; 107 107 - fsl,pull-up = <MXS_PULL_DISABLE>; 108 108 - }; 109 109 - 110 110 - mmc_sck_cfg: mmc-sck-cfg { 111 111 - fsl,pinmux-ids = <MX28_PAD_SSP0_SCK__SSP0_SCK>; 112 112 - fsl,drive-strength = <MXS_DRIVE_12mA>; 113 113 - fsl,pull-up = <MXS_PULL_DISABLE>; 114 114 - }; 115 115 - }; 116 116 - 117 117 - In this example, group node mmc0-8bit defines a group of pins for mxs SSP0 118 118 - to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations 119 119 - applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are 120 120 - adjusting the configuration for pins card-detection and clock from what group 121 121 - node mmc0-8bit defines. Only the configuration properties to be adjusted need 122 122 - to be listed in the config nodes. 123 123 - 124 124 - Valid values for i.MX28/i.MX23 pinmux-id are defined in 125 125 - arch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h. 126 126 - The definitions for the padconfig properties can be found in 127 127 - arch/arm/boot/dts/mxs-pinfunc.h.

+65

Documentation/driver-api/gpio/board.rst

reviewed

··· 94 94 For more information about the ACPI GPIO bindings see 95 95 Documentation/firmware-guide/acpi/gpio-properties.rst. 96 96 97 97 + Software Nodes 98 98 + -------------- 99 99 + 100 100 + Software nodes allow board-specific code to construct an in-memory, 101 101 + device-tree-like structure using struct software_node and struct 102 102 + property_entry. This structure can then be associated with a platform device, 103 103 + allowing drivers to use the standard device properties API to query 104 104 + configuration, just as they would on an ACPI or device tree system. 105 105 + 106 106 + Software-node-backed GPIOs are described using the ``PROPERTY_ENTRY_GPIO()`` 107 107 + macro, which ties a software node representing the GPIO controller with 108 108 + consumer device. It allows consumers to use regular gpiolib APIs, such as 109 109 + gpiod_get(), gpiod_get_optional(). 110 110 + 111 111 + The software node representing a GPIO controller need not be attached to the 112 112 + GPIO controller device. The only requirement is that the node must be 113 113 + registered and its name must match the GPIO controller's label. 114 114 + 115 115 + For example, here is how to describe a single GPIO-connected LED. This is an 116 116 + alternative to using platform_data on legacy systems. 117 117 + 118 118 + .. code-block:: c 119 119 + 120 120 + #include <linux/property.h> 121 121 + #include <linux/gpio/machine.h> 122 122 + #include <linux/gpio/property.h> 123 123 + 124 124 + /* 125 125 + * 1. Define a node for the GPIO controller. Its .name must match the 126 126 + * controller's label. 127 127 + */ 128 128 + static const struct software_node gpio_controller_node = { 129 129 + .name = "gpio-foo", 130 130 + }; 131 131 + 132 132 + /* 2. Define the properties for the LED device. */ 133 133 + static const struct property_entry led_device_props[] = { 134 134 + PROPERTY_ENTRY_STRING("label", "myboard:green:status"), 135 135 + PROPERTY_ENTRY_STRING("linux,default-trigger", "heartbeat"), 136 136 + PROPERTY_ENTRY_GPIO("gpios", &gpio_controller_node, 42, GPIO_ACTIVE_HIGH), 137 137 + { } 138 138 + }; 139 139 + 140 140 + /* 3. Define the software node for the LED device. */ 141 141 + static const struct software_node led_device_swnode = { 142 142 + .name = "status-led", 143 143 + .properties = led_device_props, 144 144 + }; 145 145 + 146 146 + /* 147 147 + * 4. Register the software nodes and the platform device. 148 148 + */ 149 149 + const struct software_node *swnodes[] = { 150 150 + &gpio_controller_node, 151 151 + &led_device_swnode, 152 152 + NULL 153 153 + }; 154 154 + software_node_register_node_group(swnodes); 155 155 + 156 156 + // Then register a platform_device for "leds-gpio" and associate 157 157 + // it with &led_device_swnode via .fwnode. 158 158 + 159 159 + For a complete guide on converting board files to use software nodes, see 160 160 + Documentation/driver-api/gpio/legacy-boards.rst. 161 161 + 97 162 Platform Data 98 163 ------------- 99 164 Finally, GPIOs can be bound to devices and functions using platform data. Board

+1

Documentation/driver-api/gpio/index.rst

reviewed

··· 12 12 driver 13 13 consumer 14 14 board 15 15 + legacy-boards 15 16 drivers-on-gpio 16 17 bt8xxgpio 17 18

+298

Documentation/driver-api/gpio/legacy-boards.rst

reviewed

··· 1 1 + Supporting Legacy Boards 2 2 + ======================== 3 3 + 4 4 + Many drivers in the kernel, such as ``leds-gpio`` and ``gpio-keys``, are 5 5 + migrating away from using board-specific ``platform_data`` to a unified device 6 6 + properties interface. This interface allows drivers to be simpler and more 7 7 + generic, as they can query properties in a standardized way. 8 8 + 9 9 + On modern systems, these properties are provided via device tree. However, some 10 10 + older platforms have not been converted to device tree and instead rely on 11 11 + board files to describe their hardware configuration. To bridge this gap and 12 12 + allow these legacy boards to work with modern, generic drivers, the kernel 13 13 + provides a mechanism called **software nodes**. 14 14 + 15 15 + This document provides a guide on how to convert a legacy board file from using 16 16 + ``platform_data`` and ``gpiod_lookup_table`` to the modern software node 17 17 + approach for describing GPIO-connected devices. 18 18 + 19 19 + The Core Idea: Software Nodes 20 20 + ----------------------------- 21 21 + 22 22 + Software nodes allow board-specific code to construct an in-memory, 23 23 + device-tree-like structure using struct software_node and struct 24 24 + property_entry. This structure can then be associated with a platform device, 25 25 + allowing drivers to use the standard device properties API (e.g., 26 26 + device_property_read_u32(), device_property_read_string()) to query 27 27 + configuration, just as they would on an ACPI or device tree system. 28 28 + 29 29 + The gpiolib code has support for handling software nodes, so that if GPIO is 30 30 + described properly, as detailed in the section below, then regular gpiolib APIs, 31 31 + such as gpiod_get(), gpiod_get_optional(), and others will work. 32 32 + 33 33 + Requirements for GPIO Properties 34 34 + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 35 35 + 36 36 + When using software nodes to describe GPIO connections, the following 37 37 + requirements must be met for the GPIO core to correctly resolve the reference: 38 38 + 39 39 + 1. **The GPIO controller's software node "name" must match the controller's 40 40 + "label".** The gpiolib core uses this name to find the corresponding 41 41 + struct gpio_chip at runtime. 42 42 + This software node has to be registered, but need not be attached to the 43 43 + device representing the GPIO controller that is providing the GPIO in 44 44 + question. It may be left as a "free floating" node. 45 45 + 46 46 + 2. **The GPIO property must be a reference.** The ``PROPERTY_ENTRY_GPIO()`` 47 47 + macro handles this as it is an alias for ``PROPERTY_ENTRY_REF()``. 48 48 + 49 49 + 3. **The reference must have exactly two arguments:** 50 50 + 51 51 + - The first argument is the GPIO offset within the controller. 52 52 + - The second argument is the flags for the GPIO line (e.g., 53 53 + GPIO_ACTIVE_HIGH, GPIO_ACTIVE_LOW). 54 54 + 55 55 + The ``PROPERTY_ENTRY_GPIO()`` macro is the preferred way of defining GPIO 56 56 + properties in software nodes. 57 57 + 58 58 + Conversion Example 59 59 + ------------------ 60 60 + 61 61 + Let's walk through an example of converting a board file that defines a GPIO- 62 62 + connected LED and a button. 63 63 + 64 64 + Before: Using Platform Data 65 65 + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 66 66 + 67 67 + A typical legacy board file might look like this: 68 68 + 69 69 + .. code-block:: c 70 70 + 71 71 + #include <linux/platform_device.h> 72 72 + #include <linux/leds.h> 73 73 + #include <linux/gpio_keys.h> 74 74 + #include <linux/gpio/machine.h> 75 75 + 76 76 + #define MYBOARD_GPIO_CONTROLLER "gpio-foo" 77 77 + 78 78 + /* LED setup */ 79 79 + static const struct gpio_led myboard_leds[] = { 80 80 + { 81 81 + .name = "myboard:green:status", 82 82 + .default_trigger = "heartbeat", 83 83 + }, 84 84 + }; 85 85 + 86 86 + static const struct gpio_led_platform_data myboard_leds_pdata = { 87 87 + .num_leds = ARRAY_SIZE(myboard_leds), 88 88 + .leds = myboard_leds, 89 89 + }; 90 90 + 91 91 + static struct gpiod_lookup_table myboard_leds_gpios = { 92 92 + .dev_id = "leds-gpio", 93 93 + .table = { 94 94 + GPIO_LOOKUP_IDX(MYBOARD_GPIO_CONTROLLER, 42, NULL, 0, GPIO_ACTIVE_HIGH), 95 95 + { }, 96 96 + }, 97 97 + }; 98 98 + 99 99 + /* Button setup */ 100 100 + static struct gpio_keys_button myboard_buttons[] = { 101 101 + { 102 102 + .code = KEY_WPS_BUTTON, 103 103 + .desc = "WPS Button", 104 104 + .active_low = 1, 105 105 + }, 106 106 + }; 107 107 + 108 108 + static const struct gpio_keys_platform_data myboard_buttons_pdata = { 109 109 + .buttons = myboard_buttons, 110 110 + .nbuttons = ARRAY_SIZE(myboard_buttons), 111 111 + }; 112 112 + 113 113 + static struct gpiod_lookup_table myboard_buttons_gpios = { 114 114 + .dev_id = "gpio-keys", 115 115 + .table = { 116 116 + GPIO_LOOKUP_IDX(MYBOARD_GPIO_CONTROLLER, 15, NULL, 0, GPIO_ACTIVE_LOW), 117 117 + { }, 118 118 + }, 119 119 + }; 120 120 + 121 121 + /* Device registration */ 122 122 + static int __init myboard_init(void) 123 123 + { 124 124 + gpiod_add_lookup_table(&myboard_leds_gpios); 125 125 + gpiod_add_lookup_table(&myboard_buttons_gpios); 126 126 + 127 127 + platform_device_register_data(NULL, "leds-gpio", -1, 128 128 + &myboard_leds_pdata, sizeof(myboard_leds_pdata)); 129 129 + platform_device_register_data(NULL, "gpio-keys", -1, 130 130 + &myboard_buttons_pdata, sizeof(myboard_buttons_pdata)); 131 131 + 132 132 + return 0; 133 133 + } 134 134 + 135 135 + After: Using Software Nodes 136 136 + ~~~~~~~~~~~~~~~~~~~~~~~~~~~ 137 137 + 138 138 + Here is how the same configuration can be expressed using software nodes. 139 139 + 140 140 + Step 1: Define the GPIO Controller Node 141 141 + *************************************** 142 142 + 143 143 + First, define a software node that represents the GPIO controller that the 144 144 + LEDs and buttons are connected to. The ``name`` of this node must match the 145 145 + name of the driver for the GPIO controller (e.g., "gpio-foo"). 146 146 + 147 147 + .. code-block:: c 148 148 + 149 149 + #include <linux/property.h> 150 150 + #include <linux/gpio/property.h> 151 151 + 152 152 + #define MYBOARD_GPIO_CONTROLLER "gpio-foo" 153 153 + 154 154 + static const struct software_node myboard_gpio_controller_node = { 155 155 + .name = MYBOARD_GPIO_CONTROLLER, 156 156 + }; 157 157 + 158 158 + Step 2: Define Consumer Device Nodes and Properties 159 159 + *************************************************** 160 160 + 161 161 + Next, define the software nodes for the consumer devices (the LEDs and buttons). 162 162 + This involves creating a parent node for each device type and child nodes for 163 163 + each individual LED or button. 164 164 + 165 165 + .. code-block:: c 166 166 + 167 167 + /* LED setup */ 168 168 + static const struct software_node myboard_leds_node = { 169 169 + .name = "myboard-leds", 170 170 + }; 171 171 + 172 172 + static const struct property_entry myboard_status_led_props[] = { 173 173 + PROPERTY_ENTRY_STRING("label", "myboard:green:status"), 174 174 + PROPERTY_ENTRY_STRING("linux,default-trigger", "heartbeat"), 175 175 + PROPERTY_ENTRY_GPIO("gpios", &myboard_gpio_controller_node, 42, GPIO_ACTIVE_HIGH), 176 176 + { } 177 177 + }; 178 178 + 179 179 + static const struct software_node myboard_status_led_swnode = { 180 180 + .name = "status-led", 181 181 + .parent = &myboard_leds_node, 182 182 + .properties = myboard_status_led_props, 183 183 + }; 184 184 + 185 185 + /* Button setup */ 186 186 + static const struct software_node myboard_keys_node = { 187 187 + .name = "myboard-keys", 188 188 + }; 189 189 + 190 190 + static const struct property_entry myboard_wps_button_props[] = { 191 191 + PROPERTY_ENTRY_STRING("label", "WPS Button"), 192 192 + PROPERTY_ENTRY_U32("linux,code", KEY_WPS_BUTTON), 193 193 + PROPERTY_ENTRY_GPIO("gpios", &myboard_gpio_controller_node, 15, GPIO_ACTIVE_LOW), 194 194 + { } 195 195 + }; 196 196 + 197 197 + static const struct software_node myboard_wps_button_swnode = { 198 198 + .name = "wps-button", 199 199 + .parent = &myboard_keys_node, 200 200 + .properties = myboard_wps_button_props, 201 201 + }; 202 202 + 203 203 + 204 204 + 205 205 + Step 3: Group and Register the Nodes 206 206 + ************************************ 207 207 + 208 208 + For maintainability, it is often beneficial to group all software nodes into a 209 209 + single array and register them with one call. 210 210 + 211 211 + .. code-block:: c 212 212 + 213 213 + static const struct software_node * const myboard_swnodes[] = { 214 214 + &myboard_gpio_controller_node, 215 215 + &myboard_leds_node, 216 216 + &myboard_status_led_swnode, 217 217 + &myboard_keys_node, 218 218 + &myboard_wps_button_swnode, 219 219 + NULL 220 220 + }; 221 221 + 222 222 + static int __init myboard_init(void) 223 223 + { 224 224 + int error; 225 225 + 226 226 + error = software_node_register_node_group(myboard_swnodes); 227 227 + if (error) { 228 228 + pr_err("Failed to register software nodes: %d\n", error); 229 229 + return error; 230 230 + } 231 231 + 232 232 + // ... platform device registration follows 233 233 + } 234 234 + 235 235 + .. note:: 236 236 + When splitting registration of nodes by devices that they represent, it is 237 237 + essential that the software node representing the GPIO controller itself 238 238 + is registered first, before any of the nodes that reference it. 239 239 + 240 240 + Step 4: Register Platform Devices with Software Nodes 241 241 + ***************************************************** 242 242 + 243 243 + Finally, register the platform devices and associate them with their respective 244 244 + software nodes using the ``fwnode`` field in struct platform_device_info. 245 245 + 246 246 + .. code-block:: c 247 247 + 248 248 + static struct platform_device *leds_pdev; 249 249 + static struct platform_device *keys_pdev; 250 250 + 251 251 + static int __init myboard_init(void) 252 252 + { 253 253 + struct platform_device_info pdev_info; 254 254 + int error; 255 255 + 256 256 + error = software_node_register_node_group(myboard_swnodes); 257 257 + if (error) 258 258 + return error; 259 259 + 260 260 + memset(&pdev_info, 0, sizeof(pdev_info)); 261 261 + pdev_info.name = "leds-gpio"; 262 262 + pdev_info.id = PLATFORM_DEVID_NONE; 263 263 + pdev_info.fwnode = software_node_fwnode(&myboard_leds_node); 264 264 + leds_pdev = platform_device_register_full(&pdev_info); 265 265 + if (IS_ERR(leds_pdev)) { 266 266 + error = PTR_ERR(leds_pdev); 267 267 + goto err_unregister_nodes; 268 268 + } 269 269 + 270 270 + memset(&pdev_info, 0, sizeof(pdev_info)); 271 271 + pdev_info.name = "gpio-keys"; 272 272 + pdev_info.id = PLATFORM_DEVID_NONE; 273 273 + pdev_info.fwnode = software_node_fwnode(&myboard_keys_node); 274 274 + keys_pdev = platform_device_register_full(&pdev_info); 275 275 + if (IS_ERR(keys_pdev)) { 276 276 + error = PTR_ERR(keys_pdev); 277 277 + platform_device_unregister(leds_pdev); 278 278 + goto err_unregister_nodes; 279 279 + } 280 280 + 281 281 + return 0; 282 282 + 283 283 + err_unregister_nodes: 284 284 + software_node_unregister_node_group(myboard_swnodes); 285 285 + return error; 286 286 + } 287 287 + 288 288 + static void __exit myboard_exit(void) 289 289 + { 290 290 + platform_device_unregister(keys_pdev); 291 291 + platform_device_unregister(leds_pdev); 292 292 + software_node_unregister_node_group(myboard_swnodes); 293 293 + } 294 294 + 295 295 + With these changes, the generic ``leds-gpio`` and ``gpio-keys`` drivers will 296 296 + be able to probe successfully and get their configuration from the properties 297 297 + defined in the software nodes, removing the need for board-specific platform 298 298 + data.

+25

MAINTAINERS

reviewed

··· 15065 15065 S: Maintained 15066 15066 F: drivers/iio/temperature/max30208.c 15067 15067 15068 15068 + MAXIM MAX7360 KEYPAD LED MFD DRIVER 15069 15069 + M: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 15070 15070 + S: Maintained 15071 15071 + F: Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml 15072 15072 + F: Documentation/devicetree/bindings/mfd/maxim,max7360.yaml 15073 15073 + F: drivers/gpio/gpio-max7360.c 15074 15074 + F: drivers/input/keyboard/max7360-keypad.c 15075 15075 + F: drivers/input/misc/max7360-rotary.c 15076 15076 + F: drivers/mfd/max7360.c 15077 15077 + F: drivers/pinctrl/pinctrl-max7360.c 15078 15078 + F: drivers/pwm/pwm-max7360.c 15079 15079 + F: include/linux/mfd/max7360.h 15080 15080 + 15068 15081 MAXIM MAX77650 PMIC MFD DRIVER 15069 15082 M: Bartosz Golaszewski <brgl@bgdev.pl> 15070 15083 L: linux-kernel@vger.kernel.org ··· 18174 18161 F: drivers/nubus/ 18175 18162 F: include/linux/nubus.h 18176 18163 F: include/uapi/linux/nubus.h 18164 18164 + 18165 18165 + NUVOTON NCT6694 MFD DRIVER 18166 18166 + M: Ming Yu <tmyu0@nuvoton.com> 18167 18167 + S: Supported 18168 18168 + F: drivers/gpio/gpio-nct6694.c 18169 18169 + F: drivers/hwmon/nct6694-hwmon.c 18170 18170 + F: drivers/i2c/busses/i2c-nct6694.c 18171 18171 + F: drivers/mfd/nct6694.c 18172 18172 + F: drivers/net/can/usb/nct6694_canfd.c 18173 18173 + F: drivers/rtc/rtc-nct6694.c 18174 18174 + F: drivers/watchdog/nct6694_wdt.c 18175 18175 + F: include/linux/mfd/nct6694.h 18177 18176 18178 18177 NUVOTON NCT7201 IIO DRIVER 18179 18178 M: Eason Yang <j2anfernee@gmail.com>

+39 -10

drivers/gpio/Kconfig

reviewed

··· 303 303 304 304 config GPIO_EP93XX 305 305 def_bool y 306 306 - depends on ARCH_EP93XX 306 306 + depends on ARCH_EP93XX || COMPILE_TEST 307 307 select GPIO_GENERIC 308 308 select GPIOLIB_IRQCHIP 309 309 ··· 408 408 409 409 config GPIO_IXP4XX 410 410 bool "Intel IXP4xx GPIO" 411 411 - depends on ARCH_IXP4XX 412 412 - depends on OF 411 411 + depends on (ARCH_IXP4XX && OF) || COMPILE_TEST 413 412 select GPIO_GENERIC 414 413 select GPIOLIB_IRQCHIP 415 414 select IRQ_DOMAIN_HIERARCHY ··· 436 437 depends on LOONGARCH || COMPILE_TEST 437 438 depends on OF_GPIO 438 439 select GPIO_GENERIC 440 440 + select GPIOLIB_IRQCHIP 439 441 help 440 442 Say yes here to support the GPIO functionality of a number of 441 443 Loongson series of chips. The Loongson GPIO controller supports ··· 734 734 If built as a module its name will be gpio-tangier. 735 735 736 736 config GPIO_TB10X 737 737 - bool 737 737 + bool "Abilis Systems TB10x GPIO controller" 738 738 + depends on ARC_PLAT_TB10X || COMPILE_TEST 738 739 select GPIO_GENERIC 739 740 select GENERIC_IRQ_CHIP 740 741 select OF_GPIO ··· 884 883 885 884 config GPIO_LOONGSON1 886 885 tristate "Loongson1 GPIO support" 887 887 - depends on MACH_LOONGSON32 886 886 + depends on MACH_LOONGSON32 || COMPILE_TEST 888 887 select GPIO_GENERIC 889 888 help 890 889 Say Y or M here to support GPIO on Loongson1 SoCs. ··· 1194 1193 4 bits: pca9536, pca9537 1195 1194 1196 1195 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, 1197 1197 - pca9556, pca9557, pca9574, tca6408, tca9554, xra1202 1196 1196 + pca9556, pca9557, pca9574, tca6408, tca9554, xra1202, 1197 1197 + pcal6408, pcal9554b, tca9538 1198 1198 1199 1199 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, 1200 1200 - tca6416 1200 1200 + tca6416, pca6416, pcal6416, pcal9535, pcal9555a, max7318, 1201 1201 + tca9539 1201 1202 1202 1202 - 24 bits: tca6424 1203 1203 + 18 bits: tca6418 1203 1204 1204 1204 - 40 bits: pca9505, pca9698 1205 1205 + 24 bits: tca6424, pcal6524 1206 1206 + 1207 1207 + 40 bits: pca9505, pca9698, pca9506 1205 1208 1206 1209 config GPIO_PCA953X_IRQ 1207 1210 bool "Interrupt controller support for PCA953x" ··· 1496 1491 help 1497 1492 Support for GPIOs on Cirrus Logic Madera class codecs. 1498 1493 1494 1494 + config GPIO_MAX7360 1495 1495 + tristate "MAX7360 GPIO support" 1496 1496 + depends on MFD_MAX7360 1497 1497 + select GPIO_REGMAP 1498 1498 + select REGMAP_IRQ 1499 1499 + help 1500 1500 + Allows to use MAX7360 I/O Expander PWM lines as GPIO and keypad COL 1501 1501 + lines as GPO. 1502 1502 + 1503 1503 + This driver can also be built as a module. If so, the module will be 1504 1504 + called gpio-max7360. 1505 1505 + 1499 1506 config GPIO_MAX77620 1500 1507 tristate "GPIO support for PMIC MAX77620 and MAX20024" 1501 1508 depends on MFD_MAX77620 ··· 1537 1520 1538 1521 This driver can also be built as a module. If so, the module will be 1539 1522 called gpio-max77759. 1523 1523 + 1524 1524 + config GPIO_NCT6694 1525 1525 + tristate "Nuvoton NCT6694 GPIO controller support" 1526 1526 + depends on MFD_NCT6694 1527 1527 + select GENERIC_IRQ_CHIP 1528 1528 + select GPIOLIB_IRQCHIP 1529 1529 + help 1530 1530 + This driver supports 8 GPIO pins per bank that can all be interrupt 1531 1531 + sources. 1532 1532 + 1533 1533 + This driver can also be built as a module. If so, the module will be 1534 1534 + called gpio-nct6694. 1540 1535 1541 1536 config GPIO_PALMAS 1542 1537 tristate "TI PALMAS series PMICs GPIO" ··· 1587 1558 called gpio-sl28cpld. 1588 1559 1589 1560 config GPIO_STMPE 1590 1590 - bool "STMPE GPIOs" 1561 1561 + tristate "STMPE GPIOs" 1591 1562 depends on MFD_STMPE 1592 1563 depends on OF_GPIO 1593 1564 select GPIOLIB_IRQCHIP

+2

drivers/gpio/Makefile

reviewed

··· 106 106 obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o 107 107 obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o 108 108 obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o 109 109 + obj-$(CONFIG_GPIO_MAX7360) += gpio-max7360.o 109 110 obj-$(CONFIG_GPIO_MAX77620) += gpio-max77620.o 110 111 obj-$(CONFIG_GPIO_MAX77650) += gpio-max77650.o 111 112 obj-$(CONFIG_GPIO_MAX77759) += gpio-max77759.o ··· 129 128 obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o 130 129 obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o 131 130 obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o 131 131 + obj-$(CONFIG_GPIO_NCT6694) += gpio-nct6694.o 132 132 obj-$(CONFIG_GPIO_NOMADIK) += gpio-nomadik.o 133 133 obj-$(CONFIG_GPIO_NPCM_SGPIO) += gpio-npcm-sgpio.o 134 134 obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o

-17

drivers/gpio/TODO

reviewed

··· 131 131 helpers (x86 inb()/outb()) and convert port-mapped I/O drivers to use 132 132 this with dry-coding and sending to maintainers to test 133 133 134 134 - - Move the MMIO GPIO specific fields out of struct gpio_chip into a 135 135 - dedicated structure. Currently every GPIO chip has them if gpio-mmio is 136 136 - enabled in Kconfig even if it itself doesn't register with the helper 137 137 - library. 138 138 - 139 134 ------------------------------------------------------------------------------- 140 135 141 136 Generic regmap GPIO ··· 168 173 amd, apple), and can be used as examples of how to proceed with this 169 174 conversion. Note that drivers using the generic irqchip framework 170 175 cannot be converted yet, but watch this space! 171 171 - 172 172 - ------------------------------------------------------------------------------- 173 173 - 174 174 - Convert all GPIO chips to using the new, value returning line setters 175 175 - 176 176 - struct gpio_chip's set() and set_multiple() callbacks are now deprecated. They 177 177 - return void and thus do not allow drivers to indicate failure to set the line 178 178 - value back to the caller. 179 179 - 180 180 - We've now added new variants - set_rv() and set_multiple_rv() that return an 181 181 - integer. Let's convert all GPIO drivers treewide to use the new callbacks, 182 182 - remove the old ones and finally rename the new ones back to the old names. 183 176 184 177 ------------------------------------------------------------------------------- 185 178

+353 -57

drivers/gpio/gpio-aggregator.c

reviewed

··· 12 12 #include <linux/configfs.h> 13 13 #include <linux/ctype.h> 14 14 #include <linux/delay.h> 15 15 + #include <linux/export.h> 15 16 #include <linux/idr.h> 16 17 #include <linux/kernel.h> 17 18 #include <linux/list.h> ··· 29 28 30 29 #include <linux/gpio/consumer.h> 31 30 #include <linux/gpio/driver.h> 31 31 + #include <linux/gpio/forwarder.h> 32 32 #include <linux/gpio/machine.h> 33 33 34 34 #include "dev-sync-probe.h" ··· 246 244 spinlock_t slock; /* protects tmp[] if !can_sleep */ 247 245 }; 248 246 struct gpiochip_fwd_timing *delay_timings; 247 247 + void *data; 248 248 + unsigned long *valid_mask; 249 249 unsigned long tmp[]; /* values and descs for multiple ops */ 250 250 }; 251 251 252 252 - #define fwd_tmp_values(fwd) &(fwd)->tmp[0] 253 253 - #define fwd_tmp_descs(fwd) (void *)&(fwd)->tmp[BITS_TO_LONGS((fwd)->chip.ngpio)] 252 252 + #define fwd_tmp_values(fwd) (&(fwd)->tmp[0]) 253 253 + #define fwd_tmp_descs(fwd) ((void *)&(fwd)->tmp[BITS_TO_LONGS((fwd)->chip.ngpio)]) 254 254 255 255 #define fwd_tmp_size(ngpios) (BITS_TO_LONGS((ngpios)) + (ngpios)) 256 256 + 257 257 + static int gpio_fwd_request(struct gpio_chip *chip, unsigned int offset) 258 258 + { 259 259 + struct gpiochip_fwd *fwd = gpiochip_get_data(chip); 260 260 + 261 261 + return test_bit(offset, fwd->valid_mask) ? 0 : -ENODEV; 262 262 + } 256 263 257 264 static int gpio_fwd_get_direction(struct gpio_chip *chip, unsigned int offset) 258 265 { 259 266 struct gpiochip_fwd *fwd = gpiochip_get_data(chip); 267 267 + 268 268 + /* 269 269 + * get_direction() is called during gpiochip registration, return 270 270 + * -ENODEV if there is no GPIO desc for the line. 271 271 + */ 272 272 + if (!test_bit(offset, fwd->valid_mask)) 273 273 + return -ENODEV; 260 274 261 275 return gpiod_get_direction(fwd->descs[offset]); 262 276 } ··· 471 453 return line; 472 454 } 473 455 474 474 - static int gpiochip_fwd_setup_delay_line(struct device *dev, struct gpio_chip *chip, 475 475 - struct gpiochip_fwd *fwd) 456 456 + static int gpiochip_fwd_setup_delay_line(struct gpiochip_fwd *fwd) 476 457 { 477 477 - fwd->delay_timings = devm_kcalloc(dev, chip->ngpio, 458 458 + struct gpio_chip *chip = &fwd->chip; 459 459 + 460 460 + fwd->delay_timings = devm_kcalloc(chip->parent, chip->ngpio, 478 461 sizeof(*fwd->delay_timings), 479 462 GFP_KERNEL); 480 463 if (!fwd->delay_timings) ··· 487 468 return 0; 488 469 } 489 470 #else 490 490 - static int gpiochip_fwd_setup_delay_line(struct device *dev, struct gpio_chip *chip, 491 491 - struct gpiochip_fwd *fwd) 471 471 + static int gpiochip_fwd_setup_delay_line(struct gpiochip_fwd *fwd) 492 472 { 493 473 return 0; 494 474 } 495 475 #endif /* !CONFIG_OF_GPIO */ 496 476 497 477 /** 478 478 + * gpiochip_fwd_get_gpiochip - Get the GPIO chip for the GPIO forwarder 479 479 + * @fwd: GPIO forwarder 480 480 + * 481 481 + * Returns: The GPIO chip for the GPIO forwarder 482 482 + */ 483 483 + struct gpio_chip *gpiochip_fwd_get_gpiochip(struct gpiochip_fwd *fwd) 484 484 + { 485 485 + return &fwd->chip; 486 486 + } 487 487 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_get_gpiochip, "GPIO_FORWARDER"); 488 488 + 489 489 + /** 490 490 + * gpiochip_fwd_get_data - Get driver-private data for the GPIO forwarder 491 491 + * @fwd: GPIO forwarder 492 492 + * 493 493 + * Returns: The driver-private data for the GPIO forwarder 494 494 + */ 495 495 + void *gpiochip_fwd_get_data(struct gpiochip_fwd *fwd) 496 496 + { 497 497 + return fwd->data; 498 498 + } 499 499 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_get_data, "GPIO_FORWARDER"); 500 500 + 501 501 + /** 502 502 + * gpiochip_fwd_gpio_request - Request a line of the GPIO forwarder 503 503 + * @fwd: GPIO forwarder 504 504 + * @offset: the offset of the line to request 505 505 + * 506 506 + * Returns: 0 on success, or negative errno on failure. 507 507 + */ 508 508 + int gpiochip_fwd_gpio_request(struct gpiochip_fwd *fwd, unsigned int offset) 509 509 + { 510 510 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 511 511 + 512 512 + return gpio_fwd_request(gc, offset); 513 513 + } 514 514 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_request, "GPIO_FORWARDER"); 515 515 + 516 516 + /** 517 517 + * gpiochip_fwd_gpio_get_direction - Return the current direction of a GPIO forwarder line 518 518 + * @fwd: GPIO forwarder 519 519 + * @offset: the offset of the line 520 520 + * 521 521 + * Returns: 0 for output, 1 for input, or an error code in case of error. 522 522 + */ 523 523 + int gpiochip_fwd_gpio_get_direction(struct gpiochip_fwd *fwd, unsigned int offset) 524 524 + { 525 525 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 526 526 + 527 527 + return gpio_fwd_get_direction(gc, offset); 528 528 + } 529 529 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_get_direction, "GPIO_FORWARDER"); 530 530 + 531 531 + /** 532 532 + * gpiochip_fwd_gpio_direction_output - Set a GPIO forwarder line direction to 533 533 + * output 534 534 + * @fwd: GPIO forwarder 535 535 + * @offset: the offset of the line 536 536 + * @value: value to set 537 537 + * 538 538 + * Returns: 0 on success, or negative errno on failure. 539 539 + */ 540 540 + int gpiochip_fwd_gpio_direction_output(struct gpiochip_fwd *fwd, unsigned int offset, 541 541 + int value) 542 542 + { 543 543 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 544 544 + 545 545 + return gpio_fwd_direction_output(gc, offset, value); 546 546 + } 547 547 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_direction_output, "GPIO_FORWARDER"); 548 548 + 549 549 + /** 550 550 + * gpiochip_fwd_gpio_direction_input - Set a GPIO forwarder line direction to input 551 551 + * @fwd: GPIO forwarder 552 552 + * @offset: the offset of the line 553 553 + * 554 554 + * Returns: 0 on success, or negative errno on failure. 555 555 + */ 556 556 + int gpiochip_fwd_gpio_direction_input(struct gpiochip_fwd *fwd, unsigned int offset) 557 557 + { 558 558 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 559 559 + 560 560 + return gpio_fwd_direction_input(gc, offset); 561 561 + } 562 562 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_direction_input, "GPIO_FORWARDER"); 563 563 + 564 564 + /** 565 565 + * gpiochip_fwd_gpio_get - Return a GPIO forwarder line's value 566 566 + * @fwd: GPIO forwarder 567 567 + * @offset: the offset of the line 568 568 + * 569 569 + * Returns: The GPIO's logical value, i.e. taking the ACTIVE_LOW status into 570 570 + * account, or negative errno on failure. 571 571 + */ 572 572 + int gpiochip_fwd_gpio_get(struct gpiochip_fwd *fwd, unsigned int offset) 573 573 + { 574 574 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 575 575 + 576 576 + return gpio_fwd_get(gc, offset); 577 577 + } 578 578 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_get, "GPIO_FORWARDER"); 579 579 + 580 580 + /** 581 581 + * gpiochip_fwd_gpio_get_multiple - Get values for multiple GPIO forwarder lines 582 582 + * @fwd: GPIO forwarder 583 583 + * @mask: bit mask array; one bit per line; BITS_PER_LONG bits per word defines 584 584 + * which lines are to be read 585 585 + * @bits: bit value array; one bit per line; BITS_PER_LONG bits per word will 586 586 + * contains the read values for the lines specified by mask 587 587 + * 588 588 + * Returns: 0 on success, or negative errno on failure. 589 589 + */ 590 590 + int gpiochip_fwd_gpio_get_multiple(struct gpiochip_fwd *fwd, unsigned long *mask, 591 591 + unsigned long *bits) 592 592 + { 593 593 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 594 594 + 595 595 + return gpio_fwd_get_multiple_locked(gc, mask, bits); 596 596 + } 597 597 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_get_multiple, "GPIO_FORWARDER"); 598 598 + 599 599 + /** 600 600 + * gpiochip_fwd_gpio_set - Assign value to a GPIO forwarder line. 601 601 + * @fwd: GPIO forwarder 602 602 + * @offset: the offset of the line 603 603 + * @value: value to set 604 604 + * 605 605 + * Returns: 0 on success, or negative errno on failure. 606 606 + */ 607 607 + int gpiochip_fwd_gpio_set(struct gpiochip_fwd *fwd, unsigned int offset, int value) 608 608 + { 609 609 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 610 610 + 611 611 + return gpio_fwd_set(gc, offset, value); 612 612 + } 613 613 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_set, "GPIO_FORWARDER"); 614 614 + 615 615 + /** 616 616 + * gpiochip_fwd_gpio_set_multiple - Assign values to multiple GPIO forwarder lines 617 617 + * @fwd: GPIO forwarder 618 618 + * @mask: bit mask array; one bit per output; BITS_PER_LONG bits per word 619 619 + * defines which outputs are to be changed 620 620 + * @bits: bit value array; one bit per output; BITS_PER_LONG bits per word 621 621 + * defines the values the outputs specified by mask are to be set to 622 622 + * 623 623 + * Returns: 0 on success, or negative errno on failure. 624 624 + */ 625 625 + int gpiochip_fwd_gpio_set_multiple(struct gpiochip_fwd *fwd, unsigned long *mask, 626 626 + unsigned long *bits) 627 627 + { 628 628 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 629 629 + 630 630 + return gpio_fwd_set_multiple_locked(gc, mask, bits); 631 631 + } 632 632 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_set_multiple, "GPIO_FORWARDER"); 633 633 + 634 634 + /** 635 635 + * gpiochip_fwd_gpio_set_config - Set @config for a GPIO forwarder line 636 636 + * @fwd: GPIO forwarder 637 637 + * @offset: the offset of the line 638 638 + * @config: Same packed config format as generic pinconf 639 639 + * 640 640 + * Returns: 0 on success, %-ENOTSUPP if the controller doesn't support setting 641 641 + * the configuration. 642 642 + */ 643 643 + int gpiochip_fwd_gpio_set_config(struct gpiochip_fwd *fwd, unsigned int offset, 644 644 + unsigned long config) 645 645 + { 646 646 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 647 647 + 648 648 + return gpio_fwd_set_config(gc, offset, config); 649 649 + } 650 650 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_set_config, "GPIO_FORWARDER"); 651 651 + 652 652 + /** 653 653 + * gpiochip_fwd_gpio_to_irq - Return the IRQ corresponding to a GPIO forwarder line 654 654 + * @fwd: GPIO forwarder 655 655 + * @offset: the offset of the line 656 656 + * 657 657 + * Returns: The Linux IRQ corresponding to the passed line, or an error code in 658 658 + * case of error. 659 659 + */ 660 660 + int gpiochip_fwd_gpio_to_irq(struct gpiochip_fwd *fwd, unsigned int offset) 661 661 + { 662 662 + struct gpio_chip *gc = gpiochip_fwd_get_gpiochip(fwd); 663 663 + 664 664 + return gpio_fwd_to_irq(gc, offset); 665 665 + } 666 666 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_gpio_to_irq, "GPIO_FORWARDER"); 667 667 + 668 668 + /** 669 669 + * devm_gpiochip_fwd_alloc - Allocate and initialize a new GPIO forwarder 670 670 + * @dev: Parent device pointer 671 671 + * @ngpios: Number of GPIOs in the forwarder 672 672 + * 673 673 + * Returns: An opaque object pointer, or an ERR_PTR()-encoded negative error 674 674 + * code on failure. 675 675 + */ 676 676 + struct gpiochip_fwd *devm_gpiochip_fwd_alloc(struct device *dev, 677 677 + unsigned int ngpios) 678 678 + { 679 679 + struct gpiochip_fwd *fwd; 680 680 + struct gpio_chip *chip; 681 681 + 682 682 + fwd = devm_kzalloc(dev, struct_size(fwd, tmp, fwd_tmp_size(ngpios)), GFP_KERNEL); 683 683 + if (!fwd) 684 684 + return ERR_PTR(-ENOMEM); 685 685 + 686 686 + fwd->descs = devm_kcalloc(dev, ngpios, sizeof(*fwd->descs), GFP_KERNEL); 687 687 + if (!fwd->descs) 688 688 + return ERR_PTR(-ENOMEM); 689 689 + 690 690 + fwd->valid_mask = devm_bitmap_zalloc(dev, ngpios, GFP_KERNEL); 691 691 + if (!fwd->valid_mask) 692 692 + return ERR_PTR(-ENOMEM); 693 693 + 694 694 + chip = &fwd->chip; 695 695 + 696 696 + chip->label = dev_name(dev); 697 697 + chip->parent = dev; 698 698 + chip->owner = THIS_MODULE; 699 699 + chip->request = gpio_fwd_request; 700 700 + chip->get_direction = gpio_fwd_get_direction; 701 701 + chip->direction_input = gpio_fwd_direction_input; 702 702 + chip->direction_output = gpio_fwd_direction_output; 703 703 + chip->get = gpio_fwd_get; 704 704 + chip->get_multiple = gpio_fwd_get_multiple_locked; 705 705 + chip->set = gpio_fwd_set; 706 706 + chip->set_multiple = gpio_fwd_set_multiple_locked; 707 707 + chip->to_irq = gpio_fwd_to_irq; 708 708 + chip->base = -1; 709 709 + chip->ngpio = ngpios; 710 710 + 711 711 + return fwd; 712 712 + } 713 713 + EXPORT_SYMBOL_NS_GPL(devm_gpiochip_fwd_alloc, "GPIO_FORWARDER"); 714 714 + 715 715 + /** 716 716 + * gpiochip_fwd_desc_add - Add a GPIO desc in the forwarder 717 717 + * @fwd: GPIO forwarder 718 718 + * @desc: GPIO descriptor to register 719 719 + * @offset: offset for the GPIO in the forwarder 720 720 + * 721 721 + * Returns: 0 on success, or negative errno on failure. 722 722 + */ 723 723 + int gpiochip_fwd_desc_add(struct gpiochip_fwd *fwd, struct gpio_desc *desc, 724 724 + unsigned int offset) 725 725 + { 726 726 + struct gpio_chip *chip = &fwd->chip; 727 727 + 728 728 + if (offset >= chip->ngpio) 729 729 + return -EINVAL; 730 730 + 731 731 + if (test_and_set_bit(offset, fwd->valid_mask)) 732 732 + return -EEXIST; 733 733 + 734 734 + /* 735 735 + * If any of the GPIO lines are sleeping, then the entire forwarder 736 736 + * will be sleeping. 737 737 + */ 738 738 + if (gpiod_cansleep(desc)) 739 739 + chip->can_sleep = true; 740 740 + 741 741 + fwd->descs[offset] = desc; 742 742 + 743 743 + dev_dbg(chip->parent, "%u => gpio %d irq %d\n", offset, 744 744 + desc_to_gpio(desc), gpiod_to_irq(desc)); 745 745 + 746 746 + return 0; 747 747 + } 748 748 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_desc_add, "GPIO_FORWARDER"); 749 749 + 750 750 + /** 751 751 + * gpiochip_fwd_desc_free - Remove a GPIO desc from the forwarder 752 752 + * @fwd: GPIO forwarder 753 753 + * @offset: offset of GPIO desc to remove 754 754 + */ 755 755 + void gpiochip_fwd_desc_free(struct gpiochip_fwd *fwd, unsigned int offset) 756 756 + { 757 757 + if (test_and_clear_bit(offset, fwd->valid_mask)) 758 758 + gpiod_put(fwd->descs[offset]); 759 759 + } 760 760 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_desc_free, "GPIO_FORWARDER"); 761 761 + 762 762 + /** 763 763 + * gpiochip_fwd_register - Register a GPIO forwarder 764 764 + * @fwd: GPIO forwarder 765 765 + * @data: driver-private data associated with this forwarder 766 766 + * 767 767 + * Returns: 0 on success, or negative errno on failure. 768 768 + */ 769 769 + int gpiochip_fwd_register(struct gpiochip_fwd *fwd, void *data) 770 770 + { 771 771 + struct gpio_chip *chip = &fwd->chip; 772 772 + 773 773 + /* 774 774 + * Some gpio_desc were not registered. They will be registered at runtime 775 775 + * but we have to suppose they can sleep. 776 776 + */ 777 777 + if (!bitmap_full(fwd->valid_mask, chip->ngpio)) 778 778 + chip->can_sleep = true; 779 779 + 780 780 + if (chip->can_sleep) 781 781 + mutex_init(&fwd->mlock); 782 782 + else 783 783 + spin_lock_init(&fwd->slock); 784 784 + 785 785 + fwd->data = data; 786 786 + 787 787 + return devm_gpiochip_add_data(chip->parent, chip, fwd); 788 788 + } 789 789 + EXPORT_SYMBOL_NS_GPL(gpiochip_fwd_register, "GPIO_FORWARDER"); 790 790 + 791 791 + /** 498 792 * gpiochip_fwd_create() - Create a new GPIO forwarder 499 793 * @dev: Parent device pointer 500 794 * @ngpios: Number of GPIOs in the forwarder. 501 795 * @descs: Array containing the GPIO descriptors to forward to. 502 502 - * This array must contain @ngpios entries, and must not be deallocated 503 503 - * before the forwarder has been destroyed again. 796 796 + * This array must contain @ngpios entries, and can be deallocated 797 797 + * as the forwarder has its own array. 504 798 * @features: Bitwise ORed features as defined with FWD_FEATURE_*. 505 799 * 506 800 * This function creates a new gpiochip, which forwards all GPIO operations to ··· 827 495 struct gpio_desc *descs[], 828 496 unsigned long features) 829 497 { 830 830 - const char *label = dev_name(dev); 831 498 struct gpiochip_fwd *fwd; 832 832 - struct gpio_chip *chip; 833 499 unsigned int i; 834 500 int error; 835 501 836 836 - fwd = devm_kzalloc(dev, struct_size(fwd, tmp, fwd_tmp_size(ngpios)), 837 837 - GFP_KERNEL); 838 838 - if (!fwd) 839 839 - return ERR_PTR(-ENOMEM); 502 502 + fwd = devm_gpiochip_fwd_alloc(dev, ngpios); 503 503 + if (IS_ERR(fwd)) 504 504 + return fwd; 840 505 841 841 - chip = &fwd->chip; 842 842 - 843 843 - /* 844 844 - * If any of the GPIO lines are sleeping, then the entire forwarder 845 845 - * will be sleeping. 846 846 - * If any of the chips support .set_config(), then the forwarder will 847 847 - * support setting configs. 848 848 - */ 849 506 for (i = 0; i < ngpios; i++) { 850 850 - struct gpio_chip *parent = gpiod_to_chip(descs[i]); 851 851 - 852 852 - dev_dbg(dev, "%u => gpio %d irq %d\n", i, 853 853 - desc_to_gpio(descs[i]), gpiod_to_irq(descs[i])); 854 854 - 855 855 - if (gpiod_cansleep(descs[i])) 856 856 - chip->can_sleep = true; 857 857 - if (parent && parent->set_config) 858 858 - chip->set_config = gpio_fwd_set_config; 859 859 - } 860 860 - 861 861 - chip->label = label; 862 862 - chip->parent = dev; 863 863 - chip->owner = THIS_MODULE; 864 864 - chip->get_direction = gpio_fwd_get_direction; 865 865 - chip->direction_input = gpio_fwd_direction_input; 866 866 - chip->direction_output = gpio_fwd_direction_output; 867 867 - chip->get = gpio_fwd_get; 868 868 - chip->get_multiple = gpio_fwd_get_multiple_locked; 869 869 - chip->set = gpio_fwd_set; 870 870 - chip->set_multiple = gpio_fwd_set_multiple_locked; 871 871 - chip->to_irq = gpio_fwd_to_irq; 872 872 - chip->base = -1; 873 873 - chip->ngpio = ngpios; 874 874 - fwd->descs = descs; 875 875 - 876 876 - if (chip->can_sleep) 877 877 - mutex_init(&fwd->mlock); 878 878 - else 879 879 - spin_lock_init(&fwd->slock); 880 880 - 881 881 - if (features & FWD_FEATURE_DELAY) { 882 882 - error = gpiochip_fwd_setup_delay_line(dev, chip, fwd); 507 507 + error = gpiochip_fwd_desc_add(fwd, descs[i], i); 883 508 if (error) 884 509 return ERR_PTR(error); 885 510 } 886 511 887 887 - error = devm_gpiochip_add_data(dev, chip, fwd); 512 512 + if (features & FWD_FEATURE_DELAY) { 513 513 + error = gpiochip_fwd_setup_delay_line(fwd); 514 514 + if (error) 515 515 + return ERR_PTR(error); 516 516 + } 517 517 + 518 518 + error = gpiochip_fwd_register(fwd, NULL); 888 519 if (error) 889 520 return ERR_PTR(error); 890 521 ··· 1629 1334 return PTR_ERR(fwd); 1630 1335 1631 1336 platform_set_drvdata(pdev, fwd); 1337 1337 + devm_kfree(dev, descs); 1632 1338 return 0; 1633 1339 } 1634 1340

+23 -21

drivers/gpio/gpio-amdpt.c

reviewed

··· 9 9 #include <linux/kernel.h> 10 10 #include <linux/module.h> 11 11 #include <linux/gpio/driver.h> 12 12 + #include <linux/gpio/generic.h> 12 13 #include <linux/spinlock.h> 13 14 #include <linux/acpi.h> 14 15 #include <linux/platform_device.h> ··· 25 24 #define PT_SYNC_REG 0x28 26 25 27 26 struct pt_gpio_chip { 28 28 - struct gpio_chip gc; 27 27 + struct gpio_generic_chip chip; 29 28 void __iomem *reg_base; 30 29 }; 31 30 32 31 static int pt_gpio_request(struct gpio_chip *gc, unsigned offset) 33 32 { 33 33 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 34 34 struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc); 35 35 - unsigned long flags; 36 35 u32 using_pins; 37 36 38 37 dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset); 39 38 40 40 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 39 39 + guard(gpio_generic_lock_irqsave)(gen_gc); 41 40 42 41 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); 43 42 if (using_pins & BIT(offset)) { 44 43 dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n", 45 44 offset); 46 46 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 47 45 return -EINVAL; 48 46 } 49 47 50 48 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); 51 51 - 52 52 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 53 49 54 50 return 0; 55 51 } 56 52 57 53 static void pt_gpio_free(struct gpio_chip *gc, unsigned offset) 58 54 { 55 55 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 59 56 struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc); 60 60 - unsigned long flags; 61 57 u32 using_pins; 62 58 63 63 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 59 59 + guard(gpio_generic_lock_irqsave)(gen_gc); 64 60 65 61 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); 66 62 using_pins &= ~BIT(offset); 67 63 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); 68 68 - 69 69 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 70 64 71 65 dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset); 72 66 } 73 67 74 68 static int pt_gpio_probe(struct platform_device *pdev) 75 69 { 70 70 + struct gpio_generic_chip_config config; 76 71 struct device *dev = &pdev->dev; 77 72 struct pt_gpio_chip *pt_gpio; 78 73 int ret = 0; ··· 88 91 return PTR_ERR(pt_gpio->reg_base); 89 92 } 90 93 91 91 - ret = bgpio_init(&pt_gpio->gc, dev, 4, 92 92 - pt_gpio->reg_base + PT_INPUTDATA_REG, 93 93 - pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, 94 94 - pt_gpio->reg_base + PT_DIRECTION_REG, NULL, 95 95 - BGPIOF_READ_OUTPUT_REG_SET); 94 94 + config = (struct gpio_generic_chip_config) { 95 95 + .dev = dev, 96 96 + .sz = 4, 97 97 + .dat = pt_gpio->reg_base + PT_INPUTDATA_REG, 98 98 + .set = pt_gpio->reg_base + PT_OUTPUTDATA_REG, 99 99 + .dirout = pt_gpio->reg_base + PT_DIRECTION_REG, 100 100 + .flags = GPIO_GENERIC_READ_OUTPUT_REG_SET, 101 101 + }; 102 102 + 103 103 + ret = gpio_generic_chip_init(&pt_gpio->chip, &config); 96 104 if (ret) { 97 97 - dev_err(dev, "bgpio_init failed\n"); 105 105 + dev_err(dev, "failed to initialize the generic GPIO chip\n"); 98 106 return ret; 99 107 } 100 108 101 101 - pt_gpio->gc.owner = THIS_MODULE; 102 102 - pt_gpio->gc.request = pt_gpio_request; 103 103 - pt_gpio->gc.free = pt_gpio_free; 104 104 - pt_gpio->gc.ngpio = (uintptr_t)device_get_match_data(dev); 109 109 + pt_gpio->chip.gc.owner = THIS_MODULE; 110 110 + pt_gpio->chip.gc.request = pt_gpio_request; 111 111 + pt_gpio->chip.gc.free = pt_gpio_free; 112 112 + pt_gpio->chip.gc.ngpio = (uintptr_t)device_get_match_data(dev); 105 113 106 106 - ret = devm_gpiochip_add_data(dev, &pt_gpio->gc, pt_gpio); 114 114 + ret = devm_gpiochip_add_data(dev, &pt_gpio->chip.gc, pt_gpio); 107 115 if (ret) { 108 116 dev_err(dev, "Failed to register GPIO lib\n"); 109 117 return ret;

+42 -46

drivers/gpio/gpio-ath79.c

reviewed

··· 10 10 11 11 #include <linux/device.h> 12 12 #include <linux/gpio/driver.h> 13 13 + #include <linux/gpio/generic.h> 13 14 #include <linux/interrupt.h> 14 15 #include <linux/irq.h> 15 16 #include <linux/mod_devicetable.h> ··· 29 28 #define AR71XX_GPIO_REG_INT_MASK 0x24 30 29 31 30 struct ath79_gpio_ctrl { 32 32 - struct gpio_chip gc; 31 31 + struct gpio_generic_chip chip; 33 32 void __iomem *base; 34 34 - raw_spinlock_t lock; 35 33 unsigned long both_edges; 36 34 }; 37 35 38 36 static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data) 39 37 { 40 38 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 39 39 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 41 40 42 42 - return container_of(gc, struct ath79_gpio_ctrl, gc); 41 41 + return container_of(gen_gc, struct ath79_gpio_ctrl, chip); 43 42 } 44 43 45 44 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) ··· 71 70 { 72 71 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 73 72 u32 mask = BIT(irqd_to_hwirq(data)); 74 74 - unsigned long flags; 75 73 76 76 - gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data)); 77 77 - raw_spin_lock_irqsave(&ctrl->lock, flags); 74 74 + gpiochip_enable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); 75 75 + 76 76 + guard(gpio_generic_lock_irqsave)(&ctrl->chip); 77 77 + 78 78 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 79 79 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); 80 79 } 81 80 82 81 static void ath79_gpio_irq_mask(struct irq_data *data) 83 82 { 84 83 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 85 84 u32 mask = BIT(irqd_to_hwirq(data)); 86 86 - unsigned long flags; 87 85 88 88 - raw_spin_lock_irqsave(&ctrl->lock, flags); 89 89 - ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 90 90 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); 91 91 - gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data)); 86 86 + scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) 87 87 + ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 88 88 + 89 89 + gpiochip_disable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); 92 90 } 93 91 94 92 static void ath79_gpio_irq_enable(struct irq_data *data) 95 93 { 96 94 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 97 95 u32 mask = BIT(irqd_to_hwirq(data)); 98 98 - unsigned long flags; 99 96 100 100 - raw_spin_lock_irqsave(&ctrl->lock, flags); 97 97 + guard(gpio_generic_lock_irqsave)(&ctrl->chip); 101 98 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 102 99 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 103 103 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); 104 100 } 105 101 106 102 static void ath79_gpio_irq_disable(struct irq_data *data) 107 103 { 108 104 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 109 105 u32 mask = BIT(irqd_to_hwirq(data)); 110 110 - unsigned long flags; 111 106 112 112 - raw_spin_lock_irqsave(&ctrl->lock, flags); 107 107 + guard(gpio_generic_lock_irqsave)(&ctrl->chip); 113 108 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 114 109 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 115 115 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); 116 110 } 117 111 118 112 static int ath79_gpio_irq_set_type(struct irq_data *data, ··· 116 120 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 117 121 u32 mask = BIT(irqd_to_hwirq(data)); 118 122 u32 type = 0, polarity = 0; 119 119 - unsigned long flags; 120 123 bool disabled; 121 124 122 125 switch (flow_type) { ··· 137 142 return -EINVAL; 138 143 } 139 144 140 140 - raw_spin_lock_irqsave(&ctrl->lock, flags); 145 145 + guard(gpio_generic_lock_irqsave)(&ctrl->chip); 141 146 142 147 if (flow_type == IRQ_TYPE_EDGE_BOTH) { 143 148 ctrl->both_edges |= mask; ··· 162 167 ath79_gpio_update_bits( 163 168 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 164 169 165 165 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); 166 166 - 167 170 return 0; 168 171 } 169 172 ··· 180 187 { 181 188 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 182 189 struct irq_chip *irqchip = irq_desc_get_chip(desc); 190 190 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 183 191 struct ath79_gpio_ctrl *ctrl = 184 184 - container_of(gc, struct ath79_gpio_ctrl, gc); 185 185 - unsigned long flags, pending; 192 192 + container_of(gen_gc, struct ath79_gpio_ctrl, chip); 193 193 + unsigned long pending; 186 194 u32 both_edges, state; 187 195 int irq; 188 196 189 197 chained_irq_enter(irqchip, desc); 190 198 191 191 - raw_spin_lock_irqsave(&ctrl->lock, flags); 199 199 + scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) { 200 200 + pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); 192 201 193 193 - pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); 194 194 - 195 195 - /* Update the polarity of the both edges irqs */ 196 196 - both_edges = ctrl->both_edges & pending; 197 197 - if (both_edges) { 198 198 - state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 199 199 - ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, 200 200 - both_edges, ~state); 202 202 + /* Update the polarity of the both edges irqs */ 203 203 + both_edges = ctrl->both_edges & pending; 204 204 + if (both_edges) { 205 205 + state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 206 206 + ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, 207 207 + both_edges, ~state); 208 208 + } 201 209 } 202 202 - 203 203 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); 204 210 205 211 for_each_set_bit(irq, &pending, gc->ngpio) 206 212 generic_handle_domain_irq(gc->irq.domain, irq); ··· 216 224 217 225 static int ath79_gpio_probe(struct platform_device *pdev) 218 226 { 227 227 + struct gpio_generic_chip_config config; 219 228 struct device *dev = &pdev->dev; 220 229 struct ath79_gpio_ctrl *ctrl; 221 230 struct gpio_irq_chip *girq; ··· 245 252 if (IS_ERR(ctrl->base)) 246 253 return PTR_ERR(ctrl->base); 247 254 248 248 - raw_spin_lock_init(&ctrl->lock); 249 249 - err = bgpio_init(&ctrl->gc, dev, 4, 250 250 - ctrl->base + AR71XX_GPIO_REG_IN, 251 251 - ctrl->base + AR71XX_GPIO_REG_SET, 252 252 - ctrl->base + AR71XX_GPIO_REG_CLEAR, 253 253 - oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, 254 254 - oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, 255 255 - 0); 255 255 + config = (struct gpio_generic_chip_config) { 256 256 + .dev = dev, 257 257 + .sz = 4, 258 258 + .dat = ctrl->base + AR71XX_GPIO_REG_IN, 259 259 + .set = ctrl->base + AR71XX_GPIO_REG_SET, 260 260 + .clr = ctrl->base + AR71XX_GPIO_REG_CLEAR, 261 261 + .dirout = oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, 262 262 + .dirin = oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, 263 263 + }; 264 264 + 265 265 + err = gpio_generic_chip_init(&ctrl->chip, &config); 256 266 if (err) { 257 257 - dev_err(dev, "bgpio_init failed\n"); 267 267 + dev_err(dev, "failed to initialize generic GPIO chip\n"); 258 268 return err; 259 269 } 260 270 261 271 /* Optional interrupt setup */ 262 272 if (device_property_read_bool(dev, "interrupt-controller")) { 263 263 - girq = &ctrl->gc.irq; 273 273 + girq = &ctrl->chip.gc.irq; 264 274 gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip); 265 275 girq->parent_handler = ath79_gpio_irq_handler; 266 276 girq->num_parents = 1; ··· 276 280 girq->handler = handle_simple_irq; 277 281 } 278 282 279 279 - return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); 283 283 + return devm_gpiochip_add_data(dev, &ctrl->chip.gc, ctrl); 280 284 } 281 285 282 286 static struct platform_driver ath79_gpio_driver = {

+24 -15

drivers/gpio/gpio-blzp1600.c

reviewed

··· 6 6 7 7 #include <linux/errno.h> 8 8 #include <linux/gpio/driver.h> 9 9 + #include <linux/gpio/generic.h> 9 10 #include <linux/init.h> 10 11 #include <linux/interrupt.h> 11 12 #include <linux/io.h> ··· 37 36 38 37 struct blzp1600_gpio { 39 38 void __iomem *base; 40 40 - struct gpio_chip gc; 39 39 + struct gpio_generic_chip gen_gc; 41 40 int irq; 42 41 }; 43 42 ··· 77 76 { 78 77 struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); 79 78 80 80 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); 79 79 + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); 81 80 blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 1); 82 81 } 83 82 ··· 85 84 { 86 85 struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); 87 86 88 88 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); 87 87 + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); 89 88 blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 0); 90 89 } 91 90 ··· 100 99 { 101 100 struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); 102 101 103 103 - gpiochip_enable_irq(&chip->gc, irqd_to_hwirq(d)); 102 102 + gpiochip_enable_irq(&chip->gen_gc.gc, irqd_to_hwirq(d)); 104 103 105 105 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); 104 104 + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); 106 105 blzp1600_gpio_rmw(chip->base + GPIO_DIR_REG, BIT(d->hwirq), 0); 107 106 blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 1); 108 107 } ··· 111 110 { 112 111 struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d); 113 112 114 114 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); 113 113 + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); 115 114 blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 0); 116 116 - gpiochip_disable_irq(&chip->gc, irqd_to_hwirq(d)); 115 115 + gpiochip_disable_irq(&chip->gen_gc.gc, irqd_to_hwirq(d)); 117 116 } 118 117 119 118 static int blzp1600_gpio_irq_set_type(struct irq_data *d, u32 type) ··· 122 121 u32 edge_level, single_both, fall_rise; 123 122 int mask = BIT(d->hwirq); 124 123 125 125 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); 124 124 + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); 126 125 edge_level = blzp1600_gpio_read(chip, GPIO_IS_REG); 127 126 single_both = blzp1600_gpio_read(chip, GPIO_IBE_REG); 128 127 fall_rise = blzp1600_gpio_read(chip, GPIO_IEV_REG); ··· 187 186 188 187 chained_irq_enter(irqchip, desc); 189 188 irq_status = blzp1600_gpio_read(gpio, GPIO_RIS_REG); 190 190 - for_each_set_bit(hwirq, &irq_status, gpio->gc.ngpio) 191 191 - generic_handle_domain_irq(gpio->gc.irq.domain, hwirq); 189 189 + for_each_set_bit(hwirq, &irq_status, gpio->gen_gc.gc.ngpio) 190 190 + generic_handle_domain_irq(gpio->gen_gc.gc.irq.domain, hwirq); 192 191 193 192 chained_irq_exit(irqchip, desc); 194 193 } ··· 198 197 { 199 198 struct blzp1600_gpio *chip = gpiochip_get_data(gc); 200 199 201 201 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); 200 200 + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); 202 201 blzp1600_gpio_rmw(chip->base + GPIO_DB_REG, BIT(offset), debounce); 203 202 204 203 return 0; ··· 217 216 218 217 static int blzp1600_gpio_probe(struct platform_device *pdev) 219 218 { 219 219 + struct gpio_generic_chip_config config; 220 220 struct blzp1600_gpio *chip; 221 221 struct gpio_chip *gc; 222 222 int ret; ··· 230 228 if (IS_ERR(chip->base)) 231 229 return PTR_ERR(chip->base); 232 230 233 233 - ret = bgpio_init(&chip->gc, &pdev->dev, 4, chip->base + GPIO_IDATA_REG, 234 234 - chip->base + GPIO_SET_REG, chip->base + GPIO_CLR_REG, 235 235 - chip->base + GPIO_DIR_REG, NULL, 0); 231 231 + config = (struct gpio_generic_chip_config) { 232 232 + .dev = &pdev->dev, 233 233 + .sz = 4, 234 234 + .dat = chip->base + GPIO_IDATA_REG, 235 235 + .set = chip->base + GPIO_SET_REG, 236 236 + .clr = chip->base + GPIO_CLR_REG, 237 237 + .dirout = chip->base + GPIO_DIR_REG, 238 238 + }; 239 239 + 240 240 + ret = gpio_generic_chip_init(&chip->gen_gc, &config); 236 241 if (ret) 237 242 return dev_err_probe(&pdev->dev, ret, "Failed to register generic gpio\n"); 238 243 239 244 /* configure the gpio chip */ 240 240 - gc = &chip->gc; 245 245 + gc = &chip->gen_gc.gc; 241 246 gc->set_config = blzp1600_gpio_set_config; 242 247 243 248 if (device_property_present(&pdev->dev, "interrupt-controller")) {

+61 -53

drivers/gpio/gpio-brcmstb.c

reviewed

··· 3 3 4 4 #include <linux/bitops.h> 5 5 #include <linux/gpio/driver.h> 6 6 + #include <linux/gpio/generic.h> 6 7 #include <linux/of.h> 7 8 #include <linux/module.h> 8 9 #include <linux/irqdomain.h> ··· 38 37 struct brcmstb_gpio_bank { 39 38 struct list_head node; 40 39 int id; 41 41 - struct gpio_chip gc; 40 40 + struct gpio_generic_chip chip; 42 41 struct brcmstb_gpio_priv *parent_priv; 43 42 u32 width; 44 43 u32 wake_active; ··· 73 72 { 74 73 void __iomem *reg_base = bank->parent_priv->reg_base; 75 74 76 76 - return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & 77 77 - bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); 75 75 + return gpio_generic_read_reg(&bank->chip, reg_base + GIO_STAT(bank->id)) & 76 76 + gpio_generic_read_reg(&bank->chip, reg_base + GIO_MASK(bank->id)); 78 77 } 79 78 80 79 static unsigned long 81 80 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) 82 81 { 83 82 unsigned long status; 84 84 - unsigned long flags; 85 83 86 86 - raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 84 84 + guard(gpio_generic_lock_irqsave)(&bank->chip); 85 85 + 87 86 status = __brcmstb_gpio_get_active_irqs(bank); 88 88 - raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 89 87 90 88 return status; 91 89 } ··· 92 92 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq, 93 93 struct brcmstb_gpio_bank *bank) 94 94 { 95 95 - return hwirq - bank->gc.offset; 95 95 + return hwirq - bank->chip.gc.offset; 96 96 } 97 97 98 98 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, 99 99 unsigned int hwirq, bool enable) 100 100 { 101 101 - struct gpio_chip *gc = &bank->gc; 102 101 struct brcmstb_gpio_priv *priv = bank->parent_priv; 103 102 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); 104 103 u32 imask; 105 105 - unsigned long flags; 106 104 107 107 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 108 108 - imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); 105 105 + guard(gpio_generic_lock_irqsave)(&bank->chip); 106 106 + 107 107 + imask = gpio_generic_read_reg(&bank->chip, 108 108 + priv->reg_base + GIO_MASK(bank->id)); 109 109 if (enable) 110 110 imask |= mask; 111 111 else 112 112 imask &= ~mask; 113 113 - gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); 114 114 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 113 113 + gpio_generic_write_reg(&bank->chip, 114 114 + priv->reg_base + GIO_MASK(bank->id), imask); 115 115 } 116 116 117 117 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) ··· 150 150 struct brcmstb_gpio_priv *priv = bank->parent_priv; 151 151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); 152 152 153 153 - gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); 153 153 + gpio_generic_write_reg(&bank->chip, 154 154 + priv->reg_base + GIO_STAT(bank->id), mask); 154 155 } 155 156 156 157 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type) ··· 163 162 u32 edge_insensitive, iedge_insensitive; 164 163 u32 edge_config, iedge_config; 165 164 u32 level, ilevel; 166 166 - unsigned long flags; 167 165 168 166 switch (type) { 169 167 case IRQ_TYPE_LEVEL_LOW: ··· 194 194 return -EINVAL; 195 195 } 196 196 197 197 - raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 197 197 + guard(gpio_generic_lock_irqsave)(&bank->chip); 198 198 199 199 - iedge_config = bank->gc.read_reg(priv->reg_base + 200 200 - GIO_EC(bank->id)) & ~mask; 201 201 - iedge_insensitive = bank->gc.read_reg(priv->reg_base + 202 202 - GIO_EI(bank->id)) & ~mask; 203 203 - ilevel = bank->gc.read_reg(priv->reg_base + 204 204 - GIO_LEVEL(bank->id)) & ~mask; 199 199 + iedge_config = gpio_generic_read_reg(&bank->chip, 200 200 + priv->reg_base + GIO_EC(bank->id)) & ~mask; 201 201 + iedge_insensitive = gpio_generic_read_reg(&bank->chip, 202 202 + priv->reg_base + GIO_EI(bank->id)) & ~mask; 203 203 + ilevel = gpio_generic_read_reg(&bank->chip, 204 204 + priv->reg_base + GIO_LEVEL(bank->id)) & ~mask; 205 205 206 206 - bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), 207 207 - iedge_config | edge_config); 208 208 - bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), 209 209 - iedge_insensitive | edge_insensitive); 210 210 - bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), 211 211 - ilevel | level); 206 206 + gpio_generic_write_reg(&bank->chip, 207 207 + priv->reg_base + GIO_EC(bank->id), 208 208 + iedge_config | edge_config); 209 209 + gpio_generic_write_reg(&bank->chip, 210 210 + priv->reg_base + GIO_EI(bank->id), 211 211 + iedge_insensitive | edge_insensitive); 212 212 + gpio_generic_write_reg(&bank->chip, 213 213 + priv->reg_base + GIO_LEVEL(bank->id), 214 214 + ilevel | level); 212 215 213 213 - raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 214 216 return 0; 215 217 } 216 218 ··· 265 263 { 266 264 struct brcmstb_gpio_priv *priv = bank->parent_priv; 267 265 struct irq_domain *domain = priv->irq_domain; 268 268 - int hwbase = bank->gc.offset; 266 266 + int hwbase = bank->chip.gc.offset; 269 267 unsigned long status; 270 268 271 269 while ((status = brcmstb_gpio_get_active_irqs(bank))) { ··· 305 303 306 304 /* banks are in descending order */ 307 305 list_for_each_entry_reverse(bank, &priv->bank_list, node) { 308 308 - i += bank->gc.ngpio; 306 306 + i += bank->chip.gc.ngpio; 309 307 if (hwirq < i) 310 308 return bank; 311 309 } ··· 334 332 335 333 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", 336 334 irq, (int)hwirq, bank->id); 337 337 - ret = irq_set_chip_data(irq, &bank->gc); 335 335 + ret = irq_set_chip_data(irq, &bank->chip.gc); 338 336 if (ret < 0) 339 337 return ret; 340 338 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class, ··· 396 394 * more important to actually perform all of the steps. 397 395 */ 398 396 list_for_each_entry(bank, &priv->bank_list, node) 399 399 - gpiochip_remove(&bank->gc); 397 397 + gpiochip_remove(&bank->chip.gc); 400 398 } 401 399 402 400 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, ··· 414 412 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) 415 413 return -EINVAL; 416 414 417 417 - offset = gpiospec->args[0] - bank->gc.offset; 415 415 + offset = gpiospec->args[0] - bank->chip.gc.offset; 418 416 if (offset >= gc->ngpio || offset < 0) 419 417 return -EINVAL; 420 418 ··· 495 493 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv, 496 494 struct brcmstb_gpio_bank *bank) 497 495 { 498 498 - struct gpio_chip *gc = &bank->gc; 499 496 unsigned int i; 500 497 501 498 for (i = 0; i < GIO_REG_STAT; i++) 502 502 - bank->saved_regs[i] = gc->read_reg(priv->reg_base + 503 503 - GIO_BANK_OFF(bank->id, i)); 499 499 + bank->saved_regs[i] = gpio_generic_read_reg(&bank->chip, 500 500 + priv->reg_base + GIO_BANK_OFF(bank->id, i)); 504 501 } 505 502 506 503 static void brcmstb_gpio_quiesce(struct device *dev, bool save) 507 504 { 508 505 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev); 509 506 struct brcmstb_gpio_bank *bank; 510 510 - struct gpio_chip *gc; 511 507 u32 imask; 512 508 513 509 /* disable non-wake interrupt */ ··· 513 513 disable_irq(priv->parent_irq); 514 514 515 515 list_for_each_entry(bank, &priv->bank_list, node) { 516 516 - gc = &bank->gc; 517 517 - 518 516 if (save) 519 517 brcmstb_gpio_bank_save(priv, bank); 520 518 ··· 521 523 imask = bank->wake_active; 522 524 else 523 525 imask = 0; 524 524 - gc->write_reg(priv->reg_base + GIO_MASK(bank->id), 525 525 - imask); 526 526 + gpio_generic_write_reg(&bank->chip, 527 527 + priv->reg_base + GIO_MASK(bank->id), 528 528 + imask); 526 529 } 527 530 } 528 531 ··· 537 538 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv, 538 539 struct brcmstb_gpio_bank *bank) 539 540 { 540 540 - struct gpio_chip *gc = &bank->gc; 541 541 unsigned int i; 542 542 543 543 for (i = 0; i < GIO_REG_STAT; i++) 544 544 - gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), 545 545 - bank->saved_regs[i]); 544 544 + gpio_generic_write_reg(&bank->chip, 545 545 + priv->reg_base + GIO_BANK_OFF(bank->id, i), 546 546 + bank->saved_regs[i]); 546 547 } 547 548 548 549 static int brcmstb_gpio_suspend(struct device *dev) ··· 584 585 585 586 static int brcmstb_gpio_probe(struct platform_device *pdev) 586 587 { 588 588 + struct gpio_generic_chip_config config; 587 589 struct device *dev = &pdev->dev; 588 590 struct device_node *np = dev->of_node; 589 591 void __iomem *reg_base; ··· 630 630 * else leave I/O in little endian mode. 631 631 */ 632 632 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) 633 633 - flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; 633 633 + flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 634 634 #endif 635 635 636 636 of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) { ··· 665 665 bank->width = bank_width; 666 666 } 667 667 668 668 + gc = &bank->chip.gc; 669 669 + 668 670 /* 669 671 * Regs are 4 bytes wide, have data reg, no set/clear regs, 670 672 * and direction bits have 0 = output and 1 = input 671 673 */ 672 672 - gc = &bank->gc; 673 673 - err = bgpio_init(gc, dev, 4, 674 674 - reg_base + GIO_DATA(bank->id), 675 675 - NULL, NULL, NULL, 676 676 - reg_base + GIO_IODIR(bank->id), flags); 674 674 + 675 675 + config = (struct gpio_generic_chip_config) { 676 676 + .dev = dev, 677 677 + .sz = 4, 678 678 + .dat = reg_base + GIO_DATA(bank->id), 679 679 + .dirin = reg_base + GIO_IODIR(bank->id), 680 680 + .flags = flags, 681 681 + }; 682 682 + 683 683 + err = gpio_generic_chip_init(&bank->chip, &config); 677 684 if (err) { 678 678 - dev_err(dev, "bgpio_init() failed\n"); 685 685 + dev_err(dev, "failed to initialize generic GPIO chip\n"); 679 686 goto fail; 680 687 } 681 688 ··· 707 700 * be retained from S5 cold boot 708 701 */ 709 702 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); 710 710 - gc->write_reg(reg_base + GIO_MASK(bank->id), 0); 703 703 + gpio_generic_write_reg(&bank->chip, 704 704 + reg_base + GIO_MASK(bank->id), 0); 711 705 712 706 err = gpiochip_add_data(gc, bank); 713 707 if (err) {

+1 -1

drivers/gpio/gpio-cadence.c

reviewed

··· 181 181 config.dat = cgpio->regs + CDNS_GPIO_INPUT_VALUE; 182 182 config.set = cgpio->regs + CDNS_GPIO_OUTPUT_VALUE; 183 183 config.dirin = cgpio->regs + CDNS_GPIO_DIRECTION_MODE; 184 184 - config.flags = BGPIOF_READ_OUTPUT_REG_SET; 184 184 + config.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET; 185 185 186 186 ret = gpio_generic_chip_init(&cgpio->gen_gc, &config); 187 187 if (ret) {

+86 -74

drivers/gpio/gpio-dwapb.c

reviewed

··· 8 8 #include <linux/clk.h> 9 9 #include <linux/err.h> 10 10 #include <linux/gpio/driver.h> 11 11 + #include <linux/gpio/generic.h> 11 12 #include <linux/init.h> 12 13 #include <linux/interrupt.h> 13 14 #include <linux/io.h> ··· 100 99 }; 101 100 102 101 struct dwapb_gpio_port { 103 103 - struct gpio_chip gc; 102 102 + struct gpio_generic_chip chip; 104 103 struct dwapb_gpio_port_irqchip *pirq; 105 104 struct dwapb_gpio *gpio; 106 105 #ifdef CONFIG_PM_SLEEP ··· 108 107 #endif 109 108 unsigned int idx; 110 109 }; 111 111 - #define to_dwapb_gpio(_gc) \ 112 112 - (container_of(_gc, struct dwapb_gpio_port, gc)->gpio) 110 110 + 111 111 + static inline struct dwapb_gpio *to_dwapb_gpio(struct gpio_chip *gc) 112 112 + { 113 113 + return container_of(to_gpio_generic_chip(gc), 114 114 + struct dwapb_gpio_port, chip)->gpio; 115 115 + } 113 116 114 117 struct dwapb_gpio { 115 118 struct device *dev; ··· 153 148 154 149 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) 155 150 { 156 156 - struct gpio_chip *gc = &gpio->ports[0].gc; 157 157 - void __iomem *reg_base = gpio->regs; 151 151 + struct gpio_generic_chip *chip = &gpio->ports[0].chip; 152 152 + void __iomem *reg_base = gpio->regs; 158 153 159 159 - return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); 154 154 + return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offset)); 160 155 } 161 156 162 157 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, 163 158 u32 val) 164 159 { 165 165 - struct gpio_chip *gc = &gpio->ports[0].gc; 166 166 - void __iomem *reg_base = gpio->regs; 160 160 + struct gpio_generic_chip *chip = &gpio->ports[0].chip; 161 161 + void __iomem *reg_base = gpio->regs; 167 162 168 168 - gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); 163 163 + gpio_generic_write_reg(chip, reg_base + gpio_reg_convert(gpio, offset), val); 169 164 } 170 165 171 166 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) ··· 191 186 192 187 if (!port) 193 188 return; 194 194 - gc = &port->gc; 189 189 + gc = &port->chip.gc; 195 190 196 191 pol = dwapb_read(gpio, GPIO_INT_POLARITY); 197 192 /* Just read the current value right out of the data register */ ··· 206 201 207 202 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) 208 203 { 209 209 - struct gpio_chip *gc = &gpio->ports[0].gc; 204 204 + struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip; 210 205 unsigned long irq_status; 211 206 irq_hw_number_t hwirq; 212 207 213 208 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); 214 209 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) { 215 215 - int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq); 210 210 + int gpio_irq = irq_find_mapping(gen_gc->gc.irq.domain, hwirq); 216 211 u32 irq_type = irq_get_trigger_type(gpio_irq); 217 212 218 213 generic_handle_irq(gpio_irq); ··· 242 237 static void dwapb_irq_ack(struct irq_data *d) 243 238 { 244 239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 240 240 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 245 241 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 246 242 u32 val = BIT(irqd_to_hwirq(d)); 247 247 - unsigned long flags; 248 243 249 249 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 244 244 + guard(gpio_generic_lock_irqsave)(gen_gc); 245 245 + 250 246 dwapb_write(gpio, GPIO_PORTA_EOI, val); 251 251 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 252 247 } 253 248 254 249 static void dwapb_irq_mask(struct irq_data *d) 255 250 { 256 251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 252 252 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 257 253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 258 254 irq_hw_number_t hwirq = irqd_to_hwirq(d); 259 259 - unsigned long flags; 260 255 u32 val; 261 256 262 262 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 263 263 - val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); 264 264 - dwapb_write(gpio, GPIO_INTMASK, val); 265 265 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 257 257 + scoped_guard(gpio_generic_lock_irqsave, gen_gc) { 258 258 + val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); 259 259 + dwapb_write(gpio, GPIO_INTMASK, val); 260 260 + } 266 261 267 262 gpiochip_disable_irq(gc, hwirq); 268 263 } ··· 270 265 static void dwapb_irq_unmask(struct irq_data *d) 271 266 { 272 267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 268 268 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 273 269 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 274 270 irq_hw_number_t hwirq = irqd_to_hwirq(d); 275 275 - unsigned long flags; 276 271 u32 val; 277 272 278 273 gpiochip_enable_irq(gc, hwirq); 279 274 280 280 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 275 275 + guard(gpio_generic_lock_irqsave)(gen_gc); 276 276 + 281 277 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); 282 278 dwapb_write(gpio, GPIO_INTMASK, val); 283 283 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 284 279 } 285 280 286 281 static void dwapb_irq_enable(struct irq_data *d) 287 282 { 288 283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 284 284 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 289 285 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 290 286 irq_hw_number_t hwirq = irqd_to_hwirq(d); 291 291 - unsigned long flags; 292 287 u32 val; 293 288 294 294 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 289 289 + guard(gpio_generic_lock_irqsave)(gen_gc); 290 290 + 295 291 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq); 296 292 dwapb_write(gpio, GPIO_INTEN, val); 297 293 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); 298 294 dwapb_write(gpio, GPIO_INTMASK, val); 299 299 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 300 295 } 301 296 302 297 static void dwapb_irq_disable(struct irq_data *d) 303 298 { 304 299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 300 300 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 305 301 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 306 302 irq_hw_number_t hwirq = irqd_to_hwirq(d); 307 307 - unsigned long flags; 308 303 u32 val; 309 304 310 310 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 305 305 + guard(gpio_generic_lock_irqsave)(gen_gc); 306 306 + 311 307 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); 312 308 dwapb_write(gpio, GPIO_INTMASK, val); 313 309 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq); 314 310 dwapb_write(gpio, GPIO_INTEN, val); 315 315 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 316 311 } 317 312 318 313 static int dwapb_irq_set_type(struct irq_data *d, u32 type) 319 314 { 320 315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 316 316 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 321 317 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 322 318 irq_hw_number_t bit = irqd_to_hwirq(d); 323 323 - unsigned long level, polarity, flags; 319 319 + unsigned long level, polarity; 324 320 325 325 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 321 321 + guard(gpio_generic_lock_irqsave)(gen_gc); 322 322 + 326 323 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 327 324 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); 328 325 ··· 359 352 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); 360 353 if (type != IRQ_TYPE_EDGE_BOTH) 361 354 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); 362 362 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 363 355 364 356 return 0; 365 357 } ··· 399 393 unsigned offset, unsigned debounce) 400 394 { 401 395 struct dwapb_gpio_port *port = gpiochip_get_data(gc); 396 396 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 402 397 struct dwapb_gpio *gpio = port->gpio; 403 403 - unsigned long flags, val_deb; 398 398 + unsigned long val_deb; 404 399 unsigned long mask = BIT(offset); 405 400 406 406 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 401 401 + guard(gpio_generic_lock_irqsave)(gen_gc); 407 402 408 403 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 409 404 if (debounce) ··· 412 405 else 413 406 val_deb &= ~mask; 414 407 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); 415 415 - 416 416 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 417 408 418 409 return 0; 419 410 } ··· 450 445 struct dwapb_port_property *pp) 451 446 { 452 447 struct dwapb_gpio_port_irqchip *pirq; 453 453 - struct gpio_chip *gc = &port->gc; 448 448 + struct gpio_chip *gc = &port->chip.gc; 454 449 struct gpio_irq_chip *girq; 455 450 int err; 456 451 ··· 506 501 struct dwapb_port_property *pp, 507 502 unsigned int offs) 508 503 { 504 504 + struct gpio_generic_chip_config config; 509 505 struct dwapb_gpio_port *port; 510 506 void __iomem *dat, *set, *dirout; 511 507 int err; ··· 525 519 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; 526 520 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; 527 521 522 522 + config = (struct gpio_generic_chip_config) { 523 523 + .dev = gpio->dev, 524 524 + .sz = 4, 525 525 + .dat = dat, 526 526 + .set = set, 527 527 + .dirout = dirout, 528 528 + }; 529 529 + 528 530 /* This registers 32 GPIO lines per port */ 529 529 - err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, 530 530 - NULL, 0); 531 531 + err = gpio_generic_chip_init(&port->chip, &config); 531 532 if (err) { 532 533 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", 533 534 port->idx); 534 535 return err; 535 536 } 536 537 537 537 - port->gc.fwnode = pp->fwnode; 538 538 - port->gc.ngpio = pp->ngpio; 539 539 - port->gc.base = pp->gpio_base; 540 540 - port->gc.request = gpiochip_generic_request; 541 541 - port->gc.free = gpiochip_generic_free; 538 538 + port->chip.gc.fwnode = pp->fwnode; 539 539 + port->chip.gc.ngpio = pp->ngpio; 540 540 + port->chip.gc.base = pp->gpio_base; 541 541 + port->chip.gc.request = gpiochip_generic_request; 542 542 + port->chip.gc.free = gpiochip_generic_free; 542 543 543 544 /* Only port A support debounce */ 544 545 if (pp->idx == 0) 545 545 - port->gc.set_config = dwapb_gpio_set_config; 546 546 + port->chip.gc.set_config = dwapb_gpio_set_config; 546 547 else 547 547 - port->gc.set_config = gpiochip_generic_config; 548 548 + port->chip.gc.set_config = gpiochip_generic_config; 548 549 549 550 /* Only port A can provide interrupts in all configurations of the IP */ 550 551 if (pp->idx == 0) 551 552 dwapb_configure_irqs(gpio, port, pp); 552 553 553 553 - err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); 554 554 + err = devm_gpiochip_add_data(gpio->dev, &port->chip.gc, port); 554 555 if (err) { 555 556 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", 556 557 port->idx); ··· 763 750 static int dwapb_gpio_suspend(struct device *dev) 764 751 { 765 752 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 766 766 - struct gpio_chip *gc = &gpio->ports[0].gc; 767 767 - unsigned long flags; 753 753 + struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip; 768 754 int i; 769 755 770 770 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 771 771 - for (i = 0; i < gpio->nr_ports; i++) { 772 772 - unsigned int offset; 773 773 - unsigned int idx = gpio->ports[i].idx; 774 774 - struct dwapb_context *ctx = gpio->ports[i].ctx; 756 756 + scoped_guard(gpio_generic_lock_irqsave, gen_gc) { 757 757 + for (i = 0; i < gpio->nr_ports; i++) { 758 758 + unsigned int offset; 759 759 + unsigned int idx = gpio->ports[i].idx; 760 760 + struct dwapb_context *ctx = gpio->ports[i].ctx; 775 761 776 776 - offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 777 777 - ctx->dir = dwapb_read(gpio, offset); 762 762 + offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 763 763 + ctx->dir = dwapb_read(gpio, offset); 778 764 779 779 - offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 780 780 - ctx->data = dwapb_read(gpio, offset); 765 765 + offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 766 766 + ctx->data = dwapb_read(gpio, offset); 781 767 782 782 - offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 783 783 - ctx->ext = dwapb_read(gpio, offset); 768 768 + offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 769 769 + ctx->ext = dwapb_read(gpio, offset); 784 770 785 785 - /* Only port A can provide interrupts */ 786 786 - if (idx == 0) { 787 787 - ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); 788 788 - ctx->int_en = dwapb_read(gpio, GPIO_INTEN); 789 789 - ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); 790 790 - ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 791 791 - ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 771 771 + /* Only port A can provide interrupts */ 772 772 + if (idx == 0) { 773 773 + ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); 774 774 + ctx->int_en = dwapb_read(gpio, GPIO_INTEN); 775 775 + ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); 776 776 + ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 777 777 + ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 792 778 793 793 - /* Mask out interrupts */ 794 794 - dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); 779 779 + /* Mask out interrupts */ 780 780 + dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); 781 781 + } 795 782 } 796 783 } 797 797 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 798 784 799 785 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 800 786 ··· 803 791 static int dwapb_gpio_resume(struct device *dev) 804 792 { 805 793 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 806 806 - struct gpio_chip *gc = &gpio->ports[0].gc; 807 807 - unsigned long flags; 794 794 + struct gpio_chip *gc = &gpio->ports[0].chip.gc; 795 795 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 808 796 int i, err; 809 797 810 798 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); ··· 813 801 return err; 814 802 } 815 803 816 816 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 804 804 + guard(gpio_generic_lock_irqsave)(gen_gc); 805 805 + 817 806 for (i = 0; i < gpio->nr_ports; i++) { 818 807 unsigned int offset; 819 808 unsigned int idx = gpio->ports[i].idx; ··· 841 828 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); 842 829 } 843 830 } 844 844 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 845 831 846 832 return 0; 847 833 }

+23 -10

drivers/gpio/gpio-ep93xx.c

reviewed

··· 9 9 * linux/arch/arm/mach-ep93xx/core.c 10 10 */ 11 11 12 12 + #include <linux/bitops.h> 13 13 + #include <linux/gpio/driver.h> 14 14 + #include <linux/gpio/generic.h> 12 15 #include <linux/init.h> 13 13 - #include <linux/module.h> 14 14 - #include <linux/platform_device.h> 15 16 #include <linux/interrupt.h> 16 17 #include <linux/io.h> 17 18 #include <linux/irq.h> 18 18 - #include <linux/slab.h> 19 19 - #include <linux/gpio/driver.h> 20 20 - #include <linux/bitops.h> 19 19 + #include <linux/module.h> 20 20 + #include <linux/platform_device.h> 21 21 #include <linux/seq_file.h> 22 22 + #include <linux/slab.h> 22 23 23 24 struct ep93xx_gpio_irq_chip { 24 25 void __iomem *base; ··· 32 31 33 32 struct ep93xx_gpio_chip { 34 33 void __iomem *base; 35 35 - struct gpio_chip gc; 34 34 + struct gpio_generic_chip chip; 36 35 struct ep93xx_gpio_irq_chip *eic; 37 36 }; 38 37 39 39 - #define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) 38 38 + static struct ep93xx_gpio_chip *to_ep93xx_gpio_chip(struct gpio_chip *gc) 39 39 + { 40 40 + return container_of(to_gpio_generic_chip(gc), struct ep93xx_gpio_chip, chip); 41 41 + } 40 42 41 43 static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc) 42 44 { ··· 271 267 static int ep93xx_setup_irqs(struct platform_device *pdev, 272 268 struct ep93xx_gpio_chip *egc) 273 269 { 274 274 - struct gpio_chip *gc = &egc->gc; 270 270 + struct gpio_chip *gc = &egc->chip.gc; 275 271 struct device *dev = &pdev->dev; 276 272 struct gpio_irq_chip *girq = &gc->irq; 277 273 int ret, irq, i; ··· 331 327 332 328 static int ep93xx_gpio_probe(struct platform_device *pdev) 333 329 { 330 330 + struct gpio_generic_chip_config config; 334 331 struct ep93xx_gpio_chip *egc; 335 332 struct gpio_chip *gc; 336 333 void __iomem *data; ··· 350 345 if (IS_ERR(dir)) 351 346 return PTR_ERR(dir); 352 347 353 353 - gc = &egc->gc; 354 354 - ret = bgpio_init(gc, &pdev->dev, 1, data, NULL, NULL, dir, NULL, 0); 348 348 + gc = &egc->chip.gc; 349 349 + 350 350 + config = (struct gpio_generic_chip_config) { 351 351 + .dev = &pdev->dev, 352 352 + .sz = 1, 353 353 + .dat = data, 354 354 + .dirout = dir, 355 355 + }; 356 356 + 357 357 + ret = gpio_generic_chip_init(&egc->chip, &config); 355 358 if (ret) 356 359 return dev_err_probe(&pdev->dev, ret, "unable to init generic GPIO\n"); 357 360

+27 -21

drivers/gpio/gpio-ftgpio010.c

reviewed

··· 10 10 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 11 11 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 12 12 */ 13 13 - #include <linux/gpio/driver.h> 14 14 - #include <linux/io.h> 15 15 - #include <linux/interrupt.h> 16 16 - #include <linux/platform_device.h> 13 13 + 17 14 #include <linux/bitops.h> 18 15 #include <linux/clk.h> 16 16 + #include <linux/gpio/driver.h> 17 17 + #include <linux/gpio/generic.h> 18 18 + #include <linux/interrupt.h> 19 19 + #include <linux/io.h> 20 20 + #include <linux/platform_device.h> 19 21 20 22 /* GPIO registers definition */ 21 23 #define GPIO_DATA_OUT 0x00 ··· 42 40 /** 43 41 * struct ftgpio_gpio - Gemini GPIO state container 44 42 * @dev: containing device for this instance 45 45 - * @gc: gpiochip for this instance 43 43 + * @chip: generic GPIO chip for this instance 46 44 * @base: remapped I/O-memory base 47 45 * @clk: silicon clock 48 46 */ 49 47 struct ftgpio_gpio { 50 48 struct device *dev; 51 51 - struct gpio_chip gc; 49 49 + struct gpio_generic_chip chip; 52 50 void __iomem *base; 53 51 struct clk *clk; 54 52 }; ··· 235 233 236 234 static int ftgpio_gpio_probe(struct platform_device *pdev) 237 235 { 236 236 + struct gpio_generic_chip_config config; 238 237 struct device *dev = &pdev->dev; 239 238 struct ftgpio_gpio *g; 240 239 struct gpio_irq_chip *girq; ··· 264 261 */ 265 262 return PTR_ERR(g->clk); 266 263 267 267 - ret = bgpio_init(&g->gc, dev, 4, 268 268 - g->base + GPIO_DATA_IN, 269 269 - g->base + GPIO_DATA_SET, 270 270 - g->base + GPIO_DATA_CLR, 271 271 - g->base + GPIO_DIR, 272 272 - NULL, 273 273 - 0); 264 264 + config = (struct gpio_generic_chip_config) { 265 265 + .dev = dev, 266 266 + .sz = 4, 267 267 + .dat = g->base + GPIO_DATA_IN, 268 268 + .set = g->base + GPIO_DATA_SET, 269 269 + .clr = g->base + GPIO_DATA_CLR, 270 270 + .dirout = g->base + GPIO_DIR, 271 271 + }; 272 272 + 273 273 + ret = gpio_generic_chip_init(&g->chip, &config); 274 274 if (ret) 275 275 return dev_err_probe(dev, ret, "unable to init generic GPIO\n"); 276 276 277 277 - g->gc.label = dev_name(dev); 278 278 - g->gc.base = -1; 279 279 - g->gc.parent = dev; 280 280 - g->gc.owner = THIS_MODULE; 281 281 - /* ngpio is set by bgpio_init() */ 277 277 + g->chip.gc.label = dev_name(dev); 278 278 + g->chip.gc.base = -1; 279 279 + g->chip.gc.parent = dev; 280 280 + g->chip.gc.owner = THIS_MODULE; 281 281 + /* ngpio is set by gpio_generic_chip_init() */ 282 282 283 283 /* We need a silicon clock to do debounce */ 284 284 if (!IS_ERR(g->clk)) 285 285 - g->gc.set_config = ftgpio_gpio_set_config; 285 285 + g->chip.gc.set_config = ftgpio_gpio_set_config; 286 286 287 287 - girq = &g->gc.irq; 287 287 + girq = &g->chip.gc.irq; 288 288 gpio_irq_chip_set_chip(girq, &ftgpio_irq_chip); 289 289 girq->parent_handler = ftgpio_gpio_irq_handler; 290 290 girq->num_parents = 1; ··· 308 302 /* Clear any use of debounce */ 309 303 writel(0x0, g->base + GPIO_DEBOUNCE_EN); 310 304 311 311 - return devm_gpiochip_add_data(dev, &g->gc, g); 305 305 + return devm_gpiochip_add_data(dev, &g->chip.gc, g); 312 306 } 313 307 314 308 static const struct of_device_id ftgpio_gpio_of_match[] = {

+19 -6

drivers/gpio/gpio-ge.c

reviewed

··· 16 16 */ 17 17 18 18 #include <linux/gpio/driver.h> 19 19 + #include <linux/gpio/generic.h> 19 20 #include <linux/io.h> 20 21 #include <linux/kernel.h> 21 22 #include <linux/mod_devicetable.h> ··· 52 51 53 52 static int __init gef_gpio_probe(struct platform_device *pdev) 54 53 { 54 54 + struct gpio_generic_chip_config config; 55 55 struct device *dev = &pdev->dev; 56 56 + struct gpio_generic_chip *chip; 56 57 struct gpio_chip *gc; 57 58 void __iomem *regs; 58 59 int ret; 59 60 60 60 - gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 61 61 - if (!gc) 61 61 + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 62 62 + if (!chip) 62 63 return -ENOMEM; 63 64 64 65 regs = devm_platform_ioremap_resource(pdev, 0); 65 66 if (IS_ERR(regs)) 66 67 return PTR_ERR(regs); 67 68 68 68 - ret = bgpio_init(gc, dev, 4, regs + GEF_GPIO_IN, regs + GEF_GPIO_OUT, 69 69 - NULL, NULL, regs + GEF_GPIO_DIRECT, 70 70 - BGPIOF_BIG_ENDIAN_BYTE_ORDER); 69 69 + config = (struct gpio_generic_chip_config) { 70 70 + .dev = dev, 71 71 + .sz = 4, 72 72 + .dat = regs + GEF_GPIO_IN, 73 73 + .set = regs + GEF_GPIO_OUT, 74 74 + .dirin = regs + GEF_GPIO_DIRECT, 75 75 + .flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER, 76 76 + }; 77 77 + 78 78 + ret = gpio_generic_chip_init(chip, &config); 71 79 if (ret) 72 72 - return dev_err_probe(dev, ret, "bgpio_init failed\n"); 80 80 + return dev_err_probe(dev, ret, 81 81 + "failed to initialize the generic GPIO chip\n"); 82 82 + 83 83 + gc = &chip->gc; 73 84 74 85 /* Setup pointers to chip functions */ 75 86 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev));

+44 -43

drivers/gpio/gpio-grgpio.c

reviewed

··· 19 19 #include <linux/bitops.h> 20 20 #include <linux/err.h> 21 21 #include <linux/gpio/driver.h> 22 22 + #include <linux/gpio/generic.h> 22 23 #include <linux/init.h> 23 24 #include <linux/interrupt.h> 24 25 #include <linux/io.h> ··· 60 59 }; 61 60 62 61 struct grgpio_priv { 63 63 - struct gpio_chip gc; 62 62 + struct gpio_generic_chip chip; 64 63 void __iomem *regs; 65 64 struct device *dev; 66 65 ··· 92 91 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset, 93 92 int val) 94 93 { 95 95 - struct gpio_chip *gc = &priv->gc; 96 96 - 97 94 if (val) 98 95 priv->imask |= BIT(offset); 99 96 else 100 97 priv->imask &= ~BIT(offset); 101 101 - gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); 98 98 + 99 99 + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IMASK, priv->imask); 102 100 } 103 101 104 102 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset) ··· 118 118 static int grgpio_irq_set_type(struct irq_data *d, unsigned int type) 119 119 { 120 120 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d); 121 121 - unsigned long flags; 122 121 u32 mask = BIT(d->hwirq); 123 122 u32 ipol; 124 123 u32 iedge; ··· 145 146 return -EINVAL; 146 147 } 147 148 148 148 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 149 149 + guard(gpio_generic_lock_irqsave)(&priv->chip); 149 150 150 150 - ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask; 151 151 - iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask; 151 151 + ipol = gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IPOL) & ~mask; 152 152 + iedge = gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IEDGE) & ~mask; 152 153 153 153 - priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol); 154 154 - priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge); 155 155 - 156 156 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 154 154 + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IPOL, ipol | pol); 155 155 + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IEDGE, iedge | edge); 157 156 158 157 return 0; 159 158 } ··· 160 163 { 161 164 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d); 162 165 int offset = d->hwirq; 163 163 - unsigned long flags; 164 166 165 165 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 167 167 + scoped_guard(gpio_generic_lock_irqsave, &priv->chip) 168 168 + grgpio_set_imask(priv, offset, 0); 166 169 167 167 - grgpio_set_imask(priv, offset, 0); 168 168 - 169 169 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 170 170 - 171 171 - gpiochip_disable_irq(&priv->gc, d->hwirq); 170 170 + gpiochip_disable_irq(&priv->chip.gc, d->hwirq); 172 171 } 173 172 174 173 static void grgpio_irq_unmask(struct irq_data *d) 175 174 { 176 175 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d); 177 176 int offset = d->hwirq; 178 178 - unsigned long flags; 179 177 180 180 - gpiochip_enable_irq(&priv->gc, d->hwirq); 181 181 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 178 178 + gpiochip_enable_irq(&priv->chip.gc, d->hwirq); 179 179 + 180 180 + guard(gpio_generic_lock_irqsave)(&priv->chip); 182 181 183 182 grgpio_set_imask(priv, offset, 1); 184 184 - 185 185 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 186 183 } 187 184 188 185 static const struct irq_chip grgpio_irq_chip = { ··· 191 200 static irqreturn_t grgpio_irq_handler(int irq, void *dev) 192 201 { 193 202 struct grgpio_priv *priv = dev; 194 194 - int ngpio = priv->gc.ngpio; 195 195 - unsigned long flags; 203 203 + int ngpio = priv->chip.gc.ngpio; 196 204 int i; 197 205 int match = 0; 198 206 199 199 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 207 207 + guard(gpio_generic_lock_irqsave)(&priv->chip); 200 208 201 209 /* 202 210 * For each gpio line, call its interrupt handler if it its underlying ··· 210 220 match = 1; 211 221 } 212 222 } 213 213 - 214 214 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 215 223 216 224 if (!match) 217 225 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq); ··· 241 253 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n", 242 254 irq, offset); 243 255 244 244 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 256 256 + gpio_generic_chip_lock_irqsave(&priv->chip, flags); 245 257 246 258 /* Request underlying irq if not already requested */ 247 259 lirq->irq = irq; 248 260 uirq = &priv->uirqs[lirq->index]; 249 261 if (uirq->refcnt == 0) { 250 250 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 262 262 + /* 263 263 + * FIXME: This is not how locking works at all, you can't just 264 264 + * release the lock for a moment to do something that can't 265 265 + * sleep... 266 266 + */ 267 267 + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); 251 268 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0, 252 269 dev_name(priv->dev), priv); 253 270 if (ret) { ··· 261 268 uirq->uirq); 262 269 return ret; 263 270 } 264 264 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 271 271 + gpio_generic_chip_lock_irqsave(&priv->chip, flags); 265 272 } 266 273 uirq->refcnt++; 267 274 268 268 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 275 275 + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); 269 276 270 277 /* Setup irq */ 271 278 irq_set_chip_data(irq, priv); ··· 283 290 struct grgpio_lirq *lirq; 284 291 struct grgpio_uirq *uirq; 285 292 unsigned long flags; 286 286 - int ngpio = priv->gc.ngpio; 293 293 + int ngpio = priv->chip.gc.ngpio; 287 294 int i; 288 295 289 296 irq_set_chip_and_handler(irq, NULL, NULL); 290 297 irq_set_chip_data(irq, NULL); 291 298 292 292 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 299 299 + gpio_generic_chip_lock_irqsave(&priv->chip, flags); 293 300 294 301 /* Free underlying irq if last user unmapped */ 295 302 index = -1; ··· 308 315 uirq = &priv->uirqs[lirq->index]; 309 316 uirq->refcnt--; 310 317 if (uirq->refcnt == 0) { 311 311 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 318 318 + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); 312 319 free_irq(uirq->uirq, priv); 313 320 return; 314 321 } 315 322 } 316 323 317 317 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 324 324 + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); 318 325 } 319 326 320 327 static void grgpio_irq_domain_remove(void *data) ··· 334 341 static int grgpio_probe(struct platform_device *ofdev) 335 342 { 336 343 struct device_node *np = ofdev->dev.of_node; 344 344 + struct gpio_generic_chip_config config; 337 345 struct device *dev = &ofdev->dev; 338 346 void __iomem *regs; 339 347 struct gpio_chip *gc; ··· 353 359 if (IS_ERR(regs)) 354 360 return PTR_ERR(regs); 355 361 356 356 - gc = &priv->gc; 357 357 - err = bgpio_init(gc, dev, 4, regs + GRGPIO_DATA, 358 358 - regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL, 359 359 - BGPIOF_BIG_ENDIAN_BYTE_ORDER); 362 362 + config = (struct gpio_generic_chip_config) { 363 363 + .dev = dev, 364 364 + .sz = 4, 365 365 + .dat = regs + GRGPIO_DATA, 366 366 + .set = regs + GRGPIO_OUTPUT, 367 367 + .dirout = regs + GRGPIO_DIR, 368 368 + .flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER, 369 369 + }; 370 370 + 371 371 + gc = &priv->chip.gc; 372 372 + err = gpio_generic_chip_init(&priv->chip, &config); 360 373 if (err) { 361 361 - dev_err(dev, "bgpio_init() failed\n"); 374 374 + dev_err(dev, "failed to initialize the generic GPIO chip\n"); 362 375 return err; 363 376 } 364 377 365 378 priv->regs = regs; 366 366 - priv->imask = gc->read_reg(regs + GRGPIO_IMASK); 379 379 + priv->imask = gpio_generic_read_reg(&priv->chip, regs + GRGPIO_IMASK); 367 380 priv->dev = dev; 368 381 369 382 gc->owner = THIS_MODULE;

+28 -20

drivers/gpio/gpio-hisi.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* Copyright (c) 2020 HiSilicon Limited. */ 3 3 + 3 4 #include <linux/gpio/driver.h> 5 5 + #include <linux/gpio/generic.h> 4 6 #include <linux/module.h> 5 7 #include <linux/mod_devicetable.h> 6 8 #include <linux/platform_device.h> ··· 35 33 #define HISI_GPIO_DRIVER_NAME "gpio-hisi" 36 34 37 35 struct hisi_gpio { 38 38 - struct gpio_chip chip; 36 36 + struct gpio_generic_chip chip; 39 37 struct device *dev; 40 38 void __iomem *reg_base; 41 39 unsigned int line_num; ··· 45 43 static inline u32 hisi_gpio_read_reg(struct gpio_chip *chip, 46 44 unsigned int off) 47 45 { 48 48 - struct hisi_gpio *hisi_gpio = 49 49 - container_of(chip, struct hisi_gpio, chip); 46 46 + struct hisi_gpio *hisi_gpio = container_of(to_gpio_generic_chip(chip), 47 47 + struct hisi_gpio, chip); 50 48 void __iomem *reg = hisi_gpio->reg_base + off; 51 49 52 50 return readl(reg); ··· 55 53 static inline void hisi_gpio_write_reg(struct gpio_chip *chip, 56 54 unsigned int off, u32 val) 57 55 { 58 58 - struct hisi_gpio *hisi_gpio = 59 59 - container_of(chip, struct hisi_gpio, chip); 56 56 + struct hisi_gpio *hisi_gpio = container_of(to_gpio_generic_chip(chip), 57 57 + struct hisi_gpio, chip); 60 58 void __iomem *reg = hisi_gpio->reg_base + off; 61 59 62 60 writel(val, reg); ··· 182 180 static void hisi_gpio_irq_handler(struct irq_desc *desc) 183 181 { 184 182 struct hisi_gpio *hisi_gpio = irq_desc_get_handler_data(desc); 185 185 - unsigned long irq_msk = hisi_gpio_read_reg(&hisi_gpio->chip, 183 183 + unsigned long irq_msk = hisi_gpio_read_reg(&hisi_gpio->chip.gc, 186 184 HISI_GPIO_INTSTATUS_WX); 187 185 struct irq_chip *irq_c = irq_desc_get_chip(desc); 188 186 int hwirq; 189 187 190 188 chained_irq_enter(irq_c, desc); 191 189 for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX) 192 192 - generic_handle_domain_irq(hisi_gpio->chip.irq.domain, 190 190 + generic_handle_domain_irq(hisi_gpio->chip.gc.irq.domain, 193 191 hwirq); 194 192 chained_irq_exit(irq_c, desc); 195 193 } ··· 208 206 209 207 static void hisi_gpio_init_irq(struct hisi_gpio *hisi_gpio) 210 208 { 211 211 - struct gpio_chip *chip = &hisi_gpio->chip; 209 209 + struct gpio_chip *chip = &hisi_gpio->chip.gc; 212 210 struct gpio_irq_chip *girq_chip = &chip->irq; 213 211 214 212 gpio_irq_chip_set_chip(girq_chip, &hisi_gpio_irq_chip); ··· 266 264 267 265 static int hisi_gpio_probe(struct platform_device *pdev) 268 266 { 267 267 + struct gpio_generic_chip_config config; 269 268 struct device *dev = &pdev->dev; 270 269 struct hisi_gpio *hisi_gpio; 271 270 int port_num; ··· 292 289 293 290 hisi_gpio->dev = dev; 294 291 295 295 - ret = bgpio_init(&hisi_gpio->chip, hisi_gpio->dev, 0x4, 296 296 - hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX, 297 297 - hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX, 298 298 - hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX, 299 299 - hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX, 300 300 - hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX, 301 301 - BGPIOF_NO_SET_ON_INPUT); 292 292 + config = (struct gpio_generic_chip_config) { 293 293 + .dev = hisi_gpio->dev, 294 294 + .sz = 4, 295 295 + .dat = hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX, 296 296 + .set = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX, 297 297 + .clr = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX, 298 298 + .dirout = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX, 299 299 + .dirin = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX, 300 300 + .flags = GPIO_GENERIC_NO_SET_ON_INPUT | 301 301 + GPIO_GENERIC_UNREADABLE_REG_DIR, 302 302 + }; 303 303 + 304 304 + ret = gpio_generic_chip_init(&hisi_gpio->chip, &config); 302 305 if (ret) { 303 306 dev_err(dev, "failed to init, ret = %d\n", ret); 304 307 return ret; 305 308 } 306 309 307 307 - hisi_gpio->chip.set_config = hisi_gpio_set_config; 308 308 - hisi_gpio->chip.ngpio = hisi_gpio->line_num; 309 309 - hisi_gpio->chip.bgpio_dir_unreadable = 1; 310 310 - hisi_gpio->chip.base = -1; 310 310 + hisi_gpio->chip.gc.set_config = hisi_gpio_set_config; 311 311 + hisi_gpio->chip.gc.ngpio = hisi_gpio->line_num; 312 312 + hisi_gpio->chip.gc.base = -1; 311 313 312 314 if (hisi_gpio->irq > 0) 313 315 hisi_gpio_init_irq(hisi_gpio); 314 316 315 315 - ret = devm_gpiochip_add_data(dev, &hisi_gpio->chip, hisi_gpio); 317 317 + ret = devm_gpiochip_add_data(dev, &hisi_gpio->chip.gc, hisi_gpio); 316 318 if (ret) { 317 319 dev_err(dev, "failed to register gpiochip, ret = %d\n", ret); 318 320 return ret;

+54 -51

drivers/gpio/gpio-hlwd.c

reviewed

··· 6 6 // Nintendo Wii (Hollywood) GPIO driver 7 7 8 8 #include <linux/gpio/driver.h> 9 9 + #include <linux/gpio/generic.h> 9 10 #include <linux/io.h> 10 11 #include <linux/kernel.h> 11 12 #include <linux/module.h> ··· 49 48 #define HW_GPIO_OWNER 0x3c 50 49 51 50 struct hlwd_gpio { 52 52 - struct gpio_chip gpioc; 51 51 + struct gpio_generic_chip gpioc; 53 52 struct device *dev; 54 53 void __iomem *regs; 55 54 int irq; ··· 62 61 struct hlwd_gpio *hlwd = 63 62 gpiochip_get_data(irq_desc_get_handler_data(desc)); 64 63 struct irq_chip *chip = irq_desc_get_chip(desc); 65 65 - unsigned long flags; 66 64 unsigned long pending; 67 65 int hwirq; 68 66 u32 emulated_pending; 69 67 70 70 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 71 71 - pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG); 72 72 - pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK); 68 68 + scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) { 69 69 + pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG); 70 70 + pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK); 73 71 74 74 - /* Treat interrupts due to edge trigger emulation separately */ 75 75 - emulated_pending = hlwd->edge_emulation & pending; 76 76 - pending &= ~emulated_pending; 77 77 - if (emulated_pending) { 78 78 - u32 level, rising, falling; 72 72 + /* Treat interrupts due to edge trigger emulation separately */ 73 73 + emulated_pending = hlwd->edge_emulation & pending; 74 74 + pending &= ~emulated_pending; 75 75 + if (emulated_pending) { 76 76 + u32 level, rising, falling; 79 77 80 80 - level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL); 81 81 - rising = level & emulated_pending; 82 82 - falling = ~level & emulated_pending; 78 78 + level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL); 79 79 + rising = level & emulated_pending; 80 80 + falling = ~level & emulated_pending; 83 81 84 84 - /* Invert the levels */ 85 85 - iowrite32be(level ^ emulated_pending, 86 86 - hlwd->regs + HW_GPIOB_INTLVL); 82 82 + /* Invert the levels */ 83 83 + iowrite32be(level ^ emulated_pending, 84 84 + hlwd->regs + HW_GPIOB_INTLVL); 87 85 88 88 - /* Ack all emulated-edge interrupts */ 89 89 - iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG); 86 86 + /* Ack all emulated-edge interrupts */ 87 87 + iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG); 90 88 91 91 - /* Signal interrupts only on the correct edge */ 92 92 - rising &= hlwd->rising_edge; 93 93 - falling &= hlwd->falling_edge; 89 89 + /* Signal interrupts only on the correct edge */ 90 90 + rising &= hlwd->rising_edge; 91 91 + falling &= hlwd->falling_edge; 94 92 95 95 - /* Mark emulated interrupts as pending */ 96 96 - pending |= rising | falling; 93 93 + /* Mark emulated interrupts as pending */ 94 94 + pending |= rising | falling; 95 95 + } 97 96 } 98 98 - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 99 97 100 98 chained_irq_enter(chip, desc); 101 99 102 100 for_each_set_bit(hwirq, &pending, 32) 103 103 - generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq); 101 101 + generic_handle_domain_irq(hlwd->gpioc.gc.irq.domain, hwirq); 104 102 105 103 chained_irq_exit(chip, desc); 106 104 } ··· 116 116 { 117 117 struct hlwd_gpio *hlwd = 118 118 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 119 119 - unsigned long flags; 120 119 u32 mask; 121 120 122 122 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 123 123 - mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); 124 124 - mask &= ~BIT(data->hwirq); 125 125 - iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); 126 126 - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 127 127 - gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); 121 121 + scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) { 122 122 + mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); 123 123 + mask &= ~BIT(data->hwirq); 124 124 + iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); 125 125 + } 126 126 + gpiochip_disable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data)); 128 127 } 129 128 130 129 static void hlwd_gpio_irq_unmask(struct irq_data *data) 131 130 { 132 131 struct hlwd_gpio *hlwd = 133 132 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 134 134 - unsigned long flags; 135 133 u32 mask; 136 134 137 137 - gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); 138 138 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 135 135 + gpiochip_enable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data)); 136 136 + 137 137 + guard(gpio_generic_lock_irqsave)(&hlwd->gpioc); 138 138 + 139 139 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); 140 140 mask |= BIT(data->hwirq); 141 141 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); 142 142 - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 143 142 } 144 143 145 144 static void hlwd_gpio_irq_enable(struct irq_data *data) ··· 172 173 { 173 174 struct hlwd_gpio *hlwd = 174 175 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 175 175 - unsigned long flags; 176 176 u32 level; 177 177 178 178 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 178 178 + guard(gpio_generic_lock_irqsave)(&hlwd->gpioc); 179 179 180 180 hlwd->edge_emulation &= ~BIT(data->hwirq); 181 181 ··· 195 197 hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type); 196 198 break; 197 199 default: 198 198 - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 199 200 return -EINVAL; 200 201 } 201 202 202 202 - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 203 203 return 0; 204 204 } 205 205 ··· 221 225 222 226 static int hlwd_gpio_probe(struct platform_device *pdev) 223 227 { 228 228 + struct gpio_generic_chip_config config; 224 229 struct hlwd_gpio *hlwd; 225 230 u32 ngpios; 226 231 int res; ··· 241 244 * systems where the AHBPROT memory firewall hasn't been configured to 242 245 * permit PPC access to HW_GPIO_*. 243 246 * 244 244 - * Note that this has to happen before bgpio_init reads the 245 245 - * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong 246 246 - * values. 247 247 + * Note that this has to happen before gpio_generic_chip_init() reads 248 248 + * the HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the 249 249 + * wrong values. 247 250 */ 248 251 iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER); 249 252 250 250 - res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4, 251 251 - hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT, 252 252 - NULL, hlwd->regs + HW_GPIOB_DIR, NULL, 253 253 - BGPIOF_BIG_ENDIAN_BYTE_ORDER); 253 253 + config = (struct gpio_generic_chip_config) { 254 254 + .dev = &pdev->dev, 255 255 + .sz = 4, 256 256 + .dat = hlwd->regs + HW_GPIOB_IN, 257 257 + .set = hlwd->regs + HW_GPIOB_OUT, 258 258 + .dirout = hlwd->regs + HW_GPIOB_DIR, 259 259 + .flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER, 260 260 + }; 261 261 + 262 262 + res = gpio_generic_chip_init(&hlwd->gpioc, &config); 254 263 if (res < 0) { 255 255 - dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res); 264 264 + dev_warn(&pdev->dev, "failed to initialize generic GPIO chip: %d\n", res); 256 265 return res; 257 266 } 258 267 259 268 res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios); 260 269 if (res) 261 270 ngpios = 32; 262 262 - hlwd->gpioc.ngpio = ngpios; 271 271 + hlwd->gpioc.gc.ngpio = ngpios; 263 272 264 273 /* Mask and ack all interrupts */ 265 274 iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK); ··· 285 282 return hlwd->irq; 286 283 } 287 284 288 288 - girq = &hlwd->gpioc.irq; 285 285 + girq = &hlwd->gpioc.gc.irq; 289 286 gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip); 290 287 girq->parent_handler = hlwd_gpio_irqhandler; 291 288 girq->num_parents = 1; ··· 299 296 girq->handler = handle_level_irq; 300 297 } 301 298 302 302 - return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd); 299 299 + return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc.gc, hlwd); 303 300 } 304 301 305 302 static const struct of_device_id hlwd_gpio_match[] = {

+23 -22

drivers/gpio/gpio-idt3243x.c

reviewed

··· 3 3 4 4 #include <linux/bitops.h> 5 5 #include <linux/gpio/driver.h> 6 6 + #include <linux/gpio/generic.h> 6 7 #include <linux/irq.h> 7 8 #include <linux/module.h> 8 9 #include <linux/mod_devicetable.h> ··· 19 18 #define IDT_GPIO_ISTAT 0x0C 20 19 21 20 struct idt_gpio_ctrl { 22 22 - struct gpio_chip gc; 21 21 + struct gpio_generic_chip chip; 23 22 void __iomem *pic; 24 23 void __iomem *gpio; 25 24 u32 mask_cache; ··· 51 50 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 52 51 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); 53 52 unsigned int sense = flow_type & IRQ_TYPE_SENSE_MASK; 54 54 - unsigned long flags; 55 53 u32 ilevel; 56 54 57 55 /* hardware only supports level triggered */ 58 56 if (sense == IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH)) 59 57 return -EINVAL; 60 58 61 61 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 59 59 + guard(gpio_generic_lock_irqsave)(&ctrl->chip); 62 60 63 61 ilevel = readl(ctrl->gpio + IDT_GPIO_ILEVEL); 64 62 if (sense & IRQ_TYPE_LEVEL_HIGH) ··· 68 68 writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL); 69 69 irq_set_handler_locked(d, handle_level_irq); 70 70 71 71 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 72 71 return 0; 73 72 } 74 73 ··· 83 84 { 84 85 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 85 86 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); 86 86 - unsigned long flags; 87 87 88 88 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 89 89 - 90 90 - ctrl->mask_cache |= BIT(d->hwirq); 91 91 - writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); 92 92 - 93 93 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 88 88 + scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) { 89 89 + ctrl->mask_cache |= BIT(d->hwirq); 90 90 + writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); 91 91 + } 94 92 95 93 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 96 94 } ··· 96 100 { 97 101 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 98 102 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); 99 99 - unsigned long flags; 100 103 101 104 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 102 102 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 105 105 + 106 106 + guard(gpio_generic_lock_irqsave)(&ctrl->chip); 103 107 104 108 ctrl->mask_cache &= ~BIT(d->hwirq); 105 109 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); 106 106 - 107 107 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 108 110 } 109 111 110 112 static int idt_gpio_irq_init_hw(struct gpio_chip *gc) ··· 128 134 129 135 static int idt_gpio_probe(struct platform_device *pdev) 130 136 { 137 137 + struct gpio_generic_chip_config config; 131 138 struct device *dev = &pdev->dev; 132 139 struct gpio_irq_chip *girq; 133 140 struct idt_gpio_ctrl *ctrl; ··· 145 150 if (IS_ERR(ctrl->gpio)) 146 151 return PTR_ERR(ctrl->gpio); 147 152 148 148 - ctrl->gc.parent = dev; 153 153 + ctrl->chip.gc.parent = dev; 149 154 150 150 - ret = bgpio_init(&ctrl->gc, &pdev->dev, 4, ctrl->gpio + IDT_GPIO_DATA, 151 151 - NULL, NULL, ctrl->gpio + IDT_GPIO_DIR, NULL, 0); 155 155 + config = (struct gpio_generic_chip_config) { 156 156 + .dev = &pdev->dev, 157 157 + .sz = 4, 158 158 + .dat = ctrl->gpio + IDT_GPIO_DATA, 159 159 + .dirout = ctrl->gpio + IDT_GPIO_DIR, 160 160 + }; 161 161 + 162 162 + ret = gpio_generic_chip_init(&ctrl->chip, &config); 152 163 if (ret) { 153 153 - dev_err(dev, "bgpio_init failed\n"); 164 164 + dev_err(dev, "failed to initialize the generic GPIO chip\n"); 154 165 return ret; 155 166 } 156 167 157 168 ret = device_property_read_u32(dev, "ngpios", &ngpios); 158 169 if (!ret) 159 159 - ctrl->gc.ngpio = ngpios; 170 170 + ctrl->chip.gc.ngpio = ngpios; 160 171 161 172 if (device_property_read_bool(dev, "interrupt-controller")) { 162 173 ctrl->pic = devm_platform_ioremap_resource_byname(pdev, "pic"); ··· 173 172 if (parent_irq < 0) 174 173 return parent_irq; 175 174 176 176 - girq = &ctrl->gc.irq; 175 175 + girq = &ctrl->chip.gc.irq; 177 176 gpio_irq_chip_set_chip(girq, &idt_gpio_irqchip); 178 177 girq->init_hw = idt_gpio_irq_init_hw; 179 178 girq->parent_handler = idt_gpio_dispatch; ··· 189 188 girq->handler = handle_bad_irq; 190 189 } 191 190 192 192 - return devm_gpiochip_add_data(&pdev->dev, &ctrl->gc, ctrl); 191 191 + return devm_gpiochip_add_data(&pdev->dev, &ctrl->chip.gc, ctrl); 193 192 } 194 193 195 194 static const struct of_device_id idt_gpio_of_match[] = {

+37 -35

drivers/gpio/gpio-ixp4xx.c

reviewed

··· 8 8 9 9 #include <linux/bitops.h> 10 10 #include <linux/gpio/driver.h> 11 11 + #include <linux/gpio/generic.h> 11 12 #include <linux/io.h> 12 13 #include <linux/irq.h> 13 14 #include <linux/irqdomain.h> ··· 54 53 55 54 /** 56 55 * struct ixp4xx_gpio - IXP4 GPIO state container 56 56 + * @chip: generic GPIO chip for this instance 57 57 * @dev: containing device for this instance 58 58 - * @gc: gpiochip for this instance 59 58 * @base: remapped I/O-memory base 60 59 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered, 61 60 * 0: level triggered 62 61 */ 63 62 struct ixp4xx_gpio { 64 64 - struct gpio_chip gc; 63 63 + struct gpio_generic_chip chip; 65 64 struct device *dev; 66 65 void __iomem *base; 67 66 unsigned long long irq_edge; ··· 101 100 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 102 101 struct ixp4xx_gpio *g = gpiochip_get_data(gc); 103 102 int line = d->hwirq; 104 104 - unsigned long flags; 105 103 u32 int_style; 106 104 u32 int_reg; 107 105 u32 val; ··· 144 144 int_reg = IXP4XX_REG_GPIT1; 145 145 } 146 146 147 147 - raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags); 147 147 + scoped_guard(gpio_generic_lock_irqsave, &g->chip) { 148 148 + /* Clear the style for the appropriate pin */ 149 149 + val = __raw_readl(g->base + int_reg); 150 150 + val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); 151 151 + __raw_writel(val, g->base + int_reg); 148 152 149 149 - /* Clear the style for the appropriate pin */ 150 150 - val = __raw_readl(g->base + int_reg); 151 151 - val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); 152 152 - __raw_writel(val, g->base + int_reg); 153 153 + __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); 153 154 154 154 - __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); 155 155 + /* Set the new style */ 156 156 + val = __raw_readl(g->base + int_reg); 157 157 + val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); 158 158 + __raw_writel(val, g->base + int_reg); 155 159 156 156 - /* Set the new style */ 157 157 - val = __raw_readl(g->base + int_reg); 158 158 - val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); 159 159 - __raw_writel(val, g->base + int_reg); 160 160 - 161 161 - /* Force-configure this line as an input */ 162 162 - val = __raw_readl(g->base + IXP4XX_REG_GPOE); 163 163 - val |= BIT(d->hwirq); 164 164 - __raw_writel(val, g->base + IXP4XX_REG_GPOE); 165 165 - 166 166 - raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags); 160 160 + /* Force-configure this line as an input */ 161 161 + val = __raw_readl(g->base + IXP4XX_REG_GPOE); 162 162 + val |= BIT(d->hwirq); 163 163 + __raw_writel(val, g->base + IXP4XX_REG_GPOE); 164 164 + } 167 165 168 166 /* This parent only accept level high (asserted) */ 169 167 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); ··· 204 206 205 207 static int ixp4xx_gpio_probe(struct platform_device *pdev) 206 208 { 209 209 + struct gpio_generic_chip_config config; 207 210 unsigned long flags; 208 211 struct device *dev = &pdev->dev; 209 212 struct device_node *np = dev->of_node; ··· 289 290 * for big endian. 290 291 */ 291 292 #if defined(CONFIG_CPU_BIG_ENDIAN) 292 292 - flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; 293 293 + flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 293 294 #else 294 295 flags = 0; 295 296 #endif 296 297 298 298 + config = (struct gpio_generic_chip_config) { 299 299 + .dev = dev, 300 300 + .sz = 4, 301 301 + .dat = g->base + IXP4XX_REG_GPIN, 302 302 + .set = g->base + IXP4XX_REG_GPOUT, 303 303 + .dirin = g->base + IXP4XX_REG_GPOE, 304 304 + .flags = flags, 305 305 + }; 306 306 + 297 307 /* Populate and register gpio chip */ 298 298 - ret = bgpio_init(&g->gc, dev, 4, 299 299 - g->base + IXP4XX_REG_GPIN, 300 300 - g->base + IXP4XX_REG_GPOUT, 301 301 - NULL, 302 302 - NULL, 303 303 - g->base + IXP4XX_REG_GPOE, 304 304 - flags); 308 308 + ret = gpio_generic_chip_init(&g->chip, &config); 305 309 if (ret) { 306 310 dev_err(dev, "unable to init generic GPIO\n"); 307 311 return ret; 308 312 } 309 309 - g->gc.ngpio = 16; 310 310 - g->gc.label = "IXP4XX_GPIO_CHIP"; 313 313 + g->chip.gc.ngpio = 16; 314 314 + g->chip.gc.label = "IXP4XX_GPIO_CHIP"; 311 315 /* 312 316 * TODO: when we have migrated to device tree and all GPIOs 313 317 * are fetched using phandles, set this to -1 to get rid of 314 318 * the fixed gpiochip base. 315 319 */ 316 316 - g->gc.base = 0; 317 317 - g->gc.parent = &pdev->dev; 318 318 - g->gc.owner = THIS_MODULE; 320 320 + g->chip.gc.base = 0; 321 321 + g->chip.gc.parent = &pdev->dev; 322 322 + g->chip.gc.owner = THIS_MODULE; 319 323 320 320 - girq = &g->gc.irq; 324 324 + girq = &g->chip.gc.irq; 321 325 gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip); 322 326 girq->fwnode = dev_fwnode(dev); 323 327 girq->parent_domain = parent; ··· 328 326 girq->handler = handle_bad_irq; 329 327 girq->default_type = IRQ_TYPE_NONE; 330 328 331 331 - ret = devm_gpiochip_add_data(dev, &g->gc, g); 329 329 + ret = devm_gpiochip_add_data(dev, &g->chip.gc, g); 332 330 if (ret) { 333 331 dev_err(dev, "failed to add SoC gpiochip\n"); 334 332 return ret;

+206 -22

drivers/gpio/gpio-loongson-64bit.c

reviewed

··· 7 7 8 8 #include <linux/kernel.h> 9 9 #include <linux/init.h> 10 10 + #include <linux/irq.h> 11 11 + #include <linux/irqdesc.h> 10 12 #include <linux/module.h> 11 13 #include <linux/spinlock.h> 12 14 #include <linux/err.h> 13 15 #include <linux/gpio/driver.h> 16 16 + #include <linux/gpio/generic.h> 14 17 #include <linux/platform_device.h> 15 18 #include <linux/bitops.h> 19 19 + #include <linux/reset.h> 16 20 #include <asm/types.h> 17 21 18 22 enum loongson_gpio_mode { ··· 31 27 unsigned int out_offset; 32 28 unsigned int in_offset; 33 29 unsigned int inten_offset; 30 30 + unsigned int intpol_offset; 31 31 + unsigned int intedge_offset; 32 32 + unsigned int intclr_offset; 33 33 + unsigned int intsts_offset; 34 34 + unsigned int intdual_offset; 35 35 + unsigned int intr_num; 36 36 + irq_flow_handler_t irq_handler; 37 37 + const struct irq_chip *girqchip; 34 38 }; 35 39 36 40 struct loongson_gpio_chip { 37 37 - struct gpio_chip chip; 41 41 + struct gpio_generic_chip chip; 38 42 spinlock_t lock; 39 43 void __iomem *reg_base; 40 44 const struct loongson_gpio_chip_data *chip_data; ··· 50 38 51 39 static inline struct loongson_gpio_chip *to_loongson_gpio_chip(struct gpio_chip *chip) 52 40 { 53 53 - return container_of(chip, struct loongson_gpio_chip, chip); 41 41 + return container_of(to_gpio_generic_chip(chip), 42 42 + struct loongson_gpio_chip, chip); 54 43 } 55 44 56 45 static inline void loongson_commit_direction(struct loongson_gpio_chip *lgpio, unsigned int pin, ··· 148 135 return platform_get_irq(pdev, offset); 149 136 } 150 137 151 151 - static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chip *lgpio, 138 138 + static void loongson_gpio_irq_ack(struct irq_data *data) 139 139 + { 140 140 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 141 141 + struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip); 142 142 + irq_hw_number_t hwirq = irqd_to_hwirq(data); 143 143 + 144 144 + writeb(0x1, lgpio->reg_base + lgpio->chip_data->intclr_offset + hwirq); 145 145 + } 146 146 + 147 147 + static void loongson_gpio_irq_mask(struct irq_data *data) 148 148 + { 149 149 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 150 150 + struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip); 151 151 + irq_hw_number_t hwirq = irqd_to_hwirq(data); 152 152 + 153 153 + writeb(0x0, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq); 154 154 + } 155 155 + 156 156 + static void loongson_gpio_irq_unmask(struct irq_data *data) 157 157 + { 158 158 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 159 159 + struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip); 160 160 + irq_hw_number_t hwirq = irqd_to_hwirq(data); 161 161 + 162 162 + writeb(0x1, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq); 163 163 + } 164 164 + 165 165 + static int loongson_gpio_irq_set_type(struct irq_data *data, unsigned int type) 166 166 + { 167 167 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 168 168 + struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip); 169 169 + irq_hw_number_t hwirq = irqd_to_hwirq(data); 170 170 + u8 pol = 0, edge = 0, dual = 0; 171 171 + 172 172 + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 173 173 + edge = 1; 174 174 + dual = 1; 175 175 + irq_set_handler_locked(data, handle_edge_irq); 176 176 + } else { 177 177 + switch (type) { 178 178 + case IRQ_TYPE_LEVEL_HIGH: 179 179 + pol = 1; 180 180 + fallthrough; 181 181 + case IRQ_TYPE_LEVEL_LOW: 182 182 + irq_set_handler_locked(data, handle_level_irq); 183 183 + break; 184 184 + 185 185 + case IRQ_TYPE_EDGE_RISING: 186 186 + pol = 1; 187 187 + fallthrough; 188 188 + case IRQ_TYPE_EDGE_FALLING: 189 189 + edge = 1; 190 190 + irq_set_handler_locked(data, handle_edge_irq); 191 191 + break; 192 192 + 193 193 + default: 194 194 + return -EINVAL; 195 195 + } 196 196 + } 197 197 + 198 198 + writeb(pol, lgpio->reg_base + lgpio->chip_data->intpol_offset + hwirq); 199 199 + writeb(edge, lgpio->reg_base + lgpio->chip_data->intedge_offset + hwirq); 200 200 + writeb(dual, lgpio->reg_base + lgpio->chip_data->intdual_offset + hwirq); 201 201 + 202 202 + return 0; 203 203 + } 204 204 + 205 205 + static void loongson_gpio_ls2k0300_irq_handler(struct irq_desc *desc) 206 206 + { 207 207 + struct loongson_gpio_chip *lgpio = irq_desc_get_handler_data(desc); 208 208 + struct irq_chip *girqchip = irq_desc_get_chip(desc); 209 209 + int i; 210 210 + 211 211 + chained_irq_enter(girqchip, desc); 212 212 + 213 213 + for (i = 0; i < lgpio->chip.gc.ngpio; i++) { 214 214 + /* 215 215 + * For the GPIO controller of LS2K0300, interrupts status bits 216 216 + * may be wrongly set even if the corresponding interrupt is 217 217 + * disabled. Thus interrupt enable bits are checked along with 218 218 + * status bits to detect interrupts reliably. 219 219 + */ 220 220 + if (readb(lgpio->reg_base + lgpio->chip_data->intsts_offset + i) && 221 221 + readb(lgpio->reg_base + lgpio->chip_data->inten_offset + i)) 222 222 + generic_handle_domain_irq(lgpio->chip.gc.irq.domain, i); 223 223 + } 224 224 + 225 225 + chained_irq_exit(girqchip, desc); 226 226 + } 227 227 + 228 228 + static const struct irq_chip loongson_gpio_ls2k0300_irqchip = { 229 229 + .irq_ack = loongson_gpio_irq_ack, 230 230 + .irq_mask = loongson_gpio_irq_mask, 231 231 + .irq_unmask = loongson_gpio_irq_unmask, 232 232 + .irq_set_type = loongson_gpio_irq_set_type, 233 233 + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE, 234 234 + GPIOCHIP_IRQ_RESOURCE_HELPERS, 235 235 + }; 236 236 + 237 237 + static int loongson_gpio_init_irqchip(struct platform_device *pdev, 238 238 + struct loongson_gpio_chip *lgpio) 239 239 + { 240 240 + const struct loongson_gpio_chip_data *data = lgpio->chip_data; 241 241 + struct gpio_chip *chip = &lgpio->chip.gc; 242 242 + int i; 243 243 + 244 244 + chip->irq.default_type = IRQ_TYPE_NONE; 245 245 + chip->irq.handler = handle_bad_irq; 246 246 + chip->irq.parent_handler = data->irq_handler; 247 247 + chip->irq.parent_handler_data = lgpio; 248 248 + gpio_irq_chip_set_chip(&chip->irq, data->girqchip); 249 249 + 250 250 + chip->irq.num_parents = data->intr_num; 251 251 + chip->irq.parents = devm_kcalloc(&pdev->dev, data->intr_num, 252 252 + sizeof(*chip->irq.parents), GFP_KERNEL); 253 253 + if (!chip->parent) 254 254 + return -ENOMEM; 255 255 + 256 256 + for (i = 0; i < data->intr_num; i++) { 257 257 + int ret; 258 258 + 259 259 + ret = platform_get_irq(pdev, i); 260 260 + if (ret < 0) 261 261 + return dev_err_probe(&pdev->dev, ret, 262 262 + "failed to get IRQ %d\n", i); 263 263 + chip->irq.parents[i] = ret; 264 264 + } 265 265 + 266 266 + for (i = 0; i < data->intr_num; i++) { 267 267 + writeb(0x0, lgpio->reg_base + data->inten_offset + i); 268 268 + writeb(0x1, lgpio->reg_base + data->intclr_offset + i); 269 269 + } 270 270 + 271 271 + return 0; 272 272 + } 273 273 + 274 274 + static int loongson_gpio_init(struct platform_device *pdev, struct loongson_gpio_chip *lgpio, 152 275 void __iomem *reg_base) 153 276 { 277 277 + struct gpio_generic_chip_config config; 154 278 int ret; 155 279 156 280 lgpio->reg_base = reg_base; 157 281 if (lgpio->chip_data->mode == BIT_CTRL_MODE) { 158 158 - ret = bgpio_init(&lgpio->chip, dev, 8, 159 159 - lgpio->reg_base + lgpio->chip_data->in_offset, 160 160 - lgpio->reg_base + lgpio->chip_data->out_offset, 161 161 - NULL, NULL, 162 162 - lgpio->reg_base + lgpio->chip_data->conf_offset, 163 163 - 0); 282 282 + config = (struct gpio_generic_chip_config) { 283 283 + .dev = &pdev->dev, 284 284 + .sz = 8, 285 285 + .dat = lgpio->reg_base + lgpio->chip_data->in_offset, 286 286 + .set = lgpio->reg_base + lgpio->chip_data->out_offset, 287 287 + .dirin = lgpio->reg_base + lgpio->chip_data->conf_offset, 288 288 + }; 289 289 + 290 290 + ret = gpio_generic_chip_init(&lgpio->chip, &config); 164 291 if (ret) { 165 165 - dev_err(dev, "unable to init generic GPIO\n"); 292 292 + dev_err(&pdev->dev, "unable to init generic GPIO\n"); 166 293 return ret; 167 294 } 168 295 } else { 169 169 - lgpio->chip.direction_input = loongson_gpio_direction_input; 170 170 - lgpio->chip.get = loongson_gpio_get; 171 171 - lgpio->chip.get_direction = loongson_gpio_get_direction; 172 172 - lgpio->chip.direction_output = loongson_gpio_direction_output; 173 173 - lgpio->chip.set = loongson_gpio_set; 174 174 - lgpio->chip.parent = dev; 296 296 + lgpio->chip.gc.direction_input = loongson_gpio_direction_input; 297 297 + lgpio->chip.gc.get = loongson_gpio_get; 298 298 + lgpio->chip.gc.get_direction = loongson_gpio_get_direction; 299 299 + lgpio->chip.gc.direction_output = loongson_gpio_direction_output; 300 300 + lgpio->chip.gc.set = loongson_gpio_set; 301 301 + lgpio->chip.gc.parent = &pdev->dev; 175 302 spin_lock_init(&lgpio->lock); 176 303 } 177 304 178 178 - lgpio->chip.label = lgpio->chip_data->label; 179 179 - lgpio->chip.can_sleep = false; 180 180 - if (lgpio->chip_data->inten_offset) 181 181 - lgpio->chip.to_irq = loongson_gpio_to_irq; 305 305 + lgpio->chip.gc.label = lgpio->chip_data->label; 306 306 + lgpio->chip.gc.can_sleep = false; 307 307 + if (lgpio->chip_data->girqchip) { 308 308 + ret = loongson_gpio_init_irqchip(pdev, lgpio); 309 309 + if (ret) 310 310 + return dev_err_probe(&pdev->dev, ret, "failed to initialize irqchip\n"); 311 311 + } else if (lgpio->chip_data->inten_offset) { 312 312 + lgpio->chip.gc.to_irq = loongson_gpio_to_irq; 313 313 + } 182 314 183 183 - return devm_gpiochip_add_data(dev, &lgpio->chip, lgpio); 315 315 + return devm_gpiochip_add_data(&pdev->dev, &lgpio->chip.gc, lgpio); 184 316 } 185 317 186 318 static int loongson_gpio_probe(struct platform_device *pdev) ··· 333 175 void __iomem *reg_base; 334 176 struct loongson_gpio_chip *lgpio; 335 177 struct device *dev = &pdev->dev; 178 178 + struct reset_control *rst; 336 179 337 180 lgpio = devm_kzalloc(dev, sizeof(*lgpio), GFP_KERNEL); 338 181 if (!lgpio) ··· 345 186 if (IS_ERR(reg_base)) 346 187 return PTR_ERR(reg_base); 347 188 348 348 - return loongson_gpio_init(dev, lgpio, reg_base); 189 189 + rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL); 190 190 + if (IS_ERR(rst)) 191 191 + return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get reset control\n"); 192 192 + 193 193 + return loongson_gpio_init(pdev, lgpio, reg_base); 349 194 } 350 195 351 196 static const struct loongson_gpio_chip_data loongson_gpio_ls2k_data = { ··· 359 196 .in_offset = 0x20, 360 197 .out_offset = 0x10, 361 198 .inten_offset = 0x30, 199 199 + }; 200 200 + 201 201 + static const struct loongson_gpio_chip_data loongson_gpio_ls2k0300_data = { 202 202 + .label = "ls2k0300_gpio", 203 203 + .mode = BYTE_CTRL_MODE, 204 204 + .conf_offset = 0x800, 205 205 + .in_offset = 0xa00, 206 206 + .out_offset = 0x900, 207 207 + .inten_offset = 0xb00, 208 208 + .intpol_offset = 0xc00, 209 209 + .intedge_offset = 0xd00, 210 210 + .intclr_offset = 0xe00, 211 211 + .intsts_offset = 0xf00, 212 212 + .intdual_offset = 0xf80, 213 213 + .intr_num = 7, 214 214 + .irq_handler = loongson_gpio_ls2k0300_irq_handler, 215 215 + .girqchip = &loongson_gpio_ls2k0300_irqchip, 362 216 }; 363 217 364 218 static const struct loongson_gpio_chip_data loongson_gpio_ls2k0500_data0 = { ··· 473 293 { 474 294 .compatible = "loongson,ls2k-gpio", 475 295 .data = &loongson_gpio_ls2k_data, 296 296 + }, 297 297 + { 298 298 + .compatible = "loongson,ls2k0300-gpio", 299 299 + .data = &loongson_gpio_ls2k0300_data, 476 300 }, 477 301 { 478 302 .compatible = "loongson,ls2k0500-gpio0",

+23 -17

drivers/gpio/gpio-loongson1.c

reviewed

··· 5 5 * Copyright (C) 2015-2023 Keguang Zhang <keguang.zhang@gmail.com> 6 6 */ 7 7 8 8 + #include <linux/bitops.h> 8 9 #include <linux/module.h> 9 10 #include <linux/gpio/driver.h> 11 11 + #include <linux/gpio/generic.h> 10 12 #include <linux/platform_device.h> 11 11 - #include <linux/bitops.h> 12 13 13 14 /* Loongson 1 GPIO Register Definitions */ 14 15 #define GPIO_CFG 0x0 ··· 18 17 #define GPIO_OUTPUT 0x30 19 18 20 19 struct ls1x_gpio_chip { 21 21 - struct gpio_chip gc; 20 20 + struct gpio_generic_chip chip; 22 21 void __iomem *reg_base; 23 22 }; 24 23 25 24 static int ls1x_gpio_request(struct gpio_chip *gc, unsigned int offset) 26 25 { 27 26 struct ls1x_gpio_chip *ls1x_gc = gpiochip_get_data(gc); 28 28 - unsigned long flags; 29 27 30 30 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 28 28 + guard(gpio_generic_lock_irqsave)(&ls1x_gc->chip); 29 29 + 31 30 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset), 32 31 ls1x_gc->reg_base + GPIO_CFG); 33 33 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 34 32 35 33 return 0; 36 34 } ··· 37 37 static void ls1x_gpio_free(struct gpio_chip *gc, unsigned int offset) 38 38 { 39 39 struct ls1x_gpio_chip *ls1x_gc = gpiochip_get_data(gc); 40 40 - unsigned long flags; 41 40 42 42 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 41 41 + guard(gpio_generic_lock_irqsave)(&ls1x_gc->chip); 42 42 + 43 43 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset), 44 44 ls1x_gc->reg_base + GPIO_CFG); 45 45 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 46 45 } 47 46 48 47 static int ls1x_gpio_probe(struct platform_device *pdev) 49 48 { 49 49 + struct gpio_generic_chip_config config; 50 50 struct device *dev = &pdev->dev; 51 51 struct ls1x_gpio_chip *ls1x_gc; 52 52 int ret; ··· 59 59 if (IS_ERR(ls1x_gc->reg_base)) 60 60 return PTR_ERR(ls1x_gc->reg_base); 61 61 62 62 - ret = bgpio_init(&ls1x_gc->gc, dev, 4, ls1x_gc->reg_base + GPIO_DATA, 63 63 - ls1x_gc->reg_base + GPIO_OUTPUT, NULL, 64 64 - NULL, ls1x_gc->reg_base + GPIO_DIR, 0); 62 62 + config = (struct gpio_generic_chip_config) { 63 63 + .dev = dev, 64 64 + .sz = 4, 65 65 + .dat = ls1x_gc->reg_base + GPIO_DATA, 66 66 + .set = ls1x_gc->reg_base + GPIO_OUTPUT, 67 67 + .dirin = ls1x_gc->reg_base + GPIO_DIR, 68 68 + }; 69 69 + 70 70 + ret = gpio_generic_chip_init(&ls1x_gc->chip, &config); 65 71 if (ret) 66 72 goto err; 67 73 68 68 - ls1x_gc->gc.owner = THIS_MODULE; 69 69 - ls1x_gc->gc.request = ls1x_gpio_request; 70 70 - ls1x_gc->gc.free = ls1x_gpio_free; 74 74 + ls1x_gc->chip.gc.owner = THIS_MODULE; 75 75 + ls1x_gc->chip.gc.request = ls1x_gpio_request; 76 76 + ls1x_gc->chip.gc.free = ls1x_gpio_free; 71 77 /* 72 78 * Clear ngpio to let gpiolib get the correct number 73 79 * by reading ngpios property 74 80 */ 75 75 - ls1x_gc->gc.ngpio = 0; 81 81 + ls1x_gc->chip.gc.ngpio = 0; 76 82 77 77 - ret = devm_gpiochip_add_data(dev, &ls1x_gc->gc, ls1x_gc); 83 83 + ret = devm_gpiochip_add_data(dev, &ls1x_gc->chip.gc, ls1x_gc); 78 84 if (ret) 79 85 goto err; 80 86 81 87 platform_set_drvdata(pdev, ls1x_gc); 82 88 83 89 dev_info(dev, "GPIO controller registered with %d pins\n", 84 84 - ls1x_gc->gc.ngpio); 90 90 + ls1x_gc->chip.gc.ngpio); 85 91 86 92 return 0; 87 93 err:

+257

drivers/gpio/gpio-max7360.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright 2025 Bootlin 4 4 + * 5 5 + * Author: Kamel BOUHARA <kamel.bouhara@bootlin.com> 6 6 + * Author: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 7 7 + */ 8 8 + 9 9 + #include <linux/bitfield.h> 10 10 + #include <linux/bitmap.h> 11 11 + #include <linux/err.h> 12 12 + #include <linux/gpio/driver.h> 13 13 + #include <linux/gpio/regmap.h> 14 14 + #include <linux/init.h> 15 15 + #include <linux/interrupt.h> 16 16 + #include <linux/mfd/max7360.h> 17 17 + #include <linux/minmax.h> 18 18 + #include <linux/mod_devicetable.h> 19 19 + #include <linux/module.h> 20 20 + #include <linux/platform_device.h> 21 21 + #include <linux/property.h> 22 22 + #include <linux/regmap.h> 23 23 + 24 24 + #define MAX7360_GPIO_PORT 1 25 25 + #define MAX7360_GPIO_COL 2 26 26 + 27 27 + struct max7360_gpio_plat_data { 28 28 + unsigned int function; 29 29 + }; 30 30 + 31 31 + static struct max7360_gpio_plat_data max7360_gpio_port_plat = { .function = MAX7360_GPIO_PORT }; 32 32 + static struct max7360_gpio_plat_data max7360_gpio_col_plat = { .function = MAX7360_GPIO_COL }; 33 33 + 34 34 + static int max7360_get_available_gpos(struct device *dev, unsigned int *available_gpios) 35 35 + { 36 36 + u32 columns; 37 37 + int ret; 38 38 + 39 39 + ret = device_property_read_u32(dev->parent, "keypad,num-columns", &columns); 40 40 + if (ret) { 41 41 + dev_err(dev, "Failed to read columns count\n"); 42 42 + return ret; 43 43 + } 44 44 + 45 45 + *available_gpios = min(MAX7360_MAX_GPO, MAX7360_MAX_KEY_COLS - columns); 46 46 + 47 47 + return 0; 48 48 + } 49 49 + 50 50 + static int max7360_gpo_init_valid_mask(struct gpio_chip *gc, 51 51 + unsigned long *valid_mask, 52 52 + unsigned int ngpios) 53 53 + { 54 54 + unsigned int available_gpios; 55 55 + int ret; 56 56 + 57 57 + ret = max7360_get_available_gpos(gc->parent, &available_gpios); 58 58 + if (ret) 59 59 + return ret; 60 60 + 61 61 + bitmap_clear(valid_mask, 0, MAX7360_MAX_KEY_COLS - available_gpios); 62 62 + 63 63 + return 0; 64 64 + } 65 65 + 66 66 + static int max7360_set_gpos_count(struct device *dev, struct regmap *regmap) 67 67 + { 68 68 + /* 69 69 + * MAX7360 COL0 to COL7 pins can be used either as keypad columns, 70 70 + * general purpose output or a mix of both. 71 71 + * By default, all pins are used as keypad, here we update this 72 72 + * configuration to allow to use some of them as GPIOs. 73 73 + */ 74 74 + unsigned int available_gpios; 75 75 + unsigned int val; 76 76 + int ret; 77 77 + 78 78 + ret = max7360_get_available_gpos(dev, &available_gpios); 79 79 + if (ret) 80 80 + return ret; 81 81 + 82 82 + /* 83 83 + * Configure which GPIOs will be used for keypad. 84 84 + * MAX7360_REG_DEBOUNCE contains configuration both for keypad debounce 85 85 + * timings and gpos/keypad columns repartition. Only the later is 86 86 + * modified here. 87 87 + */ 88 88 + val = FIELD_PREP(MAX7360_PORTS, available_gpios); 89 89 + ret = regmap_write_bits(regmap, MAX7360_REG_DEBOUNCE, MAX7360_PORTS, val); 90 90 + if (ret) 91 91 + dev_err(dev, "Failed to write max7360 columns/gpos configuration"); 92 92 + 93 93 + return ret; 94 94 + } 95 95 + 96 96 + static int max7360_gpio_reg_mask_xlate(struct gpio_regmap *gpio, 97 97 + unsigned int base, unsigned int offset, 98 98 + unsigned int *reg, unsigned int *mask) 99 99 + { 100 100 + if (base == MAX7360_REG_PWMBASE) { 101 101 + /* 102 102 + * GPIO output is using PWM duty cycle registers: one register 103 103 + * per line, with value being either 0 or 255. 104 104 + */ 105 105 + *reg = base + offset; 106 106 + *mask = GENMASK(7, 0); 107 107 + } else { 108 108 + *reg = base; 109 109 + *mask = BIT(offset); 110 110 + } 111 111 + 112 112 + return 0; 113 113 + } 114 114 + 115 115 + static const struct regmap_irq max7360_regmap_irqs[MAX7360_MAX_GPIO] = { 116 116 + REGMAP_IRQ_REG(0, 0, BIT(0)), 117 117 + REGMAP_IRQ_REG(1, 0, BIT(1)), 118 118 + REGMAP_IRQ_REG(2, 0, BIT(2)), 119 119 + REGMAP_IRQ_REG(3, 0, BIT(3)), 120 120 + REGMAP_IRQ_REG(4, 0, BIT(4)), 121 121 + REGMAP_IRQ_REG(5, 0, BIT(5)), 122 122 + REGMAP_IRQ_REG(6, 0, BIT(6)), 123 123 + REGMAP_IRQ_REG(7, 0, BIT(7)), 124 124 + }; 125 125 + 126 126 + static int max7360_handle_mask_sync(const int index, 127 127 + const unsigned int mask_buf_def, 128 128 + const unsigned int mask_buf, 129 129 + void *const irq_drv_data) 130 130 + { 131 131 + struct regmap *regmap = irq_drv_data; 132 132 + int ret; 133 133 + 134 134 + for (unsigned int i = 0; i < MAX7360_MAX_GPIO; i++) { 135 135 + ret = regmap_assign_bits(regmap, MAX7360_REG_PWMCFG(i), 136 136 + MAX7360_PORT_CFG_INTERRUPT_MASK, mask_buf & BIT(i)); 137 137 + if (ret) 138 138 + return ret; 139 139 + } 140 140 + 141 141 + return 0; 142 142 + } 143 143 + 144 144 + static int max7360_gpio_probe(struct platform_device *pdev) 145 145 + { 146 146 + const struct max7360_gpio_plat_data *plat_data; 147 147 + struct gpio_regmap_config gpio_config = { }; 148 148 + struct regmap_irq_chip *irq_chip; 149 149 + struct device *dev = &pdev->dev; 150 150 + struct regmap *regmap; 151 151 + unsigned int outconf; 152 152 + int ret; 153 153 + 154 154 + regmap = dev_get_regmap(dev->parent, NULL); 155 155 + if (!regmap) 156 156 + return dev_err_probe(dev, -ENODEV, "could not get parent regmap\n"); 157 157 + 158 158 + plat_data = device_get_match_data(dev); 159 159 + if (plat_data->function == MAX7360_GPIO_PORT) { 160 160 + if (device_property_read_bool(dev, "interrupt-controller")) { 161 161 + /* 162 162 + * Port GPIOs with interrupt-controller property: add IRQ 163 163 + * controller. 164 164 + */ 165 165 + gpio_config.regmap_irq_flags = IRQF_ONESHOT | IRQF_SHARED; 166 166 + gpio_config.regmap_irq_line = 167 167 + fwnode_irq_get_byname(dev_fwnode(dev->parent), "inti"); 168 168 + if (gpio_config.regmap_irq_line < 0) 169 169 + return dev_err_probe(dev, gpio_config.regmap_irq_line, 170 170 + "Failed to get IRQ\n"); 171 171 + 172 172 + /* Create custom IRQ configuration. */ 173 173 + irq_chip = devm_kzalloc(dev, sizeof(*irq_chip), GFP_KERNEL); 174 174 + gpio_config.regmap_irq_chip = irq_chip; 175 175 + if (!irq_chip) 176 176 + return -ENOMEM; 177 177 + 178 178 + irq_chip->name = dev_name(dev); 179 179 + irq_chip->status_base = MAX7360_REG_GPIOIN; 180 180 + irq_chip->status_is_level = true; 181 181 + irq_chip->num_regs = 1; 182 182 + irq_chip->num_irqs = MAX7360_MAX_GPIO; 183 183 + irq_chip->irqs = max7360_regmap_irqs; 184 184 + irq_chip->handle_mask_sync = max7360_handle_mask_sync; 185 185 + irq_chip->irq_drv_data = regmap; 186 186 + 187 187 + for (unsigned int i = 0; i < MAX7360_MAX_GPIO; i++) { 188 188 + ret = regmap_write_bits(regmap, MAX7360_REG_PWMCFG(i), 189 189 + MAX7360_PORT_CFG_INTERRUPT_EDGES, 190 190 + MAX7360_PORT_CFG_INTERRUPT_EDGES); 191 191 + if (ret) 192 192 + return dev_err_probe(dev, ret, 193 193 + "Failed to enable interrupts\n"); 194 194 + } 195 195 + } 196 196 + 197 197 + /* 198 198 + * Port GPIOs: set output mode configuration (constant-current or not). 199 199 + * This property is optional. 200 200 + */ 201 201 + ret = device_property_read_u32(dev, "maxim,constant-current-disable", &outconf); 202 202 + if (!ret) { 203 203 + ret = regmap_write(regmap, MAX7360_REG_GPIOOUTM, outconf); 204 204 + if (ret) 205 205 + return dev_err_probe(dev, ret, 206 206 + "Failed to set constant-current configuration\n"); 207 207 + } 208 208 + } 209 209 + 210 210 + /* Add gpio device. */ 211 211 + gpio_config.parent = dev; 212 212 + gpio_config.regmap = regmap; 213 213 + if (plat_data->function == MAX7360_GPIO_PORT) { 214 214 + gpio_config.ngpio = MAX7360_MAX_GPIO; 215 215 + gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(MAX7360_REG_GPIOIN); 216 216 + gpio_config.reg_set_base = GPIO_REGMAP_ADDR(MAX7360_REG_PWMBASE); 217 217 + gpio_config.reg_dir_out_base = GPIO_REGMAP_ADDR(MAX7360_REG_GPIOCTRL); 218 218 + gpio_config.ngpio_per_reg = MAX7360_MAX_GPIO; 219 219 + gpio_config.reg_mask_xlate = max7360_gpio_reg_mask_xlate; 220 220 + } else { 221 221 + ret = max7360_set_gpos_count(dev, regmap); 222 222 + if (ret) 223 223 + return dev_err_probe(dev, ret, "Failed to set GPOS pin count\n"); 224 224 + 225 225 + gpio_config.reg_set_base = GPIO_REGMAP_ADDR(MAX7360_REG_PORTS); 226 226 + gpio_config.ngpio = MAX7360_MAX_KEY_COLS; 227 227 + gpio_config.init_valid_mask = max7360_gpo_init_valid_mask; 228 228 + } 229 229 + 230 230 + return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); 231 231 + } 232 232 + 233 233 + static const struct of_device_id max7360_gpio_of_match[] = { 234 234 + { 235 235 + .compatible = "maxim,max7360-gpo", 236 236 + .data = &max7360_gpio_col_plat 237 237 + }, { 238 238 + .compatible = "maxim,max7360-gpio", 239 239 + .data = &max7360_gpio_port_plat 240 240 + }, { 241 241 + } 242 242 + }; 243 243 + MODULE_DEVICE_TABLE(of, max7360_gpio_of_match); 244 244 + 245 245 + static struct platform_driver max7360_gpio_driver = { 246 246 + .driver = { 247 247 + .name = "max7360-gpio", 248 248 + .of_match_table = max7360_gpio_of_match, 249 249 + }, 250 250 + .probe = max7360_gpio_probe, 251 251 + }; 252 252 + module_platform_driver(max7360_gpio_driver); 253 253 + 254 254 + MODULE_DESCRIPTION("MAX7360 GPIO driver"); 255 255 + MODULE_AUTHOR("Kamel BOUHARA <kamel.bouhara@bootlin.com>"); 256 256 + MODULE_AUTHOR("Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>"); 257 257 + MODULE_LICENSE("GPL");

+17 -14

drivers/gpio/gpio-menz127.c

reviewed

··· 12 12 #include <linux/mcb.h> 13 13 #include <linux/bitops.h> 14 14 #include <linux/gpio/driver.h> 15 15 + #include <linux/gpio/generic.h> 15 16 16 17 #define MEN_Z127_CTRL 0x00 17 18 #define MEN_Z127_PSR 0x04 ··· 31 30 (db <= MEN_Z127_DB_MAX_US)) 32 31 33 32 struct men_z127_gpio { 34 34 - struct gpio_chip gc; 33 33 + struct gpio_generic_chip chip; 35 34 void __iomem *reg_base; 36 35 struct resource *mem; 37 36 }; ··· 65 64 debounce /= 50; 66 65 } 67 66 68 68 - raw_spin_lock(&gc->bgpio_lock); 67 67 + guard(gpio_generic_lock)(&priv->chip); 69 68 70 69 db_en = readl(priv->reg_base + MEN_Z127_DBER); 71 70 ··· 80 79 writel(db_en, priv->reg_base + MEN_Z127_DBER); 81 80 writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio)); 82 81 83 83 - raw_spin_unlock(&gc->bgpio_lock); 84 84 - 85 82 return 0; 86 83 } 87 84 ··· 90 91 struct men_z127_gpio *priv = gpiochip_get_data(gc); 91 92 u32 od_en; 92 93 93 93 - raw_spin_lock(&gc->bgpio_lock); 94 94 + guard(gpio_generic_lock)(&priv->chip); 95 95 + 94 96 od_en = readl(priv->reg_base + MEN_Z127_ODER); 95 97 96 98 if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN) ··· 101 101 od_en &= ~BIT(offset); 102 102 103 103 writel(od_en, priv->reg_base + MEN_Z127_ODER); 104 104 - raw_spin_unlock(&gc->bgpio_lock); 105 104 106 105 return 0; 107 106 } ··· 136 137 static int men_z127_probe(struct mcb_device *mdev, 137 138 const struct mcb_device_id *id) 138 139 { 140 140 + struct gpio_generic_chip_config config; 139 141 struct men_z127_gpio *men_z127_gpio; 140 142 struct device *dev = &mdev->dev; 141 143 int ret; ··· 163 163 164 164 mcb_set_drvdata(mdev, men_z127_gpio); 165 165 166 166 - ret = bgpio_init(&men_z127_gpio->gc, &mdev->dev, 4, 167 167 - men_z127_gpio->reg_base + MEN_Z127_PSR, 168 168 - men_z127_gpio->reg_base + MEN_Z127_CTRL, 169 169 - NULL, 170 170 - men_z127_gpio->reg_base + MEN_Z127_GPIODR, 171 171 - NULL, 0); 166 166 + config = (struct gpio_generic_chip_config) { 167 167 + .dev = &mdev->dev, 168 168 + .sz = 4, 169 169 + .dat = men_z127_gpio->reg_base + MEN_Z127_PSR, 170 170 + .set = men_z127_gpio->reg_base + MEN_Z127_CTRL, 171 171 + .dirout = men_z127_gpio->reg_base + MEN_Z127_GPIODR, 172 172 + }; 173 173 + 174 174 + ret = gpio_generic_chip_init(&men_z127_gpio->chip, &config); 172 175 if (ret) 173 176 return ret; 174 177 175 175 - men_z127_gpio->gc.set_config = men_z127_set_config; 178 178 + men_z127_gpio->chip.gc.set_config = men_z127_set_config; 176 179 177 177 - ret = devm_gpiochip_add_data(dev, &men_z127_gpio->gc, men_z127_gpio); 180 180 + ret = devm_gpiochip_add_data(dev, &men_z127_gpio->chip.gc, men_z127_gpio); 178 181 if (ret) 179 182 return dev_err_probe(dev, ret, 180 183 "failed to register MEN 16Z127 GPIO controller");

+15 -10

drivers/gpio/gpio-mlxbf.c

reviewed

··· 4 4 #include <linux/bitops.h> 5 5 #include <linux/device.h> 6 6 #include <linux/gpio/driver.h> 7 7 + #include <linux/gpio/generic.h> 7 8 #include <linux/io.h> 8 9 #include <linux/kernel.h> 9 10 #include <linux/module.h> ··· 38 37 39 38 /* Device state structure. */ 40 39 struct mlxbf_gpio_state { 41 41 - struct gpio_chip gc; 40 40 + struct gpio_generic_chip chip; 42 41 43 42 /* Memory Address */ 44 43 void __iomem *base; ··· 50 49 51 50 static int mlxbf_gpio_probe(struct platform_device *pdev) 52 51 { 52 52 + struct gpio_generic_chip_config config; 53 53 struct mlxbf_gpio_state *gs; 54 54 struct device *dev = &pdev->dev; 55 55 struct gpio_chip *gc; ··· 64 62 if (IS_ERR(gs->base)) 65 63 return PTR_ERR(gs->base); 66 64 67 67 - gc = &gs->gc; 68 68 - ret = bgpio_init(gc, dev, 8, 69 69 - gs->base + MLXBF_GPIO_PIN_STATE, 70 70 - NULL, 71 71 - NULL, 72 72 - gs->base + MLXBF_GPIO_PIN_DIR_O, 73 73 - gs->base + MLXBF_GPIO_PIN_DIR_I, 74 74 - 0); 65 65 + gc = &gs->chip.gc; 66 66 + 67 67 + config = (struct gpio_generic_chip_config) { 68 68 + .dev = dev, 69 69 + .sz = 8, 70 70 + .dat = gs->base + MLXBF_GPIO_PIN_STATE, 71 71 + .dirout = gs->base + MLXBF_GPIO_PIN_DIR_O, 72 72 + .dirin = gs->base + MLXBF_GPIO_PIN_DIR_I, 73 73 + }; 74 74 + 75 75 + ret = gpio_generic_chip_init(&gs->chip, &config); 75 76 if (ret) 76 77 return -ENODEV; 77 78 78 79 gc->owner = THIS_MODULE; 79 80 gc->ngpio = MLXBF_GPIO_NR; 80 81 81 81 - ret = devm_gpiochip_add_data(dev, &gs->gc, gs); 82 82 + ret = devm_gpiochip_add_data(dev, &gs->chip.gc, gs); 82 83 if (ret) { 83 84 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n"); 84 85 return ret;

+37 -44

drivers/gpio/gpio-mlxbf2.c

reviewed

··· 6 6 7 7 #include <linux/bitfield.h> 8 8 #include <linux/bitops.h> 9 9 + #include <linux/cleanup.h> 9 10 #include <linux/device.h> 10 11 #include <linux/gpio/driver.h> 12 12 + #include <linux/gpio/generic.h> 11 13 #include <linux/interrupt.h> 12 14 #include <linux/io.h> 13 15 #include <linux/ioport.h> ··· 67 65 68 66 /* BlueField-2 gpio block context structure. */ 69 67 struct mlxbf2_gpio_context { 70 70 - struct gpio_chip gc; 68 68 + struct gpio_generic_chip chip; 71 69 72 70 /* YU GPIO blocks address */ 73 71 void __iomem *gpio_io; ··· 134 132 u32 arm_gpio_lock_val; 135 133 136 134 mutex_lock(yu_arm_gpio_lock_param.lock); 137 137 - raw_spin_lock(&gs->gc.bgpio_lock); 135 135 + gpio_generic_chip_lock(&gs->chip); 138 136 139 137 arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io); 140 138 ··· 142 140 * When lock active bit[31] is set, ModeX is write enabled 143 141 */ 144 142 if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) { 145 145 - raw_spin_unlock(&gs->gc.bgpio_lock); 143 143 + gpio_generic_chip_unlock(&gs->chip); 146 144 mutex_unlock(yu_arm_gpio_lock_param.lock); 147 145 return -EINVAL; 148 146 } ··· 156 154 * Release the YU arm_gpio_lock after changing the direction mode. 157 155 */ 158 156 static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs) 159 159 - __releases(&gs->gc.bgpio_lock) 157 157 + __releases(&gs->chip.lock) 160 158 __releases(yu_arm_gpio_lock_param.lock) 161 159 { 162 160 writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io); 163 163 - raw_spin_unlock(&gs->gc.bgpio_lock); 161 161 + gpio_generic_chip_unlock(&gs->chip); 164 162 mutex_unlock(yu_arm_gpio_lock_param.lock); 165 163 } 166 164 ··· 237 235 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 238 236 struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc); 239 237 int offset = irqd_to_hwirq(irqd); 240 240 - unsigned long flags; 241 238 u32 val; 242 239 243 240 gpiochip_enable_irq(gc, irqd_to_hwirq(irqd)); 244 244 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 241 241 + guard(gpio_generic_lock_irqsave)(&gs->chip); 245 242 val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); 246 243 val |= BIT(offset); 247 244 writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); ··· 248 247 val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 249 248 val |= BIT(offset); 250 249 writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 251 251 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 252 250 } 253 251 254 252 static void mlxbf2_gpio_irq_disable(struct irq_data *irqd) ··· 255 255 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 256 256 struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc); 257 257 int offset = irqd_to_hwirq(irqd); 258 258 - unsigned long flags; 259 258 u32 val; 260 259 261 261 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 262 262 - val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 263 263 - val &= ~BIT(offset); 264 264 - writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 265 265 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 260 260 + scoped_guard(gpio_generic_lock_irqsave, &gs->chip) { 261 261 + val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 262 262 + val &= ~BIT(offset); 263 263 + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 264 264 + } 265 265 + 266 266 gpiochip_disable_irq(gc, irqd_to_hwirq(irqd)); 267 267 } 268 268 269 269 static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr) 270 270 { 271 271 struct mlxbf2_gpio_context *gs = ptr; 272 272 - struct gpio_chip *gc = &gs->gc; 272 272 + struct gpio_chip *gc = &gs->chip.gc; 273 273 unsigned long pending; 274 274 u32 level; 275 275 ··· 288 288 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 289 289 struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc); 290 290 int offset = irqd_to_hwirq(irqd); 291 291 - unsigned long flags; 292 291 bool fall = false; 293 292 bool rise = false; 294 293 u32 val; ··· 307 308 return -EINVAL; 308 309 } 309 310 310 310 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 311 311 + guard(gpio_generic_lock_irqsave)(&gs->chip); 312 312 + 311 313 if (fall) { 312 314 val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN); 313 315 val |= BIT(offset); ··· 320 320 val |= BIT(offset); 321 321 writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN); 322 322 } 323 323 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 324 323 325 324 return 0; 326 325 } ··· 346 347 static int 347 348 mlxbf2_gpio_probe(struct platform_device *pdev) 348 349 { 350 350 + struct gpio_generic_chip_config config; 349 351 struct mlxbf2_gpio_context *gs; 350 352 struct device *dev = &pdev->dev; 351 353 struct gpio_irq_chip *girq; ··· 369 369 return PTR_ERR(gs->gpio_io); 370 370 371 371 ret = mlxbf2_gpio_get_lock_res(pdev); 372 372 - if (ret) { 373 373 - dev_err(dev, "Failed to get yu_arm_gpio_lock resource\n"); 374 374 - return ret; 375 375 - } 372 372 + if (ret) 373 373 + return dev_err_probe(dev, ret, "Failed to get yu_arm_gpio_lock resource\n"); 376 374 377 375 if (device_property_read_u32(dev, "npins", &npins)) 378 376 npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK; 379 377 380 380 - gc = &gs->gc; 378 378 + gc = &gs->chip.gc; 381 379 382 382 - ret = bgpio_init(gc, dev, 4, 383 383 - gs->gpio_io + YU_GPIO_DATAIN, 384 384 - gs->gpio_io + YU_GPIO_DATASET, 385 385 - gs->gpio_io + YU_GPIO_DATACLEAR, 386 386 - NULL, 387 387 - NULL, 388 388 - 0); 380 380 + config = (struct gpio_generic_chip_config) { 381 381 + .dev = dev, 382 382 + .sz = 4, 383 383 + .dat = gs->gpio_io + YU_GPIO_DATAIN, 384 384 + .set = gs->gpio_io + YU_GPIO_DATASET, 385 385 + .clr = gs->gpio_io + YU_GPIO_DATACLEAR, 386 386 + }; 389 387 390 390 - if (ret) { 391 391 - dev_err(dev, "bgpio_init failed\n"); 392 392 - return ret; 393 393 - } 388 388 + ret = gpio_generic_chip_init(&gs->chip, &config); 389 389 + if (ret) 390 390 + return dev_err_probe(dev, ret, "failed to initialize the generic GPIO chip\n"); 394 391 395 392 gc->direction_input = mlxbf2_gpio_direction_input; 396 393 gc->direction_output = mlxbf2_gpio_direction_output; ··· 396 399 397 400 irq = platform_get_irq_optional(pdev, 0); 398 401 if (irq >= 0) { 399 399 - girq = &gs->gc.irq; 402 402 + girq = &gs->chip.gc.irq; 400 403 gpio_irq_chip_set_chip(girq, &mlxbf2_gpio_irq_chip); 401 404 girq->handler = handle_simple_irq; 402 405 girq->default_type = IRQ_TYPE_NONE; ··· 411 414 */ 412 415 ret = devm_request_irq(dev, irq, mlxbf2_gpio_irq_handler, 413 416 IRQF_SHARED, name, gs); 414 414 - if (ret) { 415 415 - dev_err(dev, "failed to request IRQ"); 416 416 - return ret; 417 417 - } 417 417 + if (ret) 418 418 + return dev_err_probe(dev, ret, "failed to request IRQ"); 418 419 } 419 420 420 421 platform_set_drvdata(pdev, gs); 421 422 422 422 - ret = devm_gpiochip_add_data(dev, &gs->gc, gs); 423 423 - if (ret) { 424 424 - dev_err(dev, "Failed adding memory mapped gpiochip\n"); 425 425 - return ret; 426 426 - } 423 423 + ret = devm_gpiochip_add_data(dev, &gs->chip.gc, gs); 424 424 + if (ret) 425 425 + return dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n"); 427 426 428 427 return 0; 429 428 }

+52 -49

drivers/gpio/gpio-mlxbf3.c

reviewed

··· 6 6 #include <linux/device.h> 7 7 #include <linux/err.h> 8 8 #include <linux/gpio/driver.h> 9 9 + #include <linux/gpio/generic.h> 9 10 #include <linux/interrupt.h> 10 11 #include <linux/io.h> 11 12 #include <linux/module.h> ··· 43 42 #define MLXBF_GPIO_CLR_ALL_INTS GENMASK(31, 0) 44 43 45 44 struct mlxbf3_gpio_context { 46 46 - struct gpio_chip gc; 45 45 + struct gpio_generic_chip chip; 47 46 48 47 /* YU GPIO block address */ 49 48 void __iomem *gpio_set_io; ··· 59 58 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 60 59 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); 61 60 irq_hw_number_t offset = irqd_to_hwirq(irqd); 62 62 - unsigned long flags; 63 61 u32 val; 64 62 65 63 gpiochip_enable_irq(gc, offset); 66 64 67 67 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 65 65 + guard(gpio_generic_lock_irqsave)(&gs->chip); 66 66 + 68 67 writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); 69 68 70 69 val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); 71 70 val |= BIT(offset); 72 71 writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); 73 73 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 74 72 } 75 73 76 74 static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) ··· 77 77 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 78 78 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); 79 79 irq_hw_number_t offset = irqd_to_hwirq(irqd); 80 80 - unsigned long flags; 81 80 u32 val; 82 81 83 83 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 84 84 - val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); 85 85 - val &= ~BIT(offset); 86 86 - writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); 82 82 + scoped_guard(gpio_generic_lock_irqsave, &gs->chip) { 83 83 + val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); 84 84 + val &= ~BIT(offset); 85 85 + writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); 87 86 88 88 - writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); 89 89 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 87 87 + writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); 88 88 + } 90 89 91 90 gpiochip_disable_irq(gc, offset); 92 91 } ··· 93 94 static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr) 94 95 { 95 96 struct mlxbf3_gpio_context *gs = ptr; 96 96 - struct gpio_chip *gc = &gs->gc; 97 97 + struct gpio_chip *gc = &gs->chip.gc; 97 98 unsigned long pending; 98 99 u32 level; 99 100 ··· 112 113 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 113 114 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); 114 115 irq_hw_number_t offset = irqd_to_hwirq(irqd); 115 115 - unsigned long flags; 116 116 u32 val; 117 117 118 118 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 119 119 - 120 120 - switch (type & IRQ_TYPE_SENSE_MASK) { 121 121 - case IRQ_TYPE_EDGE_BOTH: 122 122 - val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); 123 123 - val |= BIT(offset); 124 124 - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); 125 125 - val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); 126 126 - val |= BIT(offset); 127 127 - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); 128 128 - break; 129 129 - case IRQ_TYPE_EDGE_RISING: 130 130 - val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); 131 131 - val |= BIT(offset); 132 132 - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); 133 133 - break; 134 134 - case IRQ_TYPE_EDGE_FALLING: 135 135 - val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); 136 136 - val |= BIT(offset); 137 137 - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); 138 138 - break; 139 139 - default: 140 140 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 141 141 - return -EINVAL; 118 118 + scoped_guard(gpio_generic_lock_irqsave, &gs->chip) { 119 119 + switch (type & IRQ_TYPE_SENSE_MASK) { 120 120 + case IRQ_TYPE_EDGE_BOTH: 121 121 + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); 122 122 + val |= BIT(offset); 123 123 + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); 124 124 + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); 125 125 + val |= BIT(offset); 126 126 + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); 127 127 + break; 128 128 + case IRQ_TYPE_EDGE_RISING: 129 129 + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); 130 130 + val |= BIT(offset); 131 131 + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); 132 132 + break; 133 133 + case IRQ_TYPE_EDGE_FALLING: 134 134 + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); 135 135 + val |= BIT(offset); 136 136 + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); 137 137 + break; 138 138 + default: 139 139 + return -EINVAL; 140 140 + } 142 141 } 143 143 - 144 144 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 145 142 146 143 irq_set_handler_locked(irqd, handle_edge_irq); 147 144 ··· 181 186 182 187 static int mlxbf3_gpio_probe(struct platform_device *pdev) 183 188 { 189 189 + struct gpio_generic_chip_config config; 184 190 struct device *dev = &pdev->dev; 185 191 struct mlxbf3_gpio_context *gs; 186 192 struct gpio_irq_chip *girq; ··· 207 211 gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3); 208 212 if (IS_ERR(gs->gpio_clr_io)) 209 213 return PTR_ERR(gs->gpio_clr_io); 210 210 - gc = &gs->gc; 214 214 + gc = &gs->chip.gc; 211 215 212 212 - ret = bgpio_init(gc, dev, 4, 213 213 - gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, 214 214 - gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET, 215 215 - gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, 216 216 - gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, 217 217 - gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0); 216 216 + config = (struct gpio_generic_chip_config) { 217 217 + .dev = dev, 218 218 + .sz = 4, 219 219 + .dat = gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, 220 220 + .set = gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET, 221 221 + .clr = gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, 222 222 + .dirout = gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, 223 223 + .dirin = gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 224 224 + }; 225 225 + 226 226 + ret = gpio_generic_chip_init(&gs->chip, &config); 218 227 if (ret) 219 219 - return dev_err_probe(dev, ret, "%s: bgpio_init() failed", __func__); 228 228 + return dev_err_probe(dev, ret, 229 229 + "%s: failed to initialize the generic GPIO chip", 230 230 + __func__); 220 231 221 232 gc->request = gpiochip_generic_request; 222 233 gc->free = gpiochip_generic_free; ··· 232 229 233 230 irq = platform_get_irq_optional(pdev, 0); 234 231 if (irq >= 0) { 235 235 - girq = &gs->gc.irq; 232 232 + girq = &gs->chip.gc.irq; 236 233 gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip); 237 234 girq->default_type = IRQ_TYPE_NONE; 238 235 /* This will let us handle the parent IRQ in the driver */ ··· 253 250 254 251 platform_set_drvdata(pdev, gs); 255 252 256 256 - ret = devm_gpiochip_add_data(dev, &gs->gc, gs); 253 253 + ret = devm_gpiochip_add_data(dev, gc, gs); 257 254 if (ret) 258 255 dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n"); 259 256

+190 -173

drivers/gpio/gpio-mmio.c

reviewed

··· 57 57 #include <linux/types.h> 58 58 59 59 #include <linux/gpio/driver.h> 60 60 + #include <linux/gpio/generic.h> 60 61 61 62 #include "gpiolib.h" 62 63 ··· 125 124 126 125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) 127 126 { 128 128 - if (gc->be_bits) 129 129 - return BIT(gc->bgpio_bits - 1 - line); 127 127 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 128 128 + 129 129 + if (chip->be_bits) 130 130 + return BIT(chip->bits - 1 - line); 130 131 return BIT(line); 131 132 } 132 133 133 134 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) 134 135 { 136 136 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 135 137 unsigned long pinmask = bgpio_line2mask(gc, gpio); 136 136 - bool dir = !!(gc->bgpio_dir & pinmask); 138 138 + bool dir = !!(chip->sdir & pinmask); 137 139 138 140 if (dir) 139 139 - return !!(gc->read_reg(gc->reg_set) & pinmask); 140 140 - else 141 141 - return !!(gc->read_reg(gc->reg_dat) & pinmask); 141 141 + return !!(chip->read_reg(chip->reg_set) & pinmask); 142 142 + 143 143 + return !!(chip->read_reg(chip->reg_dat) & pinmask); 142 144 } 143 145 144 146 /* ··· 151 147 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 152 148 unsigned long *bits) 153 149 { 154 154 - unsigned long get_mask = 0; 155 155 - unsigned long set_mask = 0; 150 150 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 151 151 + unsigned long get_mask = 0, set_mask = 0; 156 152 157 153 /* Make sure we first clear any bits that are zero when we read the register */ 158 154 *bits &= ~*mask; 159 155 160 160 - set_mask = *mask & gc->bgpio_dir; 161 161 - get_mask = *mask & ~gc->bgpio_dir; 156 156 + set_mask = *mask & chip->sdir; 157 157 + get_mask = *mask & ~chip->sdir; 162 158 163 159 if (set_mask) 164 164 - *bits |= gc->read_reg(gc->reg_set) & set_mask; 160 160 + *bits |= chip->read_reg(chip->reg_set) & set_mask; 165 161 if (get_mask) 166 166 - *bits |= gc->read_reg(gc->reg_dat) & get_mask; 162 162 + *bits |= chip->read_reg(chip->reg_dat) & get_mask; 167 163 168 164 return 0; 169 165 } 170 166 171 167 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) 172 168 { 173 173 - return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); 169 169 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 170 170 + 171 171 + return !!(chip->read_reg(chip->reg_dat) & bgpio_line2mask(gc, gpio)); 174 172 } 175 173 176 174 /* ··· 181 175 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 182 176 unsigned long *bits) 183 177 { 178 178 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 179 179 + 184 180 /* Make sure we first clear any bits that are zero when we read the register */ 185 181 *bits &= ~*mask; 186 186 - *bits |= gc->read_reg(gc->reg_dat) & *mask; 182 182 + *bits |= chip->read_reg(chip->reg_dat) & *mask; 187 183 return 0; 188 184 } 189 185 ··· 195 187 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 196 188 unsigned long *bits) 197 189 { 190 190 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 198 191 unsigned long readmask = 0; 199 192 unsigned long val; 200 193 int bit; ··· 208 199 readmask |= bgpio_line2mask(gc, bit); 209 200 210 201 /* Read the register */ 211 211 - val = gc->read_reg(gc->reg_dat) & readmask; 202 202 + val = chip->read_reg(chip->reg_dat) & readmask; 212 203 213 204 /* 214 205 * Mirror the result into the "bits" result, this will give line 0 ··· 227 218 228 219 static int bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 229 220 { 221 221 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 230 222 unsigned long mask = bgpio_line2mask(gc, gpio); 231 223 unsigned long flags; 232 224 233 233 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 225 225 + raw_spin_lock_irqsave(&chip->lock, flags); 234 226 235 227 if (val) 236 236 - gc->bgpio_data |= mask; 228 228 + chip->sdata |= mask; 237 229 else 238 238 - gc->bgpio_data &= ~mask; 230 230 + chip->sdata &= ~mask; 239 231 240 240 - gc->write_reg(gc->reg_dat, gc->bgpio_data); 232 232 + chip->write_reg(chip->reg_dat, chip->sdata); 241 233 242 242 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 234 234 + raw_spin_unlock_irqrestore(&chip->lock, flags); 243 235 244 236 return 0; 245 237 } ··· 248 238 static int bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 249 239 int val) 250 240 { 241 241 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 251 242 unsigned long mask = bgpio_line2mask(gc, gpio); 252 243 253 244 if (val) 254 254 - gc->write_reg(gc->reg_set, mask); 245 245 + chip->write_reg(chip->reg_set, mask); 255 246 else 256 256 - gc->write_reg(gc->reg_clr, mask); 247 247 + chip->write_reg(chip->reg_clr, mask); 257 248 258 249 return 0; 259 250 } 260 251 261 252 static int bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 262 253 { 263 263 - unsigned long mask = bgpio_line2mask(gc, gpio); 264 264 - unsigned long flags; 254 254 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 255 255 + unsigned long mask = bgpio_line2mask(gc, gpio), flags; 265 256 266 266 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 257 257 + raw_spin_lock_irqsave(&chip->lock, flags); 267 258 268 259 if (val) 269 269 - gc->bgpio_data |= mask; 260 260 + chip->sdata |= mask; 270 261 else 271 271 - gc->bgpio_data &= ~mask; 262 262 + chip->sdata &= ~mask; 272 263 273 273 - gc->write_reg(gc->reg_set, gc->bgpio_data); 264 264 + chip->write_reg(chip->reg_set, chip->sdata); 274 265 275 275 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 266 266 + raw_spin_unlock_irqrestore(&chip->lock, flags); 276 267 277 268 return 0; 278 269 } ··· 283 272 unsigned long *set_mask, 284 273 unsigned long *clear_mask) 285 274 { 275 275 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 286 276 int i; 287 277 288 278 *set_mask = 0; 289 279 *clear_mask = 0; 290 280 291 291 - for_each_set_bit(i, mask, gc->bgpio_bits) { 281 281 + for_each_set_bit(i, mask, chip->bits) { 292 282 if (test_bit(i, bits)) 293 283 *set_mask |= bgpio_line2mask(gc, i); 294 284 else ··· 302 290 unsigned long *bits, 303 291 void __iomem *reg) 304 292 { 305 305 - unsigned long flags; 306 306 - unsigned long set_mask, clear_mask; 293 293 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 294 294 + unsigned long flags, set_mask, clear_mask; 307 295 308 308 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 296 296 + raw_spin_lock_irqsave(&chip->lock, flags); 309 297 310 298 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 311 299 312 312 - gc->bgpio_data |= set_mask; 313 313 - gc->bgpio_data &= ~clear_mask; 300 300 + chip->sdata |= set_mask; 301 301 + chip->sdata &= ~clear_mask; 314 302 315 315 - gc->write_reg(reg, gc->bgpio_data); 303 303 + chip->write_reg(reg, chip->sdata); 316 304 317 317 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 305 305 + raw_spin_unlock_irqrestore(&chip->lock, flags); 318 306 } 319 307 320 308 static int bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 321 309 unsigned long *bits) 322 310 { 323 323 - bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); 311 311 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 312 312 + 313 313 + bgpio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat); 324 314 325 315 return 0; 326 316 } ··· 330 316 static int bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 331 317 unsigned long *bits) 332 318 { 333 333 - bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); 319 319 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 320 320 + 321 321 + bgpio_set_multiple_single_reg(gc, mask, bits, chip->reg_set); 334 322 335 323 return 0; 336 324 } ··· 341 325 unsigned long *mask, 342 326 unsigned long *bits) 343 327 { 328 328 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 344 329 unsigned long set_mask, clear_mask; 345 330 346 331 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 347 332 348 333 if (set_mask) 349 349 - gc->write_reg(gc->reg_set, set_mask); 334 334 + chip->write_reg(chip->reg_set, set_mask); 350 335 if (clear_mask) 351 351 - gc->write_reg(gc->reg_clr, clear_mask); 336 336 + chip->write_reg(chip->reg_clr, clear_mask); 352 337 353 338 return 0; 354 339 } 355 340 356 341 static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool dir_out) 357 342 { 358 358 - if (!gc->bgpio_pinctrl) 343 343 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 344 344 + 345 345 + if (!chip->pinctrl) 359 346 return 0; 360 347 361 348 if (dir_out) ··· 393 374 394 375 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 395 376 { 377 377 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 396 378 unsigned long flags; 397 379 398 398 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 380 380 + raw_spin_lock_irqsave(&chip->lock, flags); 399 381 400 400 - gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 382 382 + chip->sdir &= ~bgpio_line2mask(gc, gpio); 401 383 402 402 - if (gc->reg_dir_in) 403 403 - gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 404 404 - if (gc->reg_dir_out) 405 405 - gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 384 384 + if (chip->reg_dir_in) 385 385 + chip->write_reg(chip->reg_dir_in, ~chip->sdir); 386 386 + if (chip->reg_dir_out) 387 387 + chip->write_reg(chip->reg_dir_out, chip->sdir); 406 388 407 407 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 389 389 + raw_spin_unlock_irqrestore(&chip->lock, flags); 408 390 409 391 return bgpio_dir_return(gc, gpio, false); 410 392 } 411 393 412 394 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) 413 395 { 396 396 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 397 397 + 414 398 /* Return 0 if output, 1 if input */ 415 415 - if (gc->bgpio_dir_unreadable) { 416 416 - if (gc->bgpio_dir & bgpio_line2mask(gc, gpio)) 399 399 + if (chip->dir_unreadable) { 400 400 + if (chip->sdir & bgpio_line2mask(gc, gpio)) 417 401 return GPIO_LINE_DIRECTION_OUT; 418 402 return GPIO_LINE_DIRECTION_IN; 419 403 } 420 404 421 421 - if (gc->reg_dir_out) { 422 422 - if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio)) 405 405 + if (chip->reg_dir_out) { 406 406 + if (chip->read_reg(chip->reg_dir_out) & bgpio_line2mask(gc, gpio)) 423 407 return GPIO_LINE_DIRECTION_OUT; 424 408 return GPIO_LINE_DIRECTION_IN; 425 409 } 426 410 427 427 - if (gc->reg_dir_in) 428 428 - if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio))) 411 411 + if (chip->reg_dir_in) 412 412 + if (!(chip->read_reg(chip->reg_dir_in) & bgpio_line2mask(gc, gpio))) 429 413 return GPIO_LINE_DIRECTION_OUT; 430 414 431 415 return GPIO_LINE_DIRECTION_IN; ··· 436 414 437 415 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 438 416 { 417 417 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 439 418 unsigned long flags; 440 419 441 441 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 420 420 + raw_spin_lock_irqsave(&chip->lock, flags); 442 421 443 443 - gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 422 422 + chip->sdir |= bgpio_line2mask(gc, gpio); 444 423 445 445 - if (gc->reg_dir_in) 446 446 - gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 447 447 - if (gc->reg_dir_out) 448 448 - gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 424 424 + if (chip->reg_dir_in) 425 425 + chip->write_reg(chip->reg_dir_in, ~chip->sdir); 426 426 + if (chip->reg_dir_out) 427 427 + chip->write_reg(chip->reg_dir_out, chip->sdir); 449 428 450 450 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 429 429 + raw_spin_unlock_irqrestore(&chip->lock, flags); 451 430 } 452 431 453 432 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, ··· 468 445 } 469 446 470 447 static int bgpio_setup_accessors(struct device *dev, 471 471 - struct gpio_chip *gc, 448 448 + struct gpio_generic_chip *chip, 472 449 bool byte_be) 473 450 { 474 474 - 475 475 - switch (gc->bgpio_bits) { 451 451 + switch (chip->bits) { 476 452 case 8: 477 477 - gc->read_reg = bgpio_read8; 478 478 - gc->write_reg = bgpio_write8; 453 453 + chip->read_reg = bgpio_read8; 454 454 + chip->write_reg = bgpio_write8; 479 455 break; 480 456 case 16: 481 457 if (byte_be) { 482 482 - gc->read_reg = bgpio_read16be; 483 483 - gc->write_reg = bgpio_write16be; 458 458 + chip->read_reg = bgpio_read16be; 459 459 + chip->write_reg = bgpio_write16be; 484 460 } else { 485 485 - gc->read_reg = bgpio_read16; 486 486 - gc->write_reg = bgpio_write16; 461 461 + chip->read_reg = bgpio_read16; 462 462 + chip->write_reg = bgpio_write16; 487 463 } 488 464 break; 489 465 case 32: 490 466 if (byte_be) { 491 491 - gc->read_reg = bgpio_read32be; 492 492 - gc->write_reg = bgpio_write32be; 467 467 + chip->read_reg = bgpio_read32be; 468 468 + chip->write_reg = bgpio_write32be; 493 469 } else { 494 494 - gc->read_reg = bgpio_read32; 495 495 - gc->write_reg = bgpio_write32; 470 470 + chip->read_reg = bgpio_read32; 471 471 + chip->write_reg = bgpio_write32; 496 472 } 497 473 break; 498 474 #if BITS_PER_LONG >= 64 ··· 501 479 "64 bit big endian byte order unsupported\n"); 502 480 return -EINVAL; 503 481 } else { 504 504 - gc->read_reg = bgpio_read64; 505 505 - gc->write_reg = bgpio_write64; 482 482 + chip->read_reg = bgpio_read64; 483 483 + chip->write_reg = bgpio_write64; 506 484 } 507 485 break; 508 486 #endif /* BITS_PER_LONG >= 64 */ 509 487 default: 510 510 - dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); 488 488 + dev_err(dev, "unsupported data width %u bits\n", chip->bits); 511 489 return -EINVAL; 512 490 } 513 491 ··· 536 514 * - an input direction register (named "dirin") where a 1 bit indicates 537 515 * the GPIO is an input. 538 516 */ 539 539 - static int bgpio_setup_io(struct gpio_chip *gc, 540 540 - void __iomem *dat, 541 541 - void __iomem *set, 542 542 - void __iomem *clr, 543 543 - unsigned long flags) 517 517 + static int bgpio_setup_io(struct gpio_generic_chip *chip, 518 518 + const struct gpio_generic_chip_config *cfg) 544 519 { 520 520 + struct gpio_chip *gc = &chip->gc; 545 521 546 546 - gc->reg_dat = dat; 547 547 - if (!gc->reg_dat) 522 522 + chip->reg_dat = cfg->dat; 523 523 + if (!chip->reg_dat) 548 524 return -EINVAL; 549 525 550 550 - if (set && clr) { 551 551 - gc->reg_set = set; 552 552 - gc->reg_clr = clr; 526 526 + if (cfg->set && cfg->clr) { 527 527 + chip->reg_set = cfg->set; 528 528 + chip->reg_clr = cfg->clr; 553 529 gc->set = bgpio_set_with_clear; 554 530 gc->set_multiple = bgpio_set_multiple_with_clear; 555 555 - } else if (set && !clr) { 556 556 - gc->reg_set = set; 531 531 + } else if (cfg->set && !cfg->clr) { 532 532 + chip->reg_set = cfg->set; 557 533 gc->set = bgpio_set_set; 558 534 gc->set_multiple = bgpio_set_multiple_set; 559 559 - } else if (flags & BGPIOF_NO_OUTPUT) { 535 535 + } else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) { 560 536 gc->set = bgpio_set_none; 561 537 gc->set_multiple = NULL; 562 538 } else { ··· 562 542 gc->set_multiple = bgpio_set_multiple; 563 543 } 564 544 565 565 - if (!(flags & BGPIOF_UNREADABLE_REG_SET) && 566 566 - (flags & BGPIOF_READ_OUTPUT_REG_SET)) { 545 545 + if (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) && 546 546 + (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) { 567 547 gc->get = bgpio_get_set; 568 568 - if (!gc->be_bits) 548 548 + if (!chip->be_bits) 569 549 gc->get_multiple = bgpio_get_set_multiple; 570 550 /* 571 551 * We deliberately avoid assigning the ->get_multiple() call ··· 576 556 */ 577 557 } else { 578 558 gc->get = bgpio_get; 579 579 - if (gc->be_bits) 559 559 + if (chip->be_bits) 580 560 gc->get_multiple = bgpio_get_multiple_be; 581 561 else 582 562 gc->get_multiple = bgpio_get_multiple; ··· 585 565 return 0; 586 566 } 587 567 588 588 - static int bgpio_setup_direction(struct gpio_chip *gc, 589 589 - void __iomem *dirout, 590 590 - void __iomem *dirin, 591 591 - unsigned long flags) 568 568 + static int bgpio_setup_direction(struct gpio_generic_chip *chip, 569 569 + const struct gpio_generic_chip_config *cfg) 592 570 { 593 593 - if (dirout || dirin) { 594 594 - gc->reg_dir_out = dirout; 595 595 - gc->reg_dir_in = dirin; 596 596 - if (flags & BGPIOF_NO_SET_ON_INPUT) 571 571 + struct gpio_chip *gc = &chip->gc; 572 572 + 573 573 + if (cfg->dirout || cfg->dirin) { 574 574 + chip->reg_dir_out = cfg->dirout; 575 575 + chip->reg_dir_in = cfg->dirin; 576 576 + if (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT) 597 577 gc->direction_output = bgpio_dir_out_dir_first; 598 578 else 599 579 gc->direction_output = bgpio_dir_out_val_first; 600 580 gc->direction_input = bgpio_dir_in; 601 581 gc->get_direction = bgpio_get_dir; 602 582 } else { 603 603 - if (flags & BGPIOF_NO_OUTPUT) 583 583 + if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) 604 584 gc->direction_output = bgpio_dir_out_err; 605 585 else 606 586 gc->direction_output = bgpio_simple_dir_out; 607 587 608 608 - if (flags & BGPIOF_NO_INPUT) 588 588 + if (cfg->flags & GPIO_GENERIC_NO_INPUT) 609 589 gc->direction_input = bgpio_dir_in_err; 610 590 else 611 591 gc->direction_input = bgpio_simple_dir_in; ··· 614 594 return 0; 615 595 } 616 596 617 617 - static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) 597 597 + static int bgpio_request(struct gpio_chip *gc, unsigned int gpio_pin) 618 598 { 619 619 - if (gpio_pin >= chip->ngpio) 599 599 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 600 600 + 601 601 + if (gpio_pin >= gc->ngpio) 620 602 return -EINVAL; 621 603 622 622 - if (chip->bgpio_pinctrl) 623 623 - return gpiochip_generic_request(chip, gpio_pin); 604 604 + if (chip->pinctrl) 605 605 + return gpiochip_generic_request(gc, gpio_pin); 624 606 625 607 return 0; 626 608 } 627 609 628 610 /** 629 629 - * bgpio_init() - Initialize generic GPIO accessor functions 630 630 - * @gc: the GPIO chip to set up 631 631 - * @dev: the parent device of the new GPIO chip (compulsory) 632 632 - * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4 633 633 - * @dat: MMIO address for the register to READ the value of the GPIO lines, it 634 634 - * is expected that a 1 in the corresponding bit in this register means the 635 635 - * line is asserted 636 636 - * @set: MMIO address for the register to SET the value of the GPIO lines, it is 637 637 - * expected that we write the line with 1 in this register to drive the GPIO line 638 638 - * high. 639 639 - * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is 640 640 - * expected that we write the line with 1 in this register to drive the GPIO line 641 641 - * low. It is allowed to leave this address as NULL, in that case the SET register 642 642 - * will be assumed to also clear the GPIO lines, by actively writing the line 643 643 - * with 0. 644 644 - * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed 645 645 - * that setting a line to 1 in this register will turn that line into an 646 646 - * output line. Conversely, setting the line to 0 will turn that line into 647 647 - * an input. 648 648 - * @dirin: MMIO address for the register to set this line as INPUT. It is assumed 649 649 - * that setting a line to 1 in this register will turn that line into an 650 650 - * input line. Conversely, setting the line to 0 will turn that line into 651 651 - * an output. 652 652 - * @flags: Different flags that will affect the behaviour of the device, such as 653 653 - * endianness etc. 611 611 + * gpio_generic_chip_init() - Initialize a generic GPIO chip. 612 612 + * @chip: Generic GPIO chip to set up. 613 613 + * @cfg: Generic GPIO chip configuration. 614 614 + * 615 615 + * Returns 0 on success, negative error number on failure. 654 616 */ 655 655 - int bgpio_init(struct gpio_chip *gc, struct device *dev, 656 656 - unsigned long sz, void __iomem *dat, void __iomem *set, 657 657 - void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 658 658 - unsigned long flags) 617 617 + int gpio_generic_chip_init(struct gpio_generic_chip *chip, 618 618 + const struct gpio_generic_chip_config *cfg) 659 619 { 620 620 + struct gpio_chip *gc = &chip->gc; 621 621 + unsigned long flags = cfg->flags; 622 622 + struct device *dev = cfg->dev; 660 623 int ret; 661 624 662 662 - if (!is_power_of_2(sz)) 625 625 + if (!is_power_of_2(cfg->sz)) 663 626 return -EINVAL; 664 627 665 665 - gc->bgpio_bits = sz * 8; 666 666 - if (gc->bgpio_bits > BITS_PER_LONG) 628 628 + chip->bits = cfg->sz * 8; 629 629 + if (chip->bits > BITS_PER_LONG) 667 630 return -EINVAL; 668 631 669 669 - raw_spin_lock_init(&gc->bgpio_lock); 632 632 + raw_spin_lock_init(&chip->lock); 670 633 gc->parent = dev; 671 634 gc->label = dev_name(dev); 672 635 gc->base = -1; 673 636 gc->request = bgpio_request; 674 674 - gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); 637 637 + chip->be_bits = !!(flags & GPIO_GENERIC_BIG_ENDIAN); 675 638 676 639 ret = gpiochip_get_ngpios(gc, dev); 677 640 if (ret) 678 678 - gc->ngpio = gc->bgpio_bits; 641 641 + gc->ngpio = chip->bits; 679 642 680 680 - ret = bgpio_setup_io(gc, dat, set, clr, flags); 643 643 + ret = bgpio_setup_io(chip, cfg); 681 644 if (ret) 682 645 return ret; 683 646 684 684 - ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); 647 647 + ret = bgpio_setup_accessors(dev, chip, 648 648 + flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); 685 649 if (ret) 686 650 return ret; 687 651 688 688 - ret = bgpio_setup_direction(gc, dirout, dirin, flags); 652 652 + ret = bgpio_setup_direction(chip, cfg); 689 653 if (ret) 690 654 return ret; 691 655 692 692 - if (flags & BGPIOF_PINCTRL_BACKEND) { 693 693 - gc->bgpio_pinctrl = true; 656 656 + if (flags & GPIO_GENERIC_PINCTRL_BACKEND) { 657 657 + chip->pinctrl = true; 694 658 /* Currently this callback is only used for pincontrol */ 695 659 gc->free = gpiochip_generic_free; 696 660 } 697 661 698 698 - gc->bgpio_data = gc->read_reg(gc->reg_dat); 662 662 + chip->sdata = chip->read_reg(chip->reg_dat); 699 663 if (gc->set == bgpio_set_set && 700 700 - !(flags & BGPIOF_UNREADABLE_REG_SET)) 701 701 - gc->bgpio_data = gc->read_reg(gc->reg_set); 664 664 + !(flags & GPIO_GENERIC_UNREADABLE_REG_SET)) 665 665 + chip->sdata = chip->read_reg(chip->reg_set); 702 666 703 703 - if (flags & BGPIOF_UNREADABLE_REG_DIR) 704 704 - gc->bgpio_dir_unreadable = true; 667 667 + if (flags & GPIO_GENERIC_UNREADABLE_REG_DIR) 668 668 + chip->dir_unreadable = true; 705 669 706 670 /* 707 671 * Inspect hardware to find initial direction setting. 708 672 */ 709 709 - if ((gc->reg_dir_out || gc->reg_dir_in) && 710 710 - !(flags & BGPIOF_UNREADABLE_REG_DIR)) { 711 711 - if (gc->reg_dir_out) 712 712 - gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); 713 713 - else if (gc->reg_dir_in) 714 714 - gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); 673 673 + if ((chip->reg_dir_out || chip->reg_dir_in) && 674 674 + !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) { 675 675 + if (chip->reg_dir_out) 676 676 + chip->sdir = chip->read_reg(chip->reg_dir_out); 677 677 + else if (chip->reg_dir_in) 678 678 + chip->sdir = ~chip->read_reg(chip->reg_dir_in); 715 679 /* 716 680 * If we have two direction registers, synchronise 717 681 * input setting to output setting, the library 718 682 * can not handle a line being input and output at 719 683 * the same time. 720 684 */ 721 721 - if (gc->reg_dir_out && gc->reg_dir_in) 722 722 - gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 685 685 + if (chip->reg_dir_out && chip->reg_dir_in) 686 686 + chip->write_reg(chip->reg_dir_in, ~chip->sdir); 723 687 } 724 688 725 689 return ret; 726 690 } 727 727 - EXPORT_SYMBOL_GPL(bgpio_init); 691 691 + EXPORT_SYMBOL_GPL(gpio_generic_chip_init); 728 692 729 693 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 730 694 ··· 734 730 { .compatible = "brcm,bcm6345-gpio" }, 735 731 { .compatible = "wd,mbl-gpio" }, 736 732 { .compatible = "ni,169445-nand-gpio" }, 733 733 + { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" }, 737 734 { } 738 735 }; 739 736 MODULE_DEVICE_TABLE(of, bgpio_of_match); 740 737 741 738 static int bgpio_pdev_probe(struct platform_device *pdev) 742 739 { 740 740 + struct gpio_generic_chip_config config; 741 741 + struct gpio_generic_chip *gen_gc; 743 742 struct device *dev = &pdev->dev; 744 743 struct resource *r; 745 744 void __iomem *dat; ··· 754 747 unsigned long flags = 0; 755 748 unsigned int base; 756 749 int err; 757 757 - struct gpio_chip *gc; 758 750 const char *label; 759 751 760 752 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); ··· 782 776 if (IS_ERR(dirin)) 783 777 return PTR_ERR(dirin); 784 778 785 785 - gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 786 786 - if (!gc) 779 779 + gen_gc = devm_kzalloc(&pdev->dev, sizeof(*gen_gc), GFP_KERNEL); 780 780 + if (!gen_gc) 787 781 return -ENOMEM; 788 782 789 783 if (device_is_big_endian(dev)) 790 790 - flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; 784 784 + flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 791 785 792 786 if (device_property_read_bool(dev, "no-output")) 793 793 - flags |= BGPIOF_NO_OUTPUT; 787 787 + flags |= GPIO_GENERIC_NO_OUTPUT; 794 788 795 795 - err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); 789 789 + config = (struct gpio_generic_chip_config) { 790 790 + .dev = dev, 791 791 + .sz = sz, 792 792 + .dat = dat, 793 793 + .set = set, 794 794 + .clr = clr, 795 795 + .dirout = dirout, 796 796 + .dirin = dirin, 797 797 + .flags = flags, 798 798 + }; 799 799 + 800 800 + err = gpio_generic_chip_init(gen_gc, &config); 796 801 if (err) 797 802 return err; 798 803 799 804 err = device_property_read_string(dev, "label", &label); 800 805 if (!err) 801 801 - gc->label = label; 806 806 + gen_gc->gc.label = label; 802 807 803 808 /* 804 809 * This property *must not* be used in device-tree sources, it's only ··· 817 800 */ 818 801 err = device_property_read_u32(dev, "gpio-mmio,base", &base); 819 802 if (!err && base <= INT_MAX) 820 820 - gc->base = base; 803 803 + gen_gc->gc.base = base; 821 804 822 822 - platform_set_drvdata(pdev, gc); 805 805 + platform_set_drvdata(pdev, &gen_gc->gc); 823 806 824 824 - return devm_gpiochip_add_data(&pdev->dev, gc, NULL); 807 807 + return devm_gpiochip_add_data(&pdev->dev, &gen_gc->gc, NULL); 825 808 } 826 809 827 810 static const struct platform_device_id bgpio_id_table[] = {

+64 -41

drivers/gpio/gpio-mpc8xxx.c

reviewed

··· 9 9 #include <linux/acpi.h> 10 10 #include <linux/bitops.h> 11 11 #include <linux/gpio/driver.h> 12 12 + #include <linux/gpio/generic.h> 12 13 #include <linux/init.h> 13 14 #include <linux/interrupt.h> 14 15 #include <linux/io.h> ··· 35 34 #define GPIO_IBE 0x18 36 35 37 36 struct mpc8xxx_gpio_chip { 38 38 - struct gpio_chip gc; 37 37 + struct gpio_generic_chip chip; 39 38 void __iomem *regs; 40 39 raw_spinlock_t lock; 41 40 ··· 67 66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 68 67 u32 out_mask, out_shadow; 69 68 70 70 - out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 71 71 - val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; 72 72 - out_shadow = gc->bgpio_data & out_mask; 69 69 + out_mask = gpio_generic_read_reg(&mpc8xxx_gc->chip, 70 70 + mpc8xxx_gc->regs + GPIO_DIR); 71 71 + val = gpio_generic_read_reg(&mpc8xxx_gc->chip, 72 72 + mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; 73 73 + out_shadow = mpc8xxx_gc->chip.sdata & out_mask; 73 74 74 75 return !!((val | out_shadow) & mpc_pin2mask(gpio)); 75 76 } ··· 111 108 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) 112 109 { 113 110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data; 114 114 - struct gpio_chip *gc = &mpc8xxx_gc->gc; 115 111 unsigned long mask; 116 112 int i; 117 113 118 118 - mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) 119 119 - & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); 114 114 + mask = gpio_generic_read_reg(&mpc8xxx_gc->chip, 115 115 + mpc8xxx_gc->regs + GPIO_IER) & 116 116 + gpio_generic_read_reg(&mpc8xxx_gc->chip, 117 117 + mpc8xxx_gc->regs + GPIO_IMR); 120 118 for_each_set_bit(i, &mask, 32) 121 119 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); 122 120 ··· 128 124 { 129 125 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 130 126 irq_hw_number_t hwirq = irqd_to_hwirq(d); 131 131 - struct gpio_chip *gc = &mpc8xxx_gc->gc; 127 127 + struct gpio_chip *gc = &mpc8xxx_gc->chip.gc; 132 128 unsigned long flags; 133 129 134 130 gpiochip_enable_irq(gc, hwirq); 135 131 136 132 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 137 133 138 138 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 139 139 - gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 134 134 + gpio_generic_write_reg(&mpc8xxx_gc->chip, 135 135 + mpc8xxx_gc->regs + GPIO_IMR, 136 136 + gpio_generic_read_reg(&mpc8xxx_gc->chip, 137 137 + mpc8xxx_gc->regs + GPIO_IMR) 140 138 | mpc_pin2mask(irqd_to_hwirq(d))); 141 139 142 140 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); ··· 148 142 { 149 143 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 150 144 irq_hw_number_t hwirq = irqd_to_hwirq(d); 151 151 - struct gpio_chip *gc = &mpc8xxx_gc->gc; 145 145 + struct gpio_chip *gc = &mpc8xxx_gc->chip.gc; 152 146 unsigned long flags; 153 147 154 148 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 155 149 156 156 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 157 157 - gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 150 150 + gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IMR, 151 151 + gpio_generic_read_reg(&mpc8xxx_gc->chip, 152 152 + mpc8xxx_gc->regs + GPIO_IMR) 158 153 & ~mpc_pin2mask(irqd_to_hwirq(d))); 159 154 160 155 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); ··· 166 159 static void mpc8xxx_irq_ack(struct irq_data *d) 167 160 { 168 161 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 169 169 - struct gpio_chip *gc = &mpc8xxx_gc->gc; 170 162 171 171 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 163 163 + gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IER, 172 164 mpc_pin2mask(irqd_to_hwirq(d))); 173 165 } 174 166 175 167 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) 176 168 { 177 169 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 178 178 - struct gpio_chip *gc = &mpc8xxx_gc->gc; 179 170 unsigned long flags; 180 171 181 172 switch (flow_type) { 182 173 case IRQ_TYPE_EDGE_FALLING: 183 174 case IRQ_TYPE_LEVEL_LOW: 184 175 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 185 185 - gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 186 186 - gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 176 176 + gpio_generic_write_reg(&mpc8xxx_gc->chip, 177 177 + mpc8xxx_gc->regs + GPIO_ICR, 178 178 + gpio_generic_read_reg(&mpc8xxx_gc->chip, 179 179 + mpc8xxx_gc->regs + GPIO_ICR) 187 180 | mpc_pin2mask(irqd_to_hwirq(d))); 188 181 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 189 182 break; 190 183 191 184 case IRQ_TYPE_EDGE_BOTH: 192 185 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 193 193 - gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 194 194 - gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 186 186 + gpio_generic_write_reg(&mpc8xxx_gc->chip, 187 187 + mpc8xxx_gc->regs + GPIO_ICR, 188 188 + gpio_generic_read_reg(&mpc8xxx_gc->chip, 189 189 + mpc8xxx_gc->regs + GPIO_ICR) 195 190 & ~mpc_pin2mask(irqd_to_hwirq(d))); 196 191 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 197 192 break; ··· 208 199 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) 209 200 { 210 201 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 211 211 - struct gpio_chip *gc = &mpc8xxx_gc->gc; 212 202 unsigned long gpio = irqd_to_hwirq(d); 213 203 void __iomem *reg; 214 204 unsigned int shift; ··· 225 217 case IRQ_TYPE_EDGE_FALLING: 226 218 case IRQ_TYPE_LEVEL_LOW: 227 219 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 228 228 - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 220 220 + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, 221 221 + (gpio_generic_read_reg(&mpc8xxx_gc->chip, 222 222 + reg) & ~(3 << shift)) 229 223 | (2 << shift)); 230 224 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 231 225 break; ··· 235 225 case IRQ_TYPE_EDGE_RISING: 236 226 case IRQ_TYPE_LEVEL_HIGH: 237 227 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 238 238 - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 228 228 + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, 229 229 + (gpio_generic_read_reg(&mpc8xxx_gc->chip, 230 230 + reg) & ~(3 << shift)) 239 231 | (1 << shift)); 240 232 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 241 233 break; 242 234 243 235 case IRQ_TYPE_EDGE_BOTH: 244 236 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 245 245 - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); 237 237 + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, 238 238 + (gpio_generic_read_reg(&mpc8xxx_gc->chip, 239 239 + reg) & ~(3 << shift))); 246 240 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 247 241 break; 248 242 ··· 323 309 static int mpc8xxx_probe(struct platform_device *pdev) 324 310 { 325 311 const struct mpc8xxx_gpio_devtype *devtype = NULL; 312 312 + struct gpio_generic_chip_config config; 326 313 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 327 314 struct device *dev = &pdev->dev; 328 315 struct fwnode_handle *fwnode; ··· 342 327 if (IS_ERR(mpc8xxx_gc->regs)) 343 328 return PTR_ERR(mpc8xxx_gc->regs); 344 329 345 345 - gc = &mpc8xxx_gc->gc; 330 330 + gc = &mpc8xxx_gc->chip.gc; 346 331 gc->parent = dev; 347 332 333 333 + config = (struct gpio_generic_chip_config) { 334 334 + .dev = dev, 335 335 + .sz = 4, 336 336 + .dat = mpc8xxx_gc->regs + GPIO_DAT, 337 337 + .dirout = mpc8xxx_gc->regs + GPIO_DIR, 338 338 + .flags = GPIO_GENERIC_BIG_ENDIAN 339 339 + }; 340 340 + 348 341 if (device_property_read_bool(dev, "little-endian")) { 349 349 - ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, 350 350 - NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, 351 351 - NULL, BGPIOF_BIG_ENDIAN); 352 352 - if (ret) 353 353 - return ret; 354 342 dev_dbg(dev, "GPIO registers are LITTLE endian\n"); 355 343 } else { 356 356 - ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, 357 357 - NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, 358 358 - NULL, BGPIOF_BIG_ENDIAN 359 359 - | BGPIOF_BIG_ENDIAN_BYTE_ORDER); 360 360 - if (ret) 361 361 - return ret; 344 344 + config.flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 362 345 dev_dbg(dev, "GPIO registers are BIG endian\n"); 363 346 } 347 347 + 348 348 + ret = gpio_generic_chip_init(&mpc8xxx_gc->chip, &config); 349 349 + if (ret) 350 350 + return ret; 364 351 365 352 mpc8xxx_gc->direction_output = gc->direction_output; 366 353 ··· 396 379 device_is_compatible(dev, "fsl,ls1028a-gpio") || 397 380 device_is_compatible(dev, "fsl,ls1088a-gpio") || 398 381 is_acpi_node(fwnode)) { 399 399 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); 382 382 + gpio_generic_write_reg(&mpc8xxx_gc->chip, 383 383 + mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); 400 384 /* Also, latch state of GPIOs configured as output by bootloader. */ 401 401 - gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & 402 402 - gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 385 385 + mpc8xxx_gc->chip.sdata = 386 386 + gpio_generic_read_reg(&mpc8xxx_gc->chip, 387 387 + mpc8xxx_gc->regs + GPIO_DAT) & 388 388 + gpio_generic_read_reg(&mpc8xxx_gc->chip, 389 389 + mpc8xxx_gc->regs + GPIO_DIR); 403 390 } 404 391 405 392 ret = devm_gpiochip_add_data(dev, gc, mpc8xxx_gc); ··· 426 405 return 0; 427 406 428 407 /* ack and mask all irqs */ 429 429 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); 430 430 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); 408 408 + gpio_generic_write_reg(&mpc8xxx_gc->chip, 409 409 + mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); 410 410 + gpio_generic_write_reg(&mpc8xxx_gc->chip, 411 411 + mpc8xxx_gc->regs + GPIO_IMR, 0); 431 412 432 413 ret = devm_request_irq(dev, mpc8xxx_gc->irqn, 433 414 mpc8xxx_gpio_irq_cascade,

+1 -1

drivers/gpio/gpio-mpfs.c

reviewed

··· 69 69 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 70 70 71 71 regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), 72 72 - MPFS_GPIO_DIR_MASK, MPFS_GPIO_EN_IN); 72 72 + MPFS_GPIO_DIR_MASK, MPFS_GPIO_EN_OUT | MPFS_GPIO_EN_OUT_BUF); 73 73 regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index), 74 74 value << gpio_index); 75 75

+44 -36

drivers/gpio/gpio-mt7621.c

reviewed

··· 6 6 7 7 #include <linux/err.h> 8 8 #include <linux/gpio/driver.h> 9 9 + #include <linux/gpio/generic.h> 9 10 #include <linux/interrupt.h> 10 11 #include <linux/io.h> 11 12 #include <linux/module.h> 12 13 #include <linux/platform_device.h> 13 13 - #include <linux/spinlock.h> 14 14 15 15 #define MTK_BANK_CNT 3 16 16 #define MTK_BANK_WIDTH 32 ··· 30 30 31 31 struct mtk_gc { 32 32 struct irq_chip irq_chip; 33 33 - struct gpio_chip chip; 34 34 - spinlock_t lock; 33 33 + struct gpio_generic_chip chip; 35 34 int bank; 36 35 u32 rising; 37 36 u32 falling; ··· 58 59 static inline struct mtk_gc * 59 60 to_mediatek_gpio(struct gpio_chip *chip) 60 61 { 61 61 - return container_of(chip, struct mtk_gc, chip); 62 62 + struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(chip); 63 63 + 64 64 + return container_of(gen_gc, struct mtk_gc, chip); 62 65 } 63 66 64 67 static inline void 65 68 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) 66 69 { 67 67 - struct gpio_chip *gc = &rg->chip; 70 70 + struct gpio_chip *gc = &rg->chip.gc; 68 71 struct mtk *mtk = gpiochip_get_data(gc); 69 72 70 73 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; 71 71 - gc->write_reg(mtk->base + offset, val); 74 74 + gpio_generic_write_reg(&rg->chip, mtk->base + offset, val); 72 75 } 73 76 74 77 static inline u32 75 78 mtk_gpio_r32(struct mtk_gc *rg, u32 offset) 76 79 { 77 77 - struct gpio_chip *gc = &rg->chip; 80 80 + struct gpio_chip *gc = &rg->chip.gc; 78 81 struct mtk *mtk = gpiochip_get_data(gc); 79 82 80 83 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; 81 81 - return gc->read_reg(mtk->base + offset); 84 84 + return gpio_generic_read_reg(&rg->chip, mtk->base + offset); 82 85 } 83 86 84 87 static irqreturn_t ··· 109 108 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 110 109 struct mtk_gc *rg = to_mediatek_gpio(gc); 111 110 int pin = d->hwirq; 112 112 - unsigned long flags; 113 111 u32 rise, fall, high, low; 114 112 115 113 gpiochip_enable_irq(gc, d->hwirq); 116 114 117 117 - spin_lock_irqsave(&rg->lock, flags); 115 115 + guard(gpio_generic_lock_irqsave)(&rg->chip); 116 116 + 118 117 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 119 118 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 120 119 high = mtk_gpio_r32(rg, GPIO_REG_HLVL); ··· 123 122 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling)); 124 123 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel)); 125 124 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel)); 126 126 - spin_unlock_irqrestore(&rg->lock, flags); 127 125 } 128 126 129 127 static void ··· 131 131 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 132 132 struct mtk_gc *rg = to_mediatek_gpio(gc); 133 133 int pin = d->hwirq; 134 134 - unsigned long flags; 135 134 u32 rise, fall, high, low; 136 135 137 137 - spin_lock_irqsave(&rg->lock, flags); 138 138 - rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 139 139 - fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 140 140 - high = mtk_gpio_r32(rg, GPIO_REG_HLVL); 141 141 - low = mtk_gpio_r32(rg, GPIO_REG_LLVL); 142 142 - mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); 143 143 - mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); 144 144 - mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); 145 145 - mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); 146 146 - spin_unlock_irqrestore(&rg->lock, flags); 136 136 + scoped_guard(gpio_generic_lock_irqsave, &rg->chip) { 137 137 + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 138 138 + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 139 139 + high = mtk_gpio_r32(rg, GPIO_REG_HLVL); 140 140 + low = mtk_gpio_r32(rg, GPIO_REG_LLVL); 141 141 + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); 142 142 + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); 143 143 + mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); 144 144 + mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); 145 145 + } 147 146 148 147 gpiochip_disable_irq(gc, d->hwirq); 149 148 } ··· 219 220 static int 220 221 mediatek_gpio_bank_probe(struct device *dev, int bank) 221 222 { 223 223 + struct gpio_generic_chip_config config; 222 224 struct mtk *mtk = dev_get_drvdata(dev); 223 225 struct mtk_gc *rg; 224 226 void __iomem *dat, *set, *ctrl, *diro; ··· 228 228 rg = &mtk->gc_map[bank]; 229 229 memset(rg, 0, sizeof(*rg)); 230 230 231 231 - spin_lock_init(&rg->lock); 232 231 rg->bank = bank; 233 232 234 233 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); ··· 235 236 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); 236 237 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); 237 238 238 238 - ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL, 239 239 - BGPIOF_NO_SET_ON_INPUT); 239 239 + config = (struct gpio_generic_chip_config) { 240 240 + .dev = dev, 241 241 + .sz = 4, 242 242 + .dat = dat, 243 243 + .set = set, 244 244 + .clr = ctrl, 245 245 + .dirout = diro, 246 246 + .flags = GPIO_GENERIC_NO_SET_ON_INPUT, 247 247 + }; 248 248 + 249 249 + ret = gpio_generic_chip_init(&rg->chip, &config); 240 250 if (ret) { 241 241 - dev_err(dev, "bgpio_init() failed\n"); 251 251 + dev_err(dev, "failed to initialize generic GPIO chip\n"); 242 252 return ret; 243 253 } 244 254 245 245 - rg->chip.of_gpio_n_cells = 2; 246 246 - rg->chip.of_xlate = mediatek_gpio_xlate; 247 247 - rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", 255 255 + rg->chip.gc.of_gpio_n_cells = 2; 256 256 + rg->chip.gc.of_xlate = mediatek_gpio_xlate; 257 257 + rg->chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", 248 258 dev_name(dev), bank); 249 249 - if (!rg->chip.label) 259 259 + if (!rg->chip.gc.label) 250 260 return -ENOMEM; 251 261 252 252 - rg->chip.offset = bank * MTK_BANK_WIDTH; 262 262 + rg->chip.gc.offset = bank * MTK_BANK_WIDTH; 253 263 254 264 if (mtk->gpio_irq) { 255 265 struct gpio_irq_chip *girq; ··· 269 261 */ 270 262 ret = devm_request_irq(dev, mtk->gpio_irq, 271 263 mediatek_gpio_irq_handler, IRQF_SHARED, 272 272 - rg->chip.label, &rg->chip); 264 264 + rg->chip.gc.label, &rg->chip.gc); 273 265 274 266 if (ret) { 275 267 dev_err(dev, "Error requesting IRQ %d: %d\n", ··· 277 269 return ret; 278 270 } 279 271 280 280 - girq = &rg->chip.irq; 272 272 + girq = &rg->chip.gc.irq; 281 273 gpio_irq_chip_set_chip(girq, &mt7621_irq_chip); 282 274 /* This will let us handle the parent IRQ in the driver */ 283 275 girq->parent_handler = NULL; ··· 287 279 girq->handler = handle_simple_irq; 288 280 } 289 281 290 290 - ret = devm_gpiochip_add_data(dev, &rg->chip, mtk); 282 282 + ret = devm_gpiochip_add_data(dev, &rg->chip.gc, mtk); 291 283 if (ret < 0) { 292 284 dev_err(dev, "Could not register gpio %d, ret=%d\n", 293 293 - rg->chip.ngpio, ret); 285 285 + rg->chip.gc.ngpio, ret); 294 286 return ret; 295 287 } 296 288 297 289 /* set polarity to low for all gpios */ 298 290 mtk_gpio_w32(rg, GPIO_REG_POL, 0); 299 291 300 300 - dev_info(dev, "registering %d gpios\n", rg->chip.ngpio); 292 292 + dev_info(dev, "registering %d gpios\n", rg->chip.gc.ngpio); 301 293 302 294 return 0; 303 295 }

+1 -2

drivers/gpio/gpio-mvebu.c

reviewed

··· 602 602 .reg_bits = 32, 603 603 .reg_stride = 4, 604 604 .val_bits = 32, 605 605 - .fast_io = true, 606 605 }; 607 606 608 607 /* ··· 898 899 msk = BIT(i); 899 900 is_out = !(io_conf & msk); 900 901 901 901 - seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 902 902 + seq_printf(s, " gpio-%-3d (%-20.20s)", i, label); 902 903 903 904 if (is_out) { 904 905 seq_printf(s, " out %s %s\n",

+1 -1

drivers/gpio/gpio-mxc.c

reviewed

··· 481 481 config.dat = port->base + GPIO_PSR; 482 482 config.set = port->base + GPIO_DR; 483 483 config.dirout = port->base + GPIO_GDIR; 484 484 - config.flags = BGPIOF_READ_OUTPUT_REG_SET; 484 484 + config.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET; 485 485 486 486 err = gpio_generic_chip_init(&port->gen_gc, &config); 487 487 if (err)

+19 -12

drivers/gpio/gpio-mxs.c

reviewed

··· 7 7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 8 8 9 9 #include <linux/err.h> 10 10 + #include <linux/gpio/driver.h> 11 11 + #include <linux/gpio/generic.h> 10 12 #include <linux/init.h> 11 13 #include <linux/interrupt.h> 12 14 #include <linux/io.h> 13 15 #include <linux/irq.h> 14 16 #include <linux/irqdomain.h> 17 17 + #include <linux/module.h> 15 18 #include <linux/of.h> 16 19 #include <linux/of_address.h> 17 20 #include <linux/platform_device.h> 18 21 #include <linux/slab.h> 19 19 - #include <linux/gpio/driver.h> 20 20 - #include <linux/module.h> 21 22 22 23 #define MXS_SET 0x4 23 24 #define MXS_CLR 0x8 ··· 49 48 int id; 50 49 int irq; 51 50 struct irq_domain *domain; 52 52 - struct gpio_chip gc; 51 51 + struct gpio_generic_chip chip; 53 52 struct device *dev; 54 53 enum mxs_gpio_id devid; 55 54 u32 both_edges; ··· 259 258 static int mxs_gpio_probe(struct platform_device *pdev) 260 259 { 261 260 struct device_node *np = pdev->dev.of_node; 261 261 + struct gpio_generic_chip_config config; 262 262 struct device_node *parent; 263 263 static void __iomem *base; 264 264 struct mxs_gpio_port *port; ··· 321 319 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler, 322 320 port); 323 321 324 324 - err = bgpio_init(&port->gc, &pdev->dev, 4, 325 325 - port->base + PINCTRL_DIN(port), 326 326 - port->base + PINCTRL_DOUT(port) + MXS_SET, 327 327 - port->base + PINCTRL_DOUT(port) + MXS_CLR, 328 328 - port->base + PINCTRL_DOE(port), NULL, 0); 322 322 + config = (struct gpio_generic_chip_config) { 323 323 + .dev = &pdev->dev, 324 324 + .sz = 4, 325 325 + .dat = port->base + PINCTRL_DIN(port), 326 326 + .set = port->base + PINCTRL_DOUT(port) + MXS_SET, 327 327 + .clr = port->base + PINCTRL_DOUT(port) + MXS_CLR, 328 328 + .dirout = port->base + PINCTRL_DOE(port), 329 329 + }; 330 330 + 331 331 + err = gpio_generic_chip_init(&port->chip, &config); 329 332 if (err) 330 333 goto out_irqdomain_remove; 331 334 332 332 - port->gc.to_irq = mxs_gpio_to_irq; 333 333 - port->gc.get_direction = mxs_gpio_get_direction; 334 334 - port->gc.base = port->id * 32; 335 335 + port->chip.gc.to_irq = mxs_gpio_to_irq; 336 336 + port->chip.gc.get_direction = mxs_gpio_get_direction; 337 337 + port->chip.gc.base = port->id * 32; 335 338 336 336 - err = gpiochip_add_data(&port->gc, port); 339 339 + err = gpiochip_add_data(&port->chip.gc, port); 337 340 if (err) 338 341 goto out_irqdomain_remove; 339 342

+499

drivers/gpio/gpio-nct6694.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Nuvoton NCT6694 GPIO controller driver based on USB interface. 4 4 + * 5 5 + * Copyright (C) 2025 Nuvoton Technology Corp. 6 6 + */ 7 7 + 8 8 + #include <linux/bits.h> 9 9 + #include <linux/gpio/driver.h> 10 10 + #include <linux/idr.h> 11 11 + #include <linux/interrupt.h> 12 12 + #include <linux/mfd/nct6694.h> 13 13 + #include <linux/module.h> 14 14 + #include <linux/platform_device.h> 15 15 + 16 16 + /* 17 17 + * USB command module type for NCT6694 GPIO controller. 18 18 + * This defines the module type used for communication with the NCT6694 19 19 + * GPIO controller over the USB interface. 20 20 + */ 21 21 + #define NCT6694_GPIO_MOD 0xFF 22 22 + 23 23 + #define NCT6694_GPIO_VER 0x90 24 24 + #define NCT6694_GPIO_VALID 0x110 25 25 + #define NCT6694_GPI_DATA 0x120 26 26 + #define NCT6694_GPO_DIR 0x170 27 27 + #define NCT6694_GPO_TYPE 0x180 28 28 + #define NCT6694_GPO_DATA 0x190 29 29 + 30 30 + #define NCT6694_GPI_STS 0x130 31 31 + #define NCT6694_GPI_CLR 0x140 32 32 + #define NCT6694_GPI_FALLING 0x150 33 33 + #define NCT6694_GPI_RISING 0x160 34 34 + 35 35 + #define NCT6694_NR_GPIO 8 36 36 + 37 37 + struct nct6694_gpio_data { 38 38 + struct nct6694 *nct6694; 39 39 + struct gpio_chip gpio; 40 40 + struct mutex lock; 41 41 + /* Protect irq operation */ 42 42 + struct mutex irq_lock; 43 43 + 44 44 + unsigned char reg_val; 45 45 + unsigned char irq_trig_falling; 46 46 + unsigned char irq_trig_rising; 47 47 + 48 48 + /* Current gpio group */ 49 49 + unsigned char group; 50 50 + int irq; 51 51 + }; 52 52 + 53 53 + static int nct6694_get_direction(struct gpio_chip *gpio, unsigned int offset) 54 54 + { 55 55 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 56 56 + const struct nct6694_cmd_header cmd_hd = { 57 57 + .mod = NCT6694_GPIO_MOD, 58 58 + .offset = cpu_to_le16(NCT6694_GPO_DIR + data->group), 59 59 + .len = cpu_to_le16(sizeof(data->reg_val)) 60 60 + }; 61 61 + int ret; 62 62 + 63 63 + guard(mutex)(&data->lock); 64 64 + 65 65 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 66 66 + if (ret < 0) 67 67 + return ret; 68 68 + 69 69 + return !(BIT(offset) & data->reg_val); 70 70 + } 71 71 + 72 72 + static int nct6694_direction_input(struct gpio_chip *gpio, unsigned int offset) 73 73 + { 74 74 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 75 75 + const struct nct6694_cmd_header cmd_hd = { 76 76 + .mod = NCT6694_GPIO_MOD, 77 77 + .offset = cpu_to_le16(NCT6694_GPO_DIR + data->group), 78 78 + .len = cpu_to_le16(sizeof(data->reg_val)) 79 79 + }; 80 80 + int ret; 81 81 + 82 82 + guard(mutex)(&data->lock); 83 83 + 84 84 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 85 85 + if (ret < 0) 86 86 + return ret; 87 87 + 88 88 + data->reg_val &= ~BIT(offset); 89 89 + 90 90 + return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); 91 91 + } 92 92 + 93 93 + static int nct6694_direction_output(struct gpio_chip *gpio, 94 94 + unsigned int offset, int val) 95 95 + { 96 96 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 97 97 + struct nct6694_cmd_header cmd_hd = { 98 98 + .mod = NCT6694_GPIO_MOD, 99 99 + .offset = cpu_to_le16(NCT6694_GPO_DIR + data->group), 100 100 + .len = cpu_to_le16(sizeof(data->reg_val)) 101 101 + }; 102 102 + int ret; 103 103 + 104 104 + guard(mutex)(&data->lock); 105 105 + 106 106 + /* Set direction to output */ 107 107 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 108 108 + if (ret < 0) 109 109 + return ret; 110 110 + 111 111 + data->reg_val |= BIT(offset); 112 112 + ret = nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); 113 113 + if (ret < 0) 114 114 + return ret; 115 115 + 116 116 + /* Then set output level */ 117 117 + cmd_hd.offset = cpu_to_le16(NCT6694_GPO_DATA + data->group); 118 118 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 119 119 + if (ret < 0) 120 120 + return ret; 121 121 + 122 122 + if (val) 123 123 + data->reg_val |= BIT(offset); 124 124 + else 125 125 + data->reg_val &= ~BIT(offset); 126 126 + 127 127 + return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); 128 128 + } 129 129 + 130 130 + static int nct6694_get_value(struct gpio_chip *gpio, unsigned int offset) 131 131 + { 132 132 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 133 133 + struct nct6694_cmd_header cmd_hd = { 134 134 + .mod = NCT6694_GPIO_MOD, 135 135 + .offset = cpu_to_le16(NCT6694_GPO_DIR + data->group), 136 136 + .len = cpu_to_le16(sizeof(data->reg_val)) 137 137 + }; 138 138 + int ret; 139 139 + 140 140 + guard(mutex)(&data->lock); 141 141 + 142 142 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 143 143 + if (ret < 0) 144 144 + return ret; 145 145 + 146 146 + if (BIT(offset) & data->reg_val) { 147 147 + cmd_hd.offset = cpu_to_le16(NCT6694_GPO_DATA + data->group); 148 148 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 149 149 + if (ret < 0) 150 150 + return ret; 151 151 + 152 152 + return !!(BIT(offset) & data->reg_val); 153 153 + } 154 154 + 155 155 + cmd_hd.offset = cpu_to_le16(NCT6694_GPI_DATA + data->group); 156 156 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 157 157 + if (ret < 0) 158 158 + return ret; 159 159 + 160 160 + return !!(BIT(offset) & data->reg_val); 161 161 + } 162 162 + 163 163 + static int nct6694_set_value(struct gpio_chip *gpio, unsigned int offset, 164 164 + int val) 165 165 + { 166 166 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 167 167 + const struct nct6694_cmd_header cmd_hd = { 168 168 + .mod = NCT6694_GPIO_MOD, 169 169 + .offset = cpu_to_le16(NCT6694_GPO_DATA + data->group), 170 170 + .len = cpu_to_le16(sizeof(data->reg_val)) 171 171 + }; 172 172 + int ret; 173 173 + 174 174 + guard(mutex)(&data->lock); 175 175 + 176 176 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 177 177 + if (ret < 0) 178 178 + return ret; 179 179 + 180 180 + if (val) 181 181 + data->reg_val |= BIT(offset); 182 182 + else 183 183 + data->reg_val &= ~BIT(offset); 184 184 + 185 185 + return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); 186 186 + } 187 187 + 188 188 + static int nct6694_set_config(struct gpio_chip *gpio, unsigned int offset, 189 189 + unsigned long config) 190 190 + { 191 191 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 192 192 + const struct nct6694_cmd_header cmd_hd = { 193 193 + .mod = NCT6694_GPIO_MOD, 194 194 + .offset = cpu_to_le16(NCT6694_GPO_TYPE + data->group), 195 195 + .len = cpu_to_le16(sizeof(data->reg_val)) 196 196 + }; 197 197 + int ret; 198 198 + 199 199 + guard(mutex)(&data->lock); 200 200 + 201 201 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 202 202 + if (ret < 0) 203 203 + return ret; 204 204 + 205 205 + switch (pinconf_to_config_param(config)) { 206 206 + case PIN_CONFIG_DRIVE_OPEN_DRAIN: 207 207 + data->reg_val |= BIT(offset); 208 208 + break; 209 209 + case PIN_CONFIG_DRIVE_PUSH_PULL: 210 210 + data->reg_val &= ~BIT(offset); 211 211 + break; 212 212 + default: 213 213 + return -ENOTSUPP; 214 214 + } 215 215 + 216 216 + return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); 217 217 + } 218 218 + 219 219 + static int nct6694_init_valid_mask(struct gpio_chip *gpio, 220 220 + unsigned long *valid_mask, 221 221 + unsigned int ngpios) 222 222 + { 223 223 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 224 224 + const struct nct6694_cmd_header cmd_hd = { 225 225 + .mod = NCT6694_GPIO_MOD, 226 226 + .offset = cpu_to_le16(NCT6694_GPIO_VALID + data->group), 227 227 + .len = cpu_to_le16(sizeof(data->reg_val)) 228 228 + }; 229 229 + int ret; 230 230 + 231 231 + guard(mutex)(&data->lock); 232 232 + 233 233 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 234 234 + if (ret < 0) 235 235 + return ret; 236 236 + 237 237 + *valid_mask = data->reg_val; 238 238 + 239 239 + return ret; 240 240 + } 241 241 + 242 242 + static irqreturn_t nct6694_irq_handler(int irq, void *priv) 243 243 + { 244 244 + struct nct6694_gpio_data *data = priv; 245 245 + struct nct6694_cmd_header cmd_hd = { 246 246 + .mod = NCT6694_GPIO_MOD, 247 247 + .offset = cpu_to_le16(NCT6694_GPI_STS + data->group), 248 248 + .len = cpu_to_le16(sizeof(data->reg_val)) 249 249 + }; 250 250 + unsigned char status; 251 251 + int ret; 252 252 + 253 253 + guard(mutex)(&data->lock); 254 254 + 255 255 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); 256 256 + if (ret) 257 257 + return IRQ_NONE; 258 258 + 259 259 + status = data->reg_val; 260 260 + 261 261 + while (status) { 262 262 + int bit = __ffs(status); 263 263 + 264 264 + data->reg_val = BIT(bit); 265 265 + handle_nested_irq(irq_find_mapping(data->gpio.irq.domain, bit)); 266 266 + status &= ~BIT(bit); 267 267 + cmd_hd.offset = cpu_to_le16(NCT6694_GPI_CLR + data->group); 268 268 + nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); 269 269 + } 270 270 + 271 271 + return IRQ_HANDLED; 272 272 + } 273 273 + 274 274 + static int nct6694_get_irq_trig(struct nct6694_gpio_data *data) 275 275 + { 276 276 + struct nct6694_cmd_header cmd_hd = { 277 277 + .mod = NCT6694_GPIO_MOD, 278 278 + .offset = cpu_to_le16(NCT6694_GPI_FALLING + data->group), 279 279 + .len = cpu_to_le16(sizeof(data->reg_val)) 280 280 + }; 281 281 + int ret; 282 282 + 283 283 + guard(mutex)(&data->lock); 284 284 + 285 285 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->irq_trig_falling); 286 286 + if (ret) 287 287 + return ret; 288 288 + 289 289 + cmd_hd.offset = cpu_to_le16(NCT6694_GPI_RISING + data->group); 290 290 + return nct6694_read_msg(data->nct6694, &cmd_hd, &data->irq_trig_rising); 291 291 + } 292 292 + 293 293 + static void nct6694_irq_mask(struct irq_data *d) 294 294 + { 295 295 + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); 296 296 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 297 297 + 298 298 + gpiochip_disable_irq(gpio, hwirq); 299 299 + } 300 300 + 301 301 + static void nct6694_irq_unmask(struct irq_data *d) 302 302 + { 303 303 + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); 304 304 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 305 305 + 306 306 + gpiochip_enable_irq(gpio, hwirq); 307 307 + } 308 308 + 309 309 + static int nct6694_irq_set_type(struct irq_data *d, unsigned int type) 310 310 + { 311 311 + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); 312 312 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 313 313 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 314 314 + 315 315 + guard(mutex)(&data->lock); 316 316 + 317 317 + switch (type) { 318 318 + case IRQ_TYPE_EDGE_RISING: 319 319 + data->irq_trig_rising |= BIT(hwirq); 320 320 + break; 321 321 + 322 322 + case IRQ_TYPE_EDGE_FALLING: 323 323 + data->irq_trig_falling |= BIT(hwirq); 324 324 + break; 325 325 + 326 326 + case IRQ_TYPE_EDGE_BOTH: 327 327 + data->irq_trig_rising |= BIT(hwirq); 328 328 + data->irq_trig_falling |= BIT(hwirq); 329 329 + break; 330 330 + 331 331 + default: 332 332 + return -ENOTSUPP; 333 333 + } 334 334 + 335 335 + return 0; 336 336 + } 337 337 + 338 338 + static void nct6694_irq_bus_lock(struct irq_data *d) 339 339 + { 340 340 + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); 341 341 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 342 342 + 343 343 + mutex_lock(&data->irq_lock); 344 344 + } 345 345 + 346 346 + static void nct6694_irq_bus_sync_unlock(struct irq_data *d) 347 347 + { 348 348 + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); 349 349 + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); 350 350 + struct nct6694_cmd_header cmd_hd = { 351 351 + .mod = NCT6694_GPIO_MOD, 352 352 + .offset = cpu_to_le16(NCT6694_GPI_FALLING + data->group), 353 353 + .len = cpu_to_le16(sizeof(data->reg_val)) 354 354 + }; 355 355 + 356 356 + scoped_guard(mutex, &data->lock) { 357 357 + nct6694_write_msg(data->nct6694, &cmd_hd, &data->irq_trig_falling); 358 358 + 359 359 + cmd_hd.offset = cpu_to_le16(NCT6694_GPI_RISING + data->group); 360 360 + nct6694_write_msg(data->nct6694, &cmd_hd, &data->irq_trig_rising); 361 361 + } 362 362 + 363 363 + mutex_unlock(&data->irq_lock); 364 364 + } 365 365 + 366 366 + static const struct irq_chip nct6694_irq_chip = { 367 367 + .name = "gpio-nct6694", 368 368 + .irq_mask = nct6694_irq_mask, 369 369 + .irq_unmask = nct6694_irq_unmask, 370 370 + .irq_set_type = nct6694_irq_set_type, 371 371 + .irq_bus_lock = nct6694_irq_bus_lock, 372 372 + .irq_bus_sync_unlock = nct6694_irq_bus_sync_unlock, 373 373 + .flags = IRQCHIP_IMMUTABLE, 374 374 + GPIOCHIP_IRQ_RESOURCE_HELPERS, 375 375 + }; 376 376 + 377 377 + static void nct6694_irq_dispose_mapping(void *d) 378 378 + { 379 379 + struct nct6694_gpio_data *data = d; 380 380 + 381 381 + irq_dispose_mapping(data->irq); 382 382 + } 383 383 + 384 384 + static void nct6694_gpio_ida_free(void *d) 385 385 + { 386 386 + struct nct6694_gpio_data *data = d; 387 387 + struct nct6694 *nct6694 = data->nct6694; 388 388 + 389 389 + ida_free(&nct6694->gpio_ida, data->group); 390 390 + } 391 391 + 392 392 + static int nct6694_gpio_probe(struct platform_device *pdev) 393 393 + { 394 394 + struct device *dev = &pdev->dev; 395 395 + struct nct6694 *nct6694 = dev_get_drvdata(dev->parent); 396 396 + struct nct6694_gpio_data *data; 397 397 + struct gpio_irq_chip *girq; 398 398 + int ret, i; 399 399 + char **names; 400 400 + 401 401 + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 402 402 + if (!data) 403 403 + return -ENOMEM; 404 404 + 405 405 + data->nct6694 = nct6694; 406 406 + 407 407 + ret = ida_alloc(&nct6694->gpio_ida, GFP_KERNEL); 408 408 + if (ret < 0) 409 409 + return ret; 410 410 + data->group = ret; 411 411 + 412 412 + ret = devm_add_action_or_reset(dev, nct6694_gpio_ida_free, data); 413 413 + if (ret) 414 414 + return ret; 415 415 + 416 416 + names = devm_kcalloc(dev, NCT6694_NR_GPIO, sizeof(char *), 417 417 + GFP_KERNEL); 418 418 + if (!names) 419 419 + return -ENOMEM; 420 420 + 421 421 + for (i = 0; i < NCT6694_NR_GPIO; i++) { 422 422 + names[i] = devm_kasprintf(dev, GFP_KERNEL, "GPIO%X%d", 423 423 + data->group, i); 424 424 + if (!names[i]) 425 425 + return -ENOMEM; 426 426 + } 427 427 + 428 428 + data->irq = irq_create_mapping(nct6694->domain, 429 429 + NCT6694_IRQ_GPIO0 + data->group); 430 430 + if (!data->irq) 431 431 + return -EINVAL; 432 432 + 433 433 + ret = devm_add_action_or_reset(dev, nct6694_irq_dispose_mapping, data); 434 434 + if (ret) 435 435 + return ret; 436 436 + 437 437 + data->gpio.names = (const char * const*)names; 438 438 + data->gpio.label = pdev->name; 439 439 + data->gpio.direction_input = nct6694_direction_input; 440 440 + data->gpio.get = nct6694_get_value; 441 441 + data->gpio.direction_output = nct6694_direction_output; 442 442 + data->gpio.set = nct6694_set_value; 443 443 + data->gpio.get_direction = nct6694_get_direction; 444 444 + data->gpio.set_config = nct6694_set_config; 445 445 + data->gpio.init_valid_mask = nct6694_init_valid_mask; 446 446 + data->gpio.base = -1; 447 447 + data->gpio.can_sleep = false; 448 448 + data->gpio.owner = THIS_MODULE; 449 449 + data->gpio.ngpio = NCT6694_NR_GPIO; 450 450 + 451 451 + platform_set_drvdata(pdev, data); 452 452 + 453 453 + ret = devm_mutex_init(dev, &data->lock); 454 454 + if (ret) 455 455 + return ret; 456 456 + 457 457 + ret = devm_mutex_init(dev, &data->irq_lock); 458 458 + if (ret) 459 459 + return ret; 460 460 + 461 461 + ret = nct6694_get_irq_trig(data); 462 462 + if (ret) { 463 463 + dev_err_probe(dev, ret, "Failed to get irq trigger type\n"); 464 464 + return ret; 465 465 + } 466 466 + 467 467 + girq = &data->gpio.irq; 468 468 + gpio_irq_chip_set_chip(girq, &nct6694_irq_chip); 469 469 + girq->parent_handler = NULL; 470 470 + girq->num_parents = 0; 471 471 + girq->parents = NULL; 472 472 + girq->default_type = IRQ_TYPE_NONE; 473 473 + girq->handler = handle_level_irq; 474 474 + girq->threaded = true; 475 475 + 476 476 + ret = devm_request_threaded_irq(dev, data->irq, NULL, nct6694_irq_handler, 477 477 + IRQF_ONESHOT | IRQF_SHARED, 478 478 + "gpio-nct6694", data); 479 479 + if (ret) { 480 480 + dev_err_probe(dev, ret, "Failed to request irq\n"); 481 481 + return ret; 482 482 + } 483 483 + 484 484 + return devm_gpiochip_add_data(dev, &data->gpio, data); 485 485 + } 486 486 + 487 487 + static struct platform_driver nct6694_gpio_driver = { 488 488 + .driver = { 489 489 + .name = "nct6694-gpio", 490 490 + }, 491 491 + .probe = nct6694_gpio_probe, 492 492 + }; 493 493 + 494 494 + module_platform_driver(nct6694_gpio_driver); 495 495 + 496 496 + MODULE_DESCRIPTION("USB-GPIO controller driver for NCT6694"); 497 497 + MODULE_AUTHOR("Ming Yu <tmyu0@nuvoton.com>"); 498 498 + MODULE_LICENSE("GPL"); 499 499 + MODULE_ALIAS("platform:nct6694-gpio");

+14 -13

drivers/gpio/gpio-nomadik.c

reviewed

··· 20 20 */ 21 21 #include <linux/cleanup.h> 22 22 #include <linux/clk.h> 23 23 + #include <linux/gpio/consumer.h> 23 24 #include <linux/gpio/driver.h> 24 25 #include <linux/interrupt.h> 25 26 #include <linux/kernel.h> ··· 397 396 } 398 397 399 398 void nmk_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev, 400 400 - struct gpio_chip *chip, unsigned int offset, 401 401 - unsigned int gpio) 399 399 + struct gpio_chip *chip, unsigned int offset) 402 400 { 403 401 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 402 402 + #ifdef CONFIG_PINCTRL_NOMADIK 403 403 + struct gpio_desc *desc; 404 404 + #endif 404 405 int mode; 405 406 bool is_out; 406 407 bool data_out; ··· 428 425 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 429 426 mode = nmk_gpio_get_mode(nmk_chip, offset); 430 427 #ifdef CONFIG_PINCTRL_NOMADIK 431 431 - if (mode == NMK_GPIO_ALT_C && pctldev) 432 432 - mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 428 428 + if (mode == NMK_GPIO_ALT_C && pctldev) { 429 429 + desc = gpio_device_get_desc(chip->gpiodev, offset); 430 430 + mode = nmk_prcm_gpiocr_get_mode(pctldev, desc_to_gpio(desc)); 431 431 + } 433 432 #endif 434 433 435 434 if (is_out) { 436 435 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 437 437 - gpio, 438 438 - label ?: "(none)", 439 439 - str_hi_lo(data_out), 436 436 + offset, label ?: "(none)", str_hi_lo(data_out), 440 437 (mode < 0) ? "unknown" : modes[mode]); 441 438 } else { 442 439 int irq = chip->to_irq(chip, offset); ··· 448 445 }; 449 446 450 447 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 451 451 - gpio, 452 452 - label ?: "(none)", 453 453 - pulls[pullidx], 448 448 + offset, label ?: "(none)", pulls[pullidx], 454 449 (mode < 0) ? "unknown" : modes[mode]); 455 450 456 451 val = nmk_gpio_get_input(chip, offset); ··· 480 479 481 480 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 482 481 { 483 483 - unsigned int i, gpio = chip->base; 482 482 + unsigned int i; 484 483 485 485 - for (i = 0; i < chip->ngpio; i++, gpio++) { 486 486 - nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 484 484 + for (i = 0; i < chip->ngpio; i++) { 485 485 + nmk_gpio_dbg_show_one(s, NULL, chip, i); 487 486 seq_puts(s, "\n"); 488 487 } 489 488 }

+1 -7

drivers/gpio/gpio-pisosr.c

reviewed

··· 108 108 .can_sleep = true, 109 109 }; 110 110 111 111 - static void pisosr_mutex_destroy(void *lock) 112 112 - { 113 113 - mutex_destroy(lock); 114 114 - } 115 115 - 116 111 static int pisosr_gpio_probe(struct spi_device *spi) 117 112 { 118 113 struct device *dev = &spi->dev; ··· 134 139 return dev_err_probe(dev, PTR_ERR(gpio->load_gpio), 135 140 "Unable to allocate load GPIO\n"); 136 141 137 137 - mutex_init(&gpio->lock); 138 138 - ret = devm_add_action_or_reset(dev, pisosr_mutex_destroy, &gpio->lock); 142 142 + ret = devm_mutex_init(dev, &gpio->lock); 139 143 if (ret) 140 144 return ret; 141 145

+21 -14

drivers/gpio/gpio-rda.c

reviewed

··· 8 8 9 9 #include <linux/bitops.h> 10 10 #include <linux/gpio/driver.h> 11 11 + #include <linux/gpio/generic.h> 11 12 #include <linux/kernel.h> 12 13 #include <linux/module.h> 13 14 #include <linux/platform_device.h> ··· 36 35 #define RDA_GPIO_BANK_NR 32 37 36 38 37 struct rda_gpio { 39 39 - struct gpio_chip chip; 38 38 + struct gpio_generic_chip chip; 40 39 void __iomem *base; 41 40 spinlock_t lock; 42 41 int irq; ··· 209 208 210 209 static int rda_gpio_probe(struct platform_device *pdev) 211 210 { 211 211 + struct gpio_generic_chip_config config; 212 212 struct device *dev = &pdev->dev; 213 213 struct gpio_irq_chip *girq; 214 214 struct rda_gpio *rda_gpio; ··· 237 235 238 236 spin_lock_init(&rda_gpio->lock); 239 237 240 240 - ret = bgpio_init(&rda_gpio->chip, dev, 4, 241 241 - rda_gpio->base + RDA_GPIO_VAL, 242 242 - rda_gpio->base + RDA_GPIO_SET, 243 243 - rda_gpio->base + RDA_GPIO_CLR, 244 244 - rda_gpio->base + RDA_GPIO_OEN_SET_OUT, 245 245 - rda_gpio->base + RDA_GPIO_OEN_SET_IN, 246 246 - BGPIOF_READ_OUTPUT_REG_SET); 238 238 + config = (struct gpio_generic_chip_config) { 239 239 + .dev = dev, 240 240 + .sz = 4, 241 241 + .dat = rda_gpio->base + RDA_GPIO_VAL, 242 242 + .set = rda_gpio->base + RDA_GPIO_SET, 243 243 + .clr = rda_gpio->base + RDA_GPIO_CLR, 244 244 + .dirout = rda_gpio->base + RDA_GPIO_OEN_SET_OUT, 245 245 + .dirin = rda_gpio->base + RDA_GPIO_OEN_SET_IN, 246 246 + .flags = GPIO_GENERIC_READ_OUTPUT_REG_SET, 247 247 + }; 248 248 + 249 249 + ret = gpio_generic_chip_init(&rda_gpio->chip, &config); 247 250 if (ret) { 248 248 - dev_err(dev, "bgpio_init failed\n"); 251 251 + dev_err(dev, "failed to initialize the generic GPIO chip\n"); 249 252 return ret; 250 253 } 251 254 252 252 - rda_gpio->chip.label = dev_name(dev); 253 253 - rda_gpio->chip.ngpio = ngpios; 254 254 - rda_gpio->chip.base = -1; 255 255 + rda_gpio->chip.gc.label = dev_name(dev); 256 256 + rda_gpio->chip.gc.ngpio = ngpios; 257 257 + rda_gpio->chip.gc.base = -1; 255 258 256 259 if (rda_gpio->irq >= 0) { 257 257 - girq = &rda_gpio->chip.irq; 260 260 + girq = &rda_gpio->chip.gc.irq; 258 261 gpio_irq_chip_set_chip(girq, &rda_gpio_irq_chip); 259 262 girq->handler = handle_bad_irq; 260 263 girq->default_type = IRQ_TYPE_NONE; ··· 276 269 277 270 platform_set_drvdata(pdev, rda_gpio); 278 271 279 279 - return devm_gpiochip_add_data(dev, &rda_gpio->chip, rda_gpio); 272 272 + return devm_gpiochip_add_data(dev, &rda_gpio->chip.gc, rda_gpio); 280 273 } 281 274 282 275 static const struct of_device_id rda_gpio_of_match[] = {

+24 -17

drivers/gpio/gpio-realtek-otto.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 3 3 - #include <linux/gpio/driver.h> 4 3 #include <linux/cpumask.h> 4 4 + #include <linux/gpio/driver.h> 5 5 + #include <linux/gpio/generic.h> 5 6 #include <linux/irq.h> 6 7 #include <linux/minmax.h> 7 8 #include <linux/mod_devicetable.h> ··· 42 41 /** 43 42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data 44 43 * 45 45 - * @gc: Associated gpio_chip instance 44 44 + * @chip: Associated gpio_generic_chip instance 46 45 * @base: Base address of the register block for a GPIO bank 47 46 * @lock: Lock for accessing the IRQ registers and values 48 47 * @intr_mask: Mask for interrupts lines ··· 65 64 * IMR on changes. 66 65 */ 67 66 struct realtek_gpio_ctrl { 68 68 - struct gpio_chip gc; 67 67 + struct gpio_generic_chip chip; 69 68 void __iomem *base; 70 69 void __iomem *cpumask_base; 71 70 struct cpumask cpu_irq_maskable; ··· 102 101 { 103 102 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 104 103 105 105 - return container_of(gc, struct realtek_gpio_ctrl, gc); 104 104 + return container_of(to_gpio_generic_chip(gc), struct realtek_gpio_ctrl, chip); 106 105 } 107 106 108 107 /* ··· 195 194 unsigned int line = irqd_to_hwirq(data); 196 195 unsigned long flags; 197 196 198 198 - gpiochip_enable_irq(&ctrl->gc, line); 197 197 + gpiochip_enable_irq(&ctrl->chip.gc, line); 199 198 200 199 raw_spin_lock_irqsave(&ctrl->lock, flags); 201 200 ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK; ··· 214 213 realtek_gpio_update_line_imr(ctrl, line); 215 214 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 216 215 217 217 - gpiochip_disable_irq(&ctrl->gc, line); 216 216 + gpiochip_disable_irq(&ctrl->chip.gc, line); 218 217 } 219 218 220 219 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) ··· 357 356 358 357 static int realtek_gpio_probe(struct platform_device *pdev) 359 358 { 359 359 + struct gpio_generic_chip_config config; 360 360 struct device *dev = &pdev->dev; 361 361 - unsigned long bgpio_flags; 361 361 + unsigned long gen_gc_flags; 362 362 unsigned int dev_flags; 363 363 struct gpio_irq_chip *girq; 364 364 struct realtek_gpio_ctrl *ctrl; ··· 390 388 raw_spin_lock_init(&ctrl->lock); 391 389 392 390 if (dev_flags & GPIO_PORTS_REVERSED) { 393 393 - bgpio_flags = 0; 391 391 + gen_gc_flags = 0; 394 392 ctrl->bank_read = realtek_gpio_bank_read; 395 393 ctrl->bank_write = realtek_gpio_bank_write; 396 394 ctrl->line_imr_pos = realtek_gpio_line_imr_pos; 397 395 } else { 398 398 - bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; 396 396 + gen_gc_flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 399 397 ctrl->bank_read = realtek_gpio_bank_read_swapped; 400 398 ctrl->bank_write = realtek_gpio_bank_write_swapped; 401 399 ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped; 402 400 } 403 401 404 404 - err = bgpio_init(&ctrl->gc, dev, 4, 405 405 - ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL, 406 406 - ctrl->base + REALTEK_GPIO_REG_DIR, NULL, 407 407 - bgpio_flags); 402 402 + config = (struct gpio_generic_chip_config) { 403 403 + .dev = dev, 404 404 + .sz = 4, 405 405 + .dat = ctrl->base + REALTEK_GPIO_REG_DATA, 406 406 + .dirout = ctrl->base + REALTEK_GPIO_REG_DIR, 407 407 + .flags = gen_gc_flags, 408 408 + }; 409 409 + 410 410 + err = gpio_generic_chip_init(&ctrl->chip, &config); 408 411 if (err) { 409 412 dev_err(dev, "unable to init generic GPIO"); 410 413 return err; 411 414 } 412 415 413 413 - ctrl->gc.ngpio = ngpios; 414 414 - ctrl->gc.owner = THIS_MODULE; 416 416 + ctrl->chip.gc.ngpio = ngpios; 417 417 + ctrl->chip.gc.owner = THIS_MODULE; 415 418 416 419 irq = platform_get_irq_optional(pdev, 0); 417 420 if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) { 418 418 - girq = &ctrl->gc.irq; 421 421 + girq = &ctrl->chip.gc.irq; 419 422 gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip); 420 423 girq->default_type = IRQ_TYPE_NONE; 421 424 girq->handler = handle_bad_irq; ··· 449 442 cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable); 450 443 } 451 444 452 452 - return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); 445 445 + return devm_gpiochip_add_data(dev, &ctrl->chip.gc, ctrl); 453 446 } 454 447 455 448 static struct platform_driver realtek_gpio_driver = {

+28 -2

drivers/gpio/gpio-regmap.c

reviewed

··· 32 32 unsigned int reg_dir_in_base; 33 33 unsigned int reg_dir_out_base; 34 34 35 35 + #ifdef CONFIG_REGMAP_IRQ 36 36 + int regmap_irq_line; 37 37 + struct regmap_irq_chip_data *irq_chip_data; 38 38 + #endif 39 39 + 35 40 int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, 36 41 unsigned int offset, unsigned int *reg, 37 42 unsigned int *mask); ··· 220 215 */ 221 216 struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config) 222 217 { 218 218 + struct irq_domain *irq_domain; 223 219 struct gpio_regmap *gpio; 224 220 struct gpio_chip *chip; 225 221 int ret; ··· 261 255 chip->names = config->names; 262 256 chip->label = config->label ?: dev_name(config->parent); 263 257 chip->can_sleep = regmap_might_sleep(config->regmap); 258 258 + chip->init_valid_mask = config->init_valid_mask; 264 259 265 260 chip->request = gpiochip_generic_request; 266 261 chip->free = gpiochip_generic_free; ··· 302 295 if (ret < 0) 303 296 goto err_free_gpio; 304 297 305 305 - if (config->irq_domain) { 306 306 - ret = gpiochip_irqchip_add_domain(chip, config->irq_domain); 298 298 + #ifdef CONFIG_REGMAP_IRQ 299 299 + if (config->regmap_irq_chip) { 300 300 + gpio->regmap_irq_line = config->regmap_irq_line; 301 301 + ret = regmap_add_irq_chip_fwnode(dev_fwnode(config->parent), config->regmap, 302 302 + config->regmap_irq_line, config->regmap_irq_flags, 303 303 + 0, config->regmap_irq_chip, &gpio->irq_chip_data); 304 304 + if (ret) 305 305 + goto err_free_gpio; 306 306 + 307 307 + irq_domain = regmap_irq_get_domain(gpio->irq_chip_data); 308 308 + } else 309 309 + #endif 310 310 + irq_domain = config->irq_domain; 311 311 + 312 312 + if (irq_domain) { 313 313 + ret = gpiochip_irqchip_add_domain(chip, irq_domain); 307 314 if (ret) 308 315 goto err_remove_gpiochip; 309 316 } ··· 338 317 */ 339 318 void gpio_regmap_unregister(struct gpio_regmap *gpio) 340 319 { 320 320 + #ifdef CONFIG_REGMAP_IRQ 321 321 + if (gpio->irq_chip_data) 322 322 + regmap_del_irq_chip(gpio->regmap_irq_line, gpio->irq_chip_data); 323 323 + #endif 324 324 + 341 325 gpiochip_remove(&gpio->gpio_chip); 342 326 kfree(gpio); 343 327 }

+38 -36

drivers/gpio/gpio-sifive.c

reviewed

··· 7 7 #include <linux/device.h> 8 8 #include <linux/errno.h> 9 9 #include <linux/gpio/driver.h> 10 10 + #include <linux/gpio/generic.h> 10 11 #include <linux/init.h> 11 12 #include <linux/platform_device.h> 12 13 #include <linux/property.h> ··· 33 32 34 33 struct sifive_gpio { 35 34 void __iomem *base; 36 36 - struct gpio_chip gc; 35 35 + struct gpio_generic_chip gen_gc; 37 36 struct regmap *regs; 38 37 unsigned long irq_state; 39 38 unsigned int trigger[SIFIVE_GPIO_MAX]; ··· 42 41 43 42 static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset) 44 43 { 45 45 - unsigned long flags; 46 44 unsigned int trigger; 47 45 48 48 - raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags); 46 46 + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); 47 47 + 49 48 trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0; 50 49 regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset), 51 50 (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0); ··· 55 54 (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0); 56 55 regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset), 57 56 (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0); 58 58 - raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); 59 57 } 60 58 61 59 static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger) ··· 72 72 } 73 73 74 74 static void sifive_gpio_irq_enable(struct irq_data *d) 75 75 - { 75 75 + { 76 76 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 77 77 struct sifive_gpio *chip = gpiochip_get_data(gc); 78 78 irq_hw_number_t hwirq = irqd_to_hwirq(d); 79 79 int offset = hwirq % SIFIVE_GPIO_MAX; 80 80 u32 bit = BIT(offset); 81 81 - unsigned long flags; 82 81 83 82 gpiochip_enable_irq(gc, hwirq); 84 83 irq_chip_enable_parent(d); ··· 85 86 /* Switch to input */ 86 87 gc->direction_input(gc, offset); 87 88 88 88 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 89 89 - /* Clear any sticky pending interrupts */ 90 90 - regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); 91 91 - regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); 92 92 - regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); 93 93 - regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); 94 94 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 89 89 + scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) { 90 90 + /* Clear any sticky pending interrupts */ 91 91 + regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); 92 92 + regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); 93 93 + regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); 94 94 + regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); 95 95 + } 95 96 96 97 /* Enable interrupts */ 97 98 assign_bit(offset, &chip->irq_state, 1); ··· 117 118 struct sifive_gpio *chip = gpiochip_get_data(gc); 118 119 int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX; 119 120 u32 bit = BIT(offset); 120 120 - unsigned long flags; 121 121 122 122 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 123 123 - /* Clear all pending interrupts */ 124 124 - regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); 125 125 - regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); 126 126 - regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); 127 127 - regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); 128 128 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 122 122 + scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) { 123 123 + /* Clear all pending interrupts */ 124 124 + regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); 125 125 + regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); 126 126 + regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); 127 127 + regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); 128 128 + } 129 129 130 130 irq_chip_eoi_parent(d); 131 131 } ··· 172 174 .reg_bits = 32, 173 175 .reg_stride = 4, 174 176 .val_bits = 32, 175 175 - .fast_io = true, 176 177 .disable_locking = true, 177 178 }; 178 179 179 180 static int sifive_gpio_probe(struct platform_device *pdev) 180 181 { 182 182 + struct gpio_generic_chip_config config; 181 183 struct device *dev = &pdev->dev; 182 184 struct irq_domain *parent; 183 185 struct gpio_irq_chip *girq; ··· 216 218 */ 217 219 parent = irq_get_irq_data(chip->irq_number[0])->domain; 218 220 219 219 - ret = bgpio_init(&chip->gc, dev, 4, 220 220 - chip->base + SIFIVE_GPIO_INPUT_VAL, 221 221 - chip->base + SIFIVE_GPIO_OUTPUT_VAL, 222 222 - NULL, 223 223 - chip->base + SIFIVE_GPIO_OUTPUT_EN, 224 224 - chip->base + SIFIVE_GPIO_INPUT_EN, 225 225 - BGPIOF_READ_OUTPUT_REG_SET); 221 221 + config = (struct gpio_generic_chip_config) { 222 222 + .dev = dev, 223 223 + .sz = 4, 224 224 + .dat = chip->base + SIFIVE_GPIO_INPUT_VAL, 225 225 + .set = chip->base + SIFIVE_GPIO_OUTPUT_VAL, 226 226 + .dirout = chip->base + SIFIVE_GPIO_OUTPUT_EN, 227 227 + .dirin = chip->base + SIFIVE_GPIO_INPUT_EN, 228 228 + .flags = GPIO_GENERIC_READ_OUTPUT_REG_SET, 229 229 + }; 230 230 + 231 231 + ret = gpio_generic_chip_init(&chip->gen_gc, &config); 226 232 if (ret) { 227 233 dev_err(dev, "unable to init generic GPIO\n"); 228 234 return ret; ··· 239 237 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0); 240 238 chip->irq_state = 0; 241 239 242 242 - chip->gc.base = -1; 243 243 - chip->gc.ngpio = ngpio; 244 244 - chip->gc.label = dev_name(dev); 245 245 - chip->gc.parent = dev; 246 246 - chip->gc.owner = THIS_MODULE; 247 247 - girq = &chip->gc.irq; 240 240 + chip->gen_gc.gc.base = -1; 241 241 + chip->gen_gc.gc.ngpio = ngpio; 242 242 + chip->gen_gc.gc.label = dev_name(dev); 243 243 + chip->gen_gc.gc.parent = dev; 244 244 + chip->gen_gc.gc.owner = THIS_MODULE; 245 245 + girq = &chip->gen_gc.gc.irq; 248 246 gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip); 249 247 girq->fwnode = dev_fwnode(dev); 250 248 girq->parent_domain = parent; ··· 252 250 girq->handler = handle_bad_irq; 253 251 girq->default_type = IRQ_TYPE_NONE; 254 252 255 255 - return gpiochip_add_data(&chip->gc, chip); 253 253 + return gpiochip_add_data(&chip->gen_gc.gc, chip); 256 254 } 257 255 258 256 static const struct of_device_id sifive_gpio_match[] = {

+1 -2

drivers/gpio/gpio-sim.c

reviewed

··· 262 262 guard(mutex)(&chip->lock); 263 263 264 264 for_each_hwgpio(gc, i, label) 265 265 - seq_printf(seq, " gpio-%-3d (%s) %s,%s\n", 266 266 - gc->base + i, 265 265 + seq_printf(seq, " gpio-%-3d (%s) %s,%s\n", i, 267 266 label ?: "<unused>", 268 267 test_bit(i, chip->direction_map) ? "input" : 269 268 test_bit(i, chip->value_map) ? "output-high" :

+14 -6

drivers/gpio/gpio-sodaville.c

reviewed

··· 9 9 10 10 #include <linux/errno.h> 11 11 #include <linux/gpio/driver.h> 12 12 + #include <linux/gpio/generic.h> 12 13 #include <linux/init.h> 13 14 #include <linux/interrupt.h> 14 15 #include <linux/io.h> ··· 40 39 void __iomem *gpio_pub_base; 41 40 struct irq_domain *id; 42 41 struct irq_chip_generic *gc; 43 43 - struct gpio_chip chip; 42 42 + struct gpio_generic_chip gen_gc; 44 43 }; 45 44 46 45 static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type) ··· 181 180 static int sdv_gpio_probe(struct pci_dev *pdev, 182 181 const struct pci_device_id *pci_id) 183 182 { 183 183 + struct gpio_generic_chip_config config; 184 184 struct sdv_gpio_chip_data *sd; 185 185 int ret; 186 186 u32 mux_val; ··· 208 206 if (!ret) 209 207 writel(mux_val, sd->gpio_pub_base + GPMUXCTL); 210 208 211 211 - ret = bgpio_init(&sd->chip, &pdev->dev, 4, 212 212 - sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR, 213 213 - NULL, sd->gpio_pub_base + GPOER, NULL, 0); 209 209 + config = (struct gpio_generic_chip_config) { 210 210 + .dev = &pdev->dev, 211 211 + .sz = 4, 212 212 + .dat = sd->gpio_pub_base + GPINR, 213 213 + .set = sd->gpio_pub_base + GPOUTR, 214 214 + .dirout = sd->gpio_pub_base + GPOER, 215 215 + }; 216 216 + 217 217 + ret = gpio_generic_chip_init(&sd->gen_gc, &config); 214 218 if (ret) 215 219 return ret; 216 220 217 217 - sd->chip.ngpio = SDV_NUM_PUB_GPIOS; 221 221 + sd->gen_gc.gc.ngpio = SDV_NUM_PUB_GPIOS; 218 222 219 219 - ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd); 223 223 + ret = devm_gpiochip_add_data(&pdev->dev, &sd->gen_gc.gc, sd); 220 224 if (ret < 0) { 221 225 dev_err(&pdev->dev, "gpiochip_add() failed.\n"); 222 226 return ret;

+21 -8

drivers/gpio/gpio-spacemit-k1.c

reviewed

··· 6 6 7 7 #include <linux/clk.h> 8 8 #include <linux/gpio/driver.h> 9 9 + #include <linux/gpio/generic.h> 9 10 #include <linux/init.h> 10 11 #include <linux/interrupt.h> 11 12 #include <linux/io.h> ··· 39 38 struct spacemit_gpio; 40 39 41 40 struct spacemit_gpio_bank { 42 42 - struct gpio_chip gc; 41 41 + struct gpio_generic_chip chip; 43 42 struct spacemit_gpio *sg; 44 43 void __iomem *base; 45 44 u32 irq_mask; ··· 73 72 return IRQ_NONE; 74 73 75 74 for_each_set_bit(n, &pending, BITS_PER_LONG) 76 76 - handle_nested_irq(irq_find_mapping(gb->gc.irq.domain, n)); 75 75 + handle_nested_irq(irq_find_mapping(gb->chip.gc.irq.domain, n)); 77 76 78 77 return IRQ_HANDLED; 79 78 } ··· 144 143 { 145 144 struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(data); 146 145 147 147 - seq_printf(p, "%s-%d", dev_name(gb->gc.parent), spacemit_gpio_bank_index(gb)); 146 146 + seq_printf(p, "%s-%d", dev_name(gb->chip.gc.parent), spacemit_gpio_bank_index(gb)); 148 147 } 149 148 150 149 static struct irq_chip spacemit_gpio_chip = { ··· 166 165 if (i >= SPACEMIT_NR_BANKS) 167 166 return false; 168 167 169 169 - return (gc == &sg->sgb[i].gc); 168 168 + return (gc == &sg->sgb[i].chip.gc); 170 169 } 171 170 172 171 static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, ··· 174 173 int index, int irq) 175 174 { 176 175 struct spacemit_gpio_bank *gb = &sg->sgb[index]; 177 177 - struct gpio_chip *gc = &gb->gc; 176 176 + struct gpio_generic_chip_config config; 177 177 + struct gpio_chip *gc = &gb->chip.gc; 178 178 struct device *dev = sg->dev; 179 179 struct gpio_irq_chip *girq; 180 180 void __iomem *dat, *set, *clr, *dirin, *dirout; ··· 189 187 dirin = gb->base + SPACEMIT_GCDR; 190 188 dirout = gb->base + SPACEMIT_GSDR; 191 189 190 190 + config = (struct gpio_generic_chip_config) { 191 191 + .dev = dev, 192 192 + .sz = 4, 193 193 + .dat = dat, 194 194 + .set = set, 195 195 + .clr = clr, 196 196 + .dirout = dirout, 197 197 + .dirin = dirin, 198 198 + .flags = GPIO_GENERIC_UNREADABLE_REG_SET | 199 199 + GPIO_GENERIC_UNREADABLE_REG_DIR, 200 200 + }; 201 201 + 192 202 /* This registers 32 GPIO lines per bank */ 193 193 - ret = bgpio_init(gc, dev, 4, dat, set, clr, dirout, dirin, 194 194 - BGPIOF_UNREADABLE_REG_SET | BGPIOF_UNREADABLE_REG_DIR); 203 203 + ret = gpio_generic_chip_init(&gb->chip, &config); 195 204 if (ret) 196 205 return dev_err_probe(dev, ret, "failed to init gpio chip\n"); 197 206 ··· 234 221 ret = devm_request_threaded_irq(dev, irq, NULL, 235 222 spacemit_gpio_irq_handler, 236 223 IRQF_ONESHOT | IRQF_SHARED, 237 237 - gb->gc.label, gb); 224 224 + gb->chip.gc.label, gb); 238 225 if (ret < 0) 239 226 return dev_err_probe(dev, ret, "failed to register IRQ\n"); 240 227

+24 -10

drivers/gpio/gpio-stmpe.c

reviewed

··· 262 262 stmpe_gpio->regs[REG_IE][regoffset] |= mask; 263 263 } 264 264 265 265 - static void stmpe_dbg_show_one(struct seq_file *s, 266 266 - struct gpio_chip *gc, 267 267 - unsigned offset, unsigned gpio) 265 265 + static void stmpe_dbg_show_one(struct seq_file *s, struct gpio_chip *gc, 266 266 + unsigned int offset) 268 267 { 269 268 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 270 269 struct stmpe *stmpe = stmpe_gpio->stmpe; ··· 285 286 286 287 if (dir) { 287 288 seq_printf(s, " gpio-%-3d (%-20.20s) out %s", 288 288 - gpio, label ?: "(none)", str_hi_lo(val)); 289 289 + offset, label ?: "(none)", str_hi_lo(val)); 289 290 } else { 290 291 u8 edge_det_reg; 291 292 u8 rise_reg; ··· 353 354 irqen = !!(ret & mask); 354 355 355 356 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", 356 356 - gpio, label ?: "(none)", 357 357 + offset, label ?: "(none)", 357 358 str_hi_lo(val), 358 359 edge_det_values[edge_det], 359 360 irqen ? "IRQ-enabled" : "IRQ-disabled", ··· 365 366 static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) 366 367 { 367 368 unsigned i; 368 368 - unsigned gpio = gc->base; 369 369 370 370 - for (i = 0; i < gc->ngpio; i++, gpio++) { 371 371 - stmpe_dbg_show_one(s, gc, i, gpio); 370 370 + for (i = 0; i < gc->ngpio; i++) { 371 371 + stmpe_dbg_show_one(s, gc, i); 372 372 seq_putc(s, '\n'); 373 373 } 374 374 } ··· 532 534 return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio); 533 535 } 534 536 537 537 + static const struct of_device_id stmpe_gpio_of_matches[] = { 538 538 + { .compatible = "st,stmpe-gpio", }, 539 539 + { /* sentinel */ } 540 540 + }; 541 541 + MODULE_DEVICE_TABLE(of, stmpe_gpio_of_matches); 542 542 + 535 543 static struct platform_driver stmpe_gpio_driver = { 536 544 .driver = { 537 537 - .suppress_bind_attrs = true, 538 538 - .name = "stmpe-gpio", 545 545 + .name = "stmpe-gpio", 546 546 + .of_match_table = stmpe_gpio_of_matches, 539 547 }, 540 548 .probe = stmpe_gpio_probe, 541 549 }; ··· 551 547 return platform_driver_register(&stmpe_gpio_driver); 552 548 } 553 549 subsys_initcall(stmpe_gpio_init); 550 550 + 551 551 + static void __exit stmpe_gpio_exit(void) 552 552 + { 553 553 + platform_driver_unregister(&stmpe_gpio_driver); 554 554 + } 555 555 + module_exit(stmpe_gpio_exit); 556 556 + 557 557 + MODULE_DESCRIPTION("STMPE expander GPIO"); 558 558 + MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); 559 559 + MODULE_LICENSE("GPL");

+37 -37

drivers/gpio/gpio-tb10x.c

reviewed

··· 7 7 * Christian Ruppert <christian.ruppert@abilis.com> 8 8 */ 9 9 10 10 - #include <linux/kernel.h> 11 11 - #include <linux/module.h> 12 12 - #include <linux/platform_device.h> 10 10 + #include <linux/bitops.h> 13 11 #include <linux/gpio/driver.h> 14 14 - #include <linux/slab.h> 15 15 - #include <linux/irq.h> 16 16 - #include <linux/irqdomain.h> 12 12 + #include <linux/gpio/generic.h> 17 13 #include <linux/interrupt.h> 18 14 #include <linux/io.h> 15 15 + #include <linux/irq.h> 16 16 + #include <linux/irqdomain.h> 17 17 + #include <linux/kernel.h> 18 18 + #include <linux/module.h> 19 19 #include <linux/of.h> 20 20 #include <linux/of_platform.h> 21 21 - #include <linux/spinlock.h> 22 22 - #include <linux/bitops.h> 23 21 #include <linux/pinctrl/consumer.h> 22 22 + #include <linux/platform_device.h> 23 23 + #include <linux/slab.h> 24 24 25 25 #define TB10X_GPIO_DIR_IN (0x00000000) 26 26 #define TB10X_GPIO_DIR_OUT (0x00000001) ··· 36 36 * @base: register base address 37 37 * @domain: IRQ domain of GPIO generated interrupts managed by this controller 38 38 * @irq: Interrupt line of parent interrupt controller 39 39 - * @gc: gpio_chip structure associated to this GPIO controller 39 39 + * @chip: Generic GPIO chip structure associated with this GPIO controller 40 40 */ 41 41 struct tb10x_gpio { 42 42 void __iomem *base; 43 43 struct irq_domain *domain; 44 44 int irq; 45 45 - struct gpio_chip gc; 45 45 + struct gpio_generic_chip chip; 46 46 }; 47 47 48 48 static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs) ··· 60 60 u32 mask, u32 val) 61 61 { 62 62 u32 r; 63 63 - unsigned long flags; 64 63 65 65 - raw_spin_lock_irqsave(&gpio->gc.bgpio_lock, flags); 64 64 + guard(gpio_generic_lock_irqsave)(&gpio->chip); 66 65 67 66 r = tb10x_reg_read(gpio, offs); 68 67 r = (r & ~mask) | (val & mask); 69 68 70 69 tb10x_reg_write(gpio, offs, r); 71 71 - 72 72 - raw_spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags); 73 70 } 74 71 75 72 static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset) ··· 104 107 105 108 static int tb10x_gpio_probe(struct platform_device *pdev) 106 109 { 110 110 + struct gpio_generic_chip_config config; 107 111 struct tb10x_gpio *tb10x_gpio; 108 112 struct device *dev = &pdev->dev; 109 113 struct device_node *np = dev->of_node; ··· 125 127 if (IS_ERR(tb10x_gpio->base)) 126 128 return PTR_ERR(tb10x_gpio->base); 127 129 128 128 - tb10x_gpio->gc.label = 130 130 + tb10x_gpio->chip.gc.label = 129 131 devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node); 130 130 - if (!tb10x_gpio->gc.label) 132 132 + if (!tb10x_gpio->chip.gc.label) 131 133 return -ENOMEM; 132 134 133 135 /* ··· 135 137 * the lines, no special set or clear registers and a data direction register 136 138 * wher 1 means "output". 137 139 */ 138 138 - ret = bgpio_init(&tb10x_gpio->gc, dev, 4, 139 139 - tb10x_gpio->base + OFFSET_TO_REG_DATA, 140 140 - NULL, 141 141 - NULL, 142 142 - tb10x_gpio->base + OFFSET_TO_REG_DDR, 143 143 - NULL, 144 144 - 0); 140 140 + config = (struct gpio_generic_chip_config) { 141 141 + .dev = dev, 142 142 + .sz = 4, 143 143 + .dat = tb10x_gpio->base + OFFSET_TO_REG_DATA, 144 144 + .dirout = tb10x_gpio->base + OFFSET_TO_REG_DDR, 145 145 + }; 146 146 + 147 147 + ret = gpio_generic_chip_init(&tb10x_gpio->chip, &config); 145 148 if (ret) { 146 149 dev_err(dev, "unable to init generic GPIO\n"); 147 150 return ret; 148 151 } 149 149 - tb10x_gpio->gc.base = -1; 150 150 - tb10x_gpio->gc.parent = dev; 151 151 - tb10x_gpio->gc.owner = THIS_MODULE; 152 152 + tb10x_gpio->chip.gc.base = -1; 153 153 + tb10x_gpio->chip.gc.parent = dev; 154 154 + tb10x_gpio->chip.gc.owner = THIS_MODULE; 152 155 /* 153 153 - * ngpio is set by bgpio_init() but we override it, this .request() 154 154 - * callback also overrides the one set up by generic GPIO. 156 156 + * ngpio is set by gpio_generic_chip_init() but we override it, this 157 157 + * .request() callback also overrides the one set up by generic GPIO. 155 158 */ 156 156 - tb10x_gpio->gc.ngpio = ngpio; 157 157 - tb10x_gpio->gc.request = gpiochip_generic_request; 158 158 - tb10x_gpio->gc.free = gpiochip_generic_free; 159 159 + tb10x_gpio->chip.gc.ngpio = ngpio; 160 160 + tb10x_gpio->chip.gc.request = gpiochip_generic_request; 161 161 + tb10x_gpio->chip.gc.free = gpiochip_generic_free; 159 162 160 160 - ret = devm_gpiochip_add_data(dev, &tb10x_gpio->gc, tb10x_gpio); 163 163 + ret = devm_gpiochip_add_data(dev, &tb10x_gpio->chip.gc, tb10x_gpio); 161 164 if (ret < 0) { 162 165 dev_err(dev, "Could not add gpiochip.\n"); 163 166 return ret; ··· 173 174 if (ret < 0) 174 175 return ret; 175 176 176 176 - tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq; 177 177 + tb10x_gpio->chip.gc.to_irq = tb10x_gpio_to_irq; 177 178 tb10x_gpio->irq = ret; 178 179 179 180 ret = devm_request_irq(dev, ret, tb10x_gpio_irq_cascade, ··· 182 183 if (ret != 0) 183 184 return ret; 184 185 185 185 - tb10x_gpio->domain = irq_domain_create_linear(dev_fwnode(dev), tb10x_gpio->gc.ngpio, 186 186 + tb10x_gpio->domain = irq_domain_create_linear(dev_fwnode(dev), 187 187 + tb10x_gpio->chip.gc.ngpio, 186 188 &irq_generic_chip_ops, NULL); 187 189 if (!tb10x_gpio->domain) { 188 190 return -ENOMEM; 189 191 } 190 192 191 193 ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain, 192 192 - tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label, 194 194 + tb10x_gpio->chip.gc.ngpio, 1, tb10x_gpio->chip.gc.label, 193 195 handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE, 194 196 IRQ_GC_INIT_MASK_CACHE); 195 197 if (ret) ··· 218 218 { 219 219 struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev); 220 220 221 221 - if (tb10x_gpio->gc.to_irq) { 221 221 + if (tb10x_gpio->chip.gc.to_irq) { 222 222 irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0], 223 223 - BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0); 223 223 + BIT(tb10x_gpio->chip.gc.ngpio) - 1, 0, 0); 224 224 kfree(tb10x_gpio->domain->gc); 225 225 irq_domain_remove(tb10x_gpio->domain); 226 226 }

+28

drivers/gpio/gpio-tegra186.c

reviewed

··· 20 20 #include <dt-bindings/gpio/tegra194-gpio.h> 21 21 #include <dt-bindings/gpio/tegra234-gpio.h> 22 22 #include <dt-bindings/gpio/tegra241-gpio.h> 23 23 + #include <dt-bindings/gpio/tegra256-gpio.h> 23 24 24 25 /* security registers */ 25 26 #define TEGRA186_GPIO_CTL_SCR 0x0c ··· 1280 1279 .has_vm_support = false, 1281 1280 }; 1282 1281 1282 1282 + #define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1283 1283 + [TEGRA256_MAIN_GPIO_PORT_##_name] = { \ 1284 1284 + .name = #_name, \ 1285 1285 + .bank = _bank, \ 1286 1286 + .port = _port, \ 1287 1287 + .pins = _pins, \ 1288 1288 + } 1289 1289 + 1290 1290 + static const struct tegra_gpio_port tegra256_main_ports[] = { 1291 1291 + TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8), 1292 1292 + TEGRA256_MAIN_GPIO_PORT(B, 0, 1, 8), 1293 1293 + TEGRA256_MAIN_GPIO_PORT(C, 0, 2, 8), 1294 1294 + TEGRA256_MAIN_GPIO_PORT(D, 0, 3, 8), 1295 1295 + }; 1296 1296 + 1297 1297 + static const struct tegra_gpio_soc tegra256_main_soc = { 1298 1298 + .num_ports = ARRAY_SIZE(tegra256_main_ports), 1299 1299 + .ports = tegra256_main_ports, 1300 1300 + .name = "tegra256-gpio-main", 1301 1301 + .instance = 1, 1302 1302 + .num_irqs_per_bank = 8, 1303 1303 + .has_vm_support = true, 1304 1304 + }; 1305 1305 + 1283 1306 static const struct of_device_id tegra186_gpio_of_match[] = { 1284 1307 { 1285 1308 .compatible = "nvidia,tegra186-gpio", ··· 1323 1298 }, { 1324 1299 .compatible = "nvidia,tegra234-gpio-aon", 1325 1300 .data = &tegra234_aon_soc 1301 1301 + }, { 1302 1302 + .compatible = "nvidia,tegra256-gpio", 1303 1303 + .data = &tegra256_main_soc 1326 1304 }, { 1327 1305 /* sentinel */ 1328 1306 }

+20 -19

drivers/gpio/gpio-ts4800.c

reviewed

··· 6 6 */ 7 7 8 8 #include <linux/gpio/driver.h> 9 9 + #include <linux/gpio/generic.h> 9 10 #include <linux/module.h> 10 10 - #include <linux/of.h> 11 11 #include <linux/platform_device.h> 12 12 + #include <linux/property.h> 12 13 13 14 #define DEFAULT_PIN_NUMBER 16 14 15 #define INPUT_REG_OFFSET 0x00 ··· 18 17 19 18 static int ts4800_gpio_probe(struct platform_device *pdev) 20 19 { 21 21 - struct device_node *node; 22 22 - struct gpio_chip *chip; 20 20 + struct gpio_generic_chip_config config; 21 21 + struct device *dev = &pdev->dev; 22 22 + struct gpio_generic_chip *chip; 23 23 void __iomem *base_addr; 24 24 int retval; 25 25 u32 ngpios; 26 26 27 27 - chip = devm_kzalloc(&pdev->dev, sizeof(struct gpio_chip), GFP_KERNEL); 27 27 + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 28 28 if (!chip) 29 29 return -ENOMEM; 30 30 ··· 33 31 if (IS_ERR(base_addr)) 34 32 return PTR_ERR(base_addr); 35 33 36 36 - node = pdev->dev.of_node; 37 37 - if (!node) 38 38 - return -EINVAL; 39 39 - 40 40 - retval = of_property_read_u32(node, "ngpios", &ngpios); 34 34 + retval = device_property_read_u32(dev, "ngpios", &ngpios); 41 35 if (retval == -EINVAL) 42 36 ngpios = DEFAULT_PIN_NUMBER; 43 37 else if (retval) 44 38 return retval; 45 39 46 46 - retval = bgpio_init(chip, &pdev->dev, 2, base_addr + INPUT_REG_OFFSET, 47 47 - base_addr + OUTPUT_REG_OFFSET, NULL, 48 48 - base_addr + DIRECTION_REG_OFFSET, NULL, 0); 49 49 - if (retval) { 50 50 - dev_err(&pdev->dev, "bgpio_init failed\n"); 51 51 - return retval; 52 52 - } 40 40 + config = (struct gpio_generic_chip_config) { 41 41 + .dev = dev, 42 42 + .sz = 2, 43 43 + .dat = base_addr + INPUT_REG_OFFSET, 44 44 + .set = base_addr + OUTPUT_REG_OFFSET, 45 45 + .dirout = base_addr + DIRECTION_REG_OFFSET, 46 46 + }; 53 47 54 54 - chip->ngpio = ngpios; 48 48 + retval = gpio_generic_chip_init(chip, &config); 49 49 + if (retval) 50 50 + return dev_err_probe(dev, retval, 51 51 + "failed to initialize the generic GPIO chip\n"); 55 52 56 56 - platform_set_drvdata(pdev, chip); 53 53 + chip->gc.ngpio = ngpios; 57 54 58 58 - return devm_gpiochip_add_data(&pdev->dev, chip, NULL); 55 55 + return devm_gpiochip_add_data(dev, &chip->gc, NULL); 59 56 } 60 57 61 58 static const struct of_device_id ts4800_gpio_of_match[] = {

+1 -3

drivers/gpio/gpio-twl4030.c

reviewed

··· 597 597 598 598 ret = devm_add_action_or_reset(&pdev->dev, gpio_twl4030_power_off_action, d); 599 599 if (ret) 600 600 - return dev_err_probe(&pdev->dev, ret, 601 601 - "failed to install power off handler\n"); 602 602 - 600 600 + return ret; 603 601 } 604 602 605 603 return 0;

+19 -12

drivers/gpio/gpio-vf610.c

reviewed

··· 10 10 #include <linux/clk.h> 11 11 #include <linux/err.h> 12 12 #include <linux/gpio/driver.h> 13 13 + #include <linux/gpio/generic.h> 13 14 #include <linux/init.h> 14 15 #include <linux/interrupt.h> 15 16 #include <linux/io.h> ··· 29 28 }; 30 29 31 30 struct vf610_gpio_port { 32 32 - struct gpio_chip gc; 31 31 + struct gpio_generic_chip chip; 33 32 void __iomem *base; 34 33 void __iomem *gpio_base; 35 34 const struct fsl_gpio_soc_data *sdata; ··· 109 108 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { 110 109 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); 111 110 112 112 - generic_handle_domain_irq(port->gc.irq.domain, pin); 111 111 + generic_handle_domain_irq(port->chip.gc.irq.domain, pin); 113 112 } 114 113 115 114 chained_irq_exit(chip, desc); ··· 215 214 216 215 static int vf610_gpio_probe(struct platform_device *pdev) 217 216 { 217 217 + struct gpio_generic_chip_config config; 218 218 struct device *dev = &pdev->dev; 219 219 struct vf610_gpio_port *port; 220 220 struct gpio_chip *gc; ··· 295 293 return ret; 296 294 } 297 295 298 298 - gc = &port->gc; 299 299 - flags = BGPIOF_PINCTRL_BACKEND; 296 296 + gc = &port->chip.gc; 297 297 + flags = GPIO_GENERIC_PINCTRL_BACKEND; 300 298 /* 301 299 * We only read the output register for current value on output 302 300 * lines if the direction register is available so we can switch 303 301 * direction. 304 302 */ 305 303 if (port->sdata->have_paddr) 306 306 - flags |= BGPIOF_READ_OUTPUT_REG_SET; 307 307 - ret = bgpio_init(gc, dev, 4, 308 308 - port->gpio_base + GPIO_PDIR, 309 309 - port->gpio_base + GPIO_PDOR, 310 310 - NULL, 311 311 - port->sdata->have_paddr ? port->gpio_base + GPIO_PDDR : NULL, 312 312 - NULL, 313 313 - flags); 304 304 + flags |= GPIO_GENERIC_READ_OUTPUT_REG_SET; 305 305 + 306 306 + config = (struct gpio_generic_chip_config) { 307 307 + .dev = dev, 308 308 + .sz = 4, 309 309 + .dat = port->gpio_base + GPIO_PDIR, 310 310 + .set = port->gpio_base + GPIO_PDOR, 311 311 + .dirout = port->sdata->have_paddr ? 312 312 + port->gpio_base + GPIO_PDDR : NULL, 313 313 + .flags = flags, 314 314 + }; 315 315 + 316 316 + ret = gpio_generic_chip_init(&port->chip, &config); 314 317 if (ret) 315 318 return dev_err_probe(dev, ret, "unable to init generic GPIO\n"); 316 319 gc->label = dev_name(dev);

+15 -10

drivers/gpio/gpio-visconti.c

reviewed

··· 10 10 11 11 #include <linux/bitops.h> 12 12 #include <linux/gpio/driver.h> 13 13 + #include <linux/gpio/generic.h> 13 14 #include <linux/init.h> 14 15 #include <linux/interrupt.h> 15 16 #include <linux/module.h> ··· 33 32 struct visconti_gpio { 34 33 void __iomem *base; 35 34 spinlock_t lock; /* protect gpio register */ 36 36 - struct gpio_chip gpio_chip; 35 35 + struct gpio_generic_chip chip; 37 36 struct device *dev; 38 37 }; 39 38 ··· 159 158 160 159 static int visconti_gpio_probe(struct platform_device *pdev) 161 160 { 161 161 + struct gpio_generic_chip_config config; 162 162 struct device *dev = &pdev->dev; 163 163 struct visconti_gpio *priv; 164 164 struct gpio_irq_chip *girq; ··· 191 189 return -ENODEV; 192 190 } 193 191 194 194 - ret = bgpio_init(&priv->gpio_chip, dev, 4, 195 195 - priv->base + GPIO_IDATA, 196 196 - priv->base + GPIO_OSET, 197 197 - priv->base + GPIO_OCLR, 198 198 - priv->base + GPIO_DIR, 199 199 - NULL, 200 200 - 0); 192 192 + config = (struct gpio_generic_chip_config) { 193 193 + .dev = dev, 194 194 + .sz = 4, 195 195 + .dat = priv->base + GPIO_IDATA, 196 196 + .set = priv->base + GPIO_OSET, 197 197 + .clr = priv->base + GPIO_OCLR, 198 198 + .dirout = priv->base + GPIO_DIR, 199 199 + }; 200 200 + 201 201 + ret = gpio_generic_chip_init(&priv->chip, &config); 201 202 if (ret) { 202 203 dev_err(dev, "unable to init generic GPIO\n"); 203 204 return ret; 204 205 } 205 206 206 206 - girq = &priv->gpio_chip.irq; 207 207 + girq = &priv->chip.gc.irq; 207 208 gpio_irq_chip_set_chip(girq, &visconti_gpio_irq_chip); 208 209 girq->fwnode = dev_fwnode(dev); 209 210 girq->parent_domain = parent; ··· 215 210 girq->default_type = IRQ_TYPE_NONE; 216 211 girq->handler = handle_level_irq; 217 212 218 218 - return devm_gpiochip_add_data(dev, &priv->gpio_chip, priv); 213 213 + return devm_gpiochip_add_data(dev, &priv->chip.gc, priv); 219 214 } 220 215 221 216 static const struct of_device_id visconti_gpio_of_match[] = {

+2 -3

drivers/gpio/gpio-wm831x.c

reviewed

··· 159 159 int i, tristated; 160 160 161 161 for (i = 0; i < chip->ngpio; i++) { 162 162 - int gpio = i + chip->base; 163 162 int reg; 164 163 const char *pull, *powerdomain; 165 164 ··· 174 175 } 175 176 176 177 seq_printf(s, " gpio-%-3d (%-20.20s) ", 177 177 - gpio, label ?: "Unrequested"); 178 178 + i, label ?: "Unrequested"); 178 179 179 180 reg = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i); 180 181 if (reg < 0) { 181 182 dev_err(wm831x->dev, 182 183 "GPIO control %d read failed: %d\n", 183 183 - gpio, reg); 184 184 + i, reg); 184 185 seq_putc(s, '\n'); 185 186 continue; 186 187 }

+2 -4

drivers/gpio/gpio-wm8994.c

reviewed

··· 194 194 int i; 195 195 196 196 for (i = 0; i < chip->ngpio; i++) { 197 197 - int gpio = i + chip->base; 198 197 int reg; 199 198 200 199 /* We report the GPIO even if it's not requested since ··· 207 208 continue; 208 209 } 209 210 210 210 - seq_printf(s, " gpio-%-3d (%-20.20s) ", gpio, 211 211 + seq_printf(s, " gpio-%-3d (%-20.20s) ", i, 211 212 label ?: "Unrequested"); 212 213 213 214 reg = wm8994_reg_read(wm8994, WM8994_GPIO_1 + i); 214 215 if (reg < 0) { 215 216 dev_err(wm8994->dev, 216 216 - "GPIO control %d read failed: %d\n", 217 217 - gpio, reg); 217 217 + "GPIO control %d read failed: %d\n", i, reg); 218 218 seq_printf(s, "\n"); 219 219 continue; 220 220 }

+33 -25

drivers/gpio/gpio-xgene-sb.c

reviewed

··· 21 21 #include <linux/types.h> 22 22 23 23 #include <linux/gpio/driver.h> 24 24 + #include <linux/gpio/generic.h> 24 25 25 26 #include "gpiolib-acpi.h" 26 27 ··· 41 40 42 41 /** 43 42 * struct xgene_gpio_sb - GPIO-Standby private data structure. 44 44 - * @gc: memory-mapped GPIO controllers. 43 43 + * @chip: Generic GPIO chip data 45 44 * @regs: GPIO register base offset 46 45 * @irq_domain: GPIO interrupt domain 47 46 * @irq_start: GPIO pin that start support interrupt ··· 49 48 * @parent_irq_base: Start parent HWIRQ 50 49 */ 51 50 struct xgene_gpio_sb { 52 52 - struct gpio_chip gc; 51 51 + struct gpio_generic_chip chip; 53 52 void __iomem *regs; 54 53 struct irq_domain *irq_domain; 55 54 u16 irq_start; ··· 63 62 static void xgene_gpio_set_bit(struct gpio_chip *gc, 64 63 void __iomem *reg, u32 gpio, int val) 65 64 { 65 65 + struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 66 66 u32 data; 67 67 68 68 - data = gc->read_reg(reg); 68 68 + data = gpio_generic_read_reg(chip, reg); 69 69 if (val) 70 70 data |= GPIO_MASK(gpio); 71 71 else 72 72 data &= ~GPIO_MASK(gpio); 73 73 - gc->write_reg(reg, data); 73 73 + gpio_generic_write_reg(chip, reg, data); 74 74 } 75 75 76 76 static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type) ··· 93 91 break; 94 92 } 95 93 96 96 - xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, 94 94 + xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO, 97 95 gpio * 2, 1); 98 98 - xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL, 96 96 + xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_INT_LVL, 99 97 d->hwirq, lvl_type); 100 98 101 99 /* Propagate IRQ type setting to parent */ ··· 111 109 112 110 irq_chip_mask_parent(d); 113 111 114 114 - gpiochip_disable_irq(&priv->gc, d->hwirq); 112 112 + gpiochip_disable_irq(&priv->chip.gc, d->hwirq); 115 113 } 116 114 117 115 static void xgene_gpio_sb_irq_unmask(struct irq_data *d) 118 116 { 119 117 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d); 120 118 121 121 - gpiochip_enable_irq(&priv->gc, d->hwirq); 119 119 + gpiochip_enable_irq(&priv->chip.gc, d->hwirq); 122 120 123 121 irq_chip_unmask_parent(d); 124 122 } ··· 157 155 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); 158 156 int ret; 159 157 160 160 - ret = gpiochip_lock_as_irq(&priv->gc, gpio); 158 158 + ret = gpiochip_lock_as_irq(&priv->chip.gc, gpio); 161 159 if (ret) { 162 162 - dev_err(priv->gc.parent, 160 160 + dev_err(priv->chip.gc.parent, 163 161 "Unable to configure XGene GPIO standby pin %d as IRQ\n", 164 162 gpio); 165 163 return ret; 166 164 } 167 165 168 168 - xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, 166 166 + xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO, 169 167 gpio * 2, 1); 170 168 return 0; 171 169 } ··· 176 174 struct xgene_gpio_sb *priv = d->host_data; 177 175 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); 178 176 179 179 - gpiochip_unlock_as_irq(&priv->gc, gpio); 180 180 - xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, 177 177 + gpiochip_unlock_as_irq(&priv->chip.gc, gpio); 178 178 + xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO, 181 179 gpio * 2, 0); 182 180 } 183 181 ··· 239 237 240 238 static int xgene_gpio_sb_probe(struct platform_device *pdev) 241 239 { 240 240 + struct gpio_generic_chip_config config; 242 241 struct xgene_gpio_sb *priv; 243 242 int ret; 244 243 void __iomem *regs; ··· 266 263 return -ENODEV; 267 264 } 268 265 269 269 - ret = bgpio_init(&priv->gc, &pdev->dev, 4, 270 270 - regs + MPA_GPIO_IN_ADDR, 271 271 - regs + MPA_GPIO_OUT_ADDR, NULL, 272 272 - regs + MPA_GPIO_OE_ADDR, NULL, 0); 266 266 + config = (struct gpio_generic_chip_config) { 267 267 + .dev = &pdev->dev, 268 268 + .sz = 4, 269 269 + .dat = regs + MPA_GPIO_IN_ADDR, 270 270 + .set = regs + MPA_GPIO_OUT_ADDR, 271 271 + .dirout = regs + MPA_GPIO_OE_ADDR, 272 272 + }; 273 273 + 274 274 + ret = gpio_generic_chip_init(&priv->chip, &config); 273 275 if (ret) 274 276 return ret; 275 277 276 276 - priv->gc.to_irq = xgene_gpio_sb_to_irq; 278 278 + priv->chip.gc.to_irq = xgene_gpio_sb_to_irq; 277 279 278 280 /* Retrieve start irq pin, use default if property not found */ 279 281 priv->irq_start = XGENE_DFLT_IRQ_START_PIN; ··· 291 283 priv->nirq = val32; 292 284 293 285 /* Retrieve number gpio, use default if property not found */ 294 294 - priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO; 286 286 + priv->chip.gc.ngpio = XGENE_DFLT_MAX_NGPIO; 295 287 if (!device_property_read_u32(&pdev->dev, "apm,nr-gpios", &val32)) 296 296 - priv->gc.ngpio = val32; 288 288 + priv->chip.gc.ngpio = val32; 297 289 298 290 dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n", 299 299 - priv->gc.ngpio, priv->nirq, priv->irq_start); 291 291 + priv->chip.gc.ngpio, priv->nirq, priv->irq_start); 300 292 301 293 platform_set_drvdata(pdev, priv); 302 294 ··· 306 298 if (!priv->irq_domain) 307 299 return -ENODEV; 308 300 309 309 - priv->gc.irq.domain = priv->irq_domain; 301 301 + priv->chip.gc.irq.domain = priv->irq_domain; 310 302 311 311 - ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv); 303 303 + ret = devm_gpiochip_add_data(&pdev->dev, &priv->chip.gc, priv); 312 304 if (ret) { 313 305 dev_err(&pdev->dev, 314 306 "failed to register X-Gene GPIO Standby driver\n"); ··· 319 311 dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n"); 320 312 321 313 /* Register interrupt handlers for GPIO signaled ACPI Events */ 322 322 - acpi_gpiochip_request_interrupts(&priv->gc); 314 314 + acpi_gpiochip_request_interrupts(&priv->chip.gc); 323 315 324 316 return ret; 325 317 } ··· 328 320 { 329 321 struct xgene_gpio_sb *priv = platform_get_drvdata(pdev); 330 322 331 331 - acpi_gpiochip_free_interrupts(&priv->gc); 323 323 + acpi_gpiochip_free_interrupts(&priv->chip.gc); 332 324 333 325 irq_domain_remove(priv->irq_domain); 334 326 }

+19 -15

drivers/gpio/gpio-xgs-iproc.c

reviewed

··· 3 3 * Copyright (C) 2017 Broadcom 4 4 */ 5 5 6 6 - #include <linux/gpio/driver.h> 7 6 #include <linux/init.h> 8 7 #include <linux/interrupt.h> 9 8 #include <linux/io.h> 10 9 #include <linux/irq.h> 10 10 + #include <linux/gpio/driver.h> 11 11 + #include <linux/gpio/generic.h> 11 12 #include <linux/kernel.h> 12 13 #include <linux/module.h> 13 14 #include <linux/platform_device.h> ··· 29 28 #define IPROC_GPIO_CCA_INT_EDGE 0x24 30 29 31 30 struct iproc_gpio_chip { 32 32 - struct gpio_chip gc; 31 31 + struct gpio_generic_chip gen_gc; 33 32 spinlock_t lock; 34 33 struct device *dev; 35 34 void __iomem *base; ··· 39 38 static inline struct iproc_gpio_chip * 40 39 to_iproc_gpio(struct gpio_chip *gc) 41 40 { 42 42 - return container_of(gc, struct iproc_gpio_chip, gc); 41 41 + return container_of(to_gpio_generic_chip(gc), struct iproc_gpio_chip, gen_gc); 43 42 } 44 43 45 44 static void iproc_gpio_irq_ack(struct irq_data *d) ··· 214 213 215 214 static int iproc_gpio_probe(struct platform_device *pdev) 216 215 { 216 216 + struct gpio_generic_chip_config config; 217 217 struct device *dev = &pdev->dev; 218 218 struct device_node *dn = pdev->dev.of_node; 219 219 struct iproc_gpio_chip *chip; ··· 233 231 if (IS_ERR(chip->base)) 234 232 return PTR_ERR(chip->base); 235 233 236 236 - ret = bgpio_init(&chip->gc, dev, 4, 237 237 - chip->base + IPROC_GPIO_CCA_DIN, 238 238 - chip->base + IPROC_GPIO_CCA_DOUT, 239 239 - NULL, 240 240 - chip->base + IPROC_GPIO_CCA_OUT_EN, 241 241 - NULL, 242 242 - 0); 234 234 + config = (struct gpio_generic_chip_config) { 235 235 + .dev = dev, 236 236 + .sz = 4, 237 237 + .dat = chip->base + IPROC_GPIO_CCA_DIN, 238 238 + .set = chip->base + IPROC_GPIO_CCA_DOUT, 239 239 + .dirout = chip->base + IPROC_GPIO_CCA_OUT_EN, 240 240 + }; 241 241 + 242 242 + ret = gpio_generic_chip_init(&chip->gen_gc, &config); 243 243 if (ret) { 244 244 dev_err(dev, "unable to init GPIO chip\n"); 245 245 return ret; 246 246 } 247 247 248 248 - chip->gc.label = dev_name(dev); 248 248 + chip->gen_gc.gc.label = dev_name(dev); 249 249 if (!of_property_read_u32(dn, "ngpios", &num_gpios)) 250 250 - chip->gc.ngpio = num_gpios; 250 250 + chip->gen_gc.gc.ngpio = num_gpios; 251 251 252 252 irq = platform_get_irq(pdev, 0); 253 253 if (irq > 0) { ··· 270 266 * a flow-handler because the irq is shared. 271 267 */ 272 268 ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler, 273 273 - IRQF_SHARED, chip->gc.label, &chip->gc); 269 269 + IRQF_SHARED, chip->gen_gc.gc.label, &chip->gen_gc.gc); 274 270 if (ret) { 275 271 dev_err(dev, "Fail to request IRQ%d: %d\n", irq, ret); 276 272 return ret; 277 273 } 278 274 279 279 - girq = &chip->gc.irq; 275 275 + girq = &chip->gen_gc.gc.irq; 280 276 gpio_irq_chip_set_chip(girq, &iproc_gpio_irq_chip); 281 277 /* This will let us handle the parent IRQ in the driver */ 282 278 girq->parent_handler = NULL; ··· 286 282 girq->handler = handle_simple_irq; 287 283 } 288 284 289 289 - ret = devm_gpiochip_add_data(dev, &chip->gc, chip); 285 285 + ret = devm_gpiochip_add_data(dev, &chip->gen_gc.gc, chip); 290 286 if (ret) { 291 287 dev_err(dev, "unable to add GPIO chip\n"); 292 288 return ret;

+1 -2

drivers/gpio/gpio-xra1403.c

reviewed

··· 135 135 gcr = value[XRA_GCR + 1] << 8 | value[XRA_GCR]; 136 136 gsr = value[XRA_GSR + 1] << 8 | value[XRA_GSR]; 137 137 for_each_requested_gpio(chip, i, label) { 138 138 - seq_printf(s, " gpio-%-3d (%-12s) %s %s\n", 139 139 - chip->base + i, label, 138 138 + seq_printf(s, " gpio-%-3d (%-12s) %s %s\n", i, label, 140 139 (gcr & BIT(i)) ? "in" : "out", 141 140 str_hi_lo(gsr & BIT(i))); 142 141 }

+45 -45

drivers/gpio/gpiolib-cdev.c

reviewed

··· 144 144 { 145 145 unsigned long flags = READ_ONCE(*flagsp); 146 146 147 147 - assign_bit(FLAG_ACTIVE_LOW, &flags, 147 147 + assign_bit(GPIOD_FLAG_ACTIVE_LOW, &flags, 148 148 lflags & GPIOHANDLE_REQUEST_ACTIVE_LOW); 149 149 - assign_bit(FLAG_OPEN_DRAIN, &flags, 149 149 + assign_bit(GPIOD_FLAG_OPEN_DRAIN, &flags, 150 150 lflags & GPIOHANDLE_REQUEST_OPEN_DRAIN); 151 151 - assign_bit(FLAG_OPEN_SOURCE, &flags, 151 151 + assign_bit(GPIOD_FLAG_OPEN_SOURCE, &flags, 152 152 lflags & GPIOHANDLE_REQUEST_OPEN_SOURCE); 153 153 - assign_bit(FLAG_PULL_UP, &flags, 153 153 + assign_bit(GPIOD_FLAG_PULL_UP, &flags, 154 154 lflags & GPIOHANDLE_REQUEST_BIAS_PULL_UP); 155 155 - assign_bit(FLAG_PULL_DOWN, &flags, 155 155 + assign_bit(GPIOD_FLAG_PULL_DOWN, &flags, 156 156 lflags & GPIOHANDLE_REQUEST_BIAS_PULL_DOWN); 157 157 - assign_bit(FLAG_BIAS_DISABLE, &flags, 157 157 + assign_bit(GPIOD_FLAG_BIAS_DISABLE, &flags, 158 158 lflags & GPIOHANDLE_REQUEST_BIAS_DISABLE); 159 159 160 160 WRITE_ONCE(*flagsp, flags); ··· 238 238 * All line descriptors were created at once with the same 239 239 * flags so just check if the first one is really output. 240 240 */ 241 241 - if (!test_bit(FLAG_IS_OUT, &lh->descs[0]->flags)) 241 241 + if (!test_bit(GPIOD_FLAG_IS_OUT, &lh->descs[0]->flags)) 242 242 return -EPERM; 243 243 244 244 if (copy_from_user(&ghd, ip, sizeof(ghd))) ··· 599 599 600 600 static u64 line_event_timestamp(struct line *line) 601 601 { 602 602 - if (test_bit(FLAG_EVENT_CLOCK_REALTIME, &line->desc->flags)) 602 602 + if (test_bit(GPIOD_FLAG_EVENT_CLOCK_REALTIME, &line->desc->flags)) 603 603 return ktime_get_real_ns(); 604 604 else if (IS_ENABLED(CONFIG_HTE) && 605 605 - test_bit(FLAG_EVENT_CLOCK_HTE, &line->desc->flags)) 605 605 + test_bit(GPIOD_FLAG_EVENT_CLOCK_HTE, &line->desc->flags)) 606 606 return line->timestamp_ns; 607 607 608 608 return ktime_get_ns(); ··· 725 725 struct hte_ts_desc *hdesc = &line->hdesc; 726 726 727 727 if (eflags & GPIO_V2_LINE_FLAG_EDGE_RISING) 728 728 - flags |= test_bit(FLAG_ACTIVE_LOW, &line->desc->flags) ? 728 728 + flags |= test_bit(GPIOD_FLAG_ACTIVE_LOW, &line->desc->flags) ? 729 729 HTE_FALLING_EDGE_TS : 730 730 HTE_RISING_EDGE_TS; 731 731 if (eflags & GPIO_V2_LINE_FLAG_EDGE_FALLING) 732 732 - flags |= test_bit(FLAG_ACTIVE_LOW, &line->desc->flags) ? 732 732 + flags |= test_bit(GPIOD_FLAG_ACTIVE_LOW, &line->desc->flags) ? 733 733 HTE_RISING_EDGE_TS : 734 734 HTE_FALLING_EDGE_TS; 735 735 ··· 831 831 */ 832 832 value = READ_ONCE(line->level); 833 833 834 834 - if (test_bit(FLAG_ACTIVE_LOW, &line->desc->flags)) 834 834 + if (test_bit(GPIOD_FLAG_ACTIVE_LOW, &line->desc->flags)) 835 835 value = !value; 836 836 837 837 return value; ··· 939 939 return level; 940 940 941 941 if (!(IS_ENABLED(CONFIG_HTE) && 942 942 - test_bit(FLAG_EVENT_CLOCK_HTE, &line->desc->flags))) { 942 942 + test_bit(GPIOD_FLAG_EVENT_CLOCK_HTE, &line->desc->flags))) { 943 943 irq = gpiod_to_irq(line->desc); 944 944 if (irq < 0) 945 945 return -ENXIO; ··· 1061 1061 return -ENXIO; 1062 1062 1063 1063 if (eflags & GPIO_V2_LINE_FLAG_EDGE_RISING) 1064 1064 - irqflags |= test_bit(FLAG_ACTIVE_LOW, &line->desc->flags) ? 1064 1064 + irqflags |= test_bit(GPIOD_FLAG_ACTIVE_LOW, &line->desc->flags) ? 1065 1065 IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING; 1066 1066 if (eflags & GPIO_V2_LINE_FLAG_EDGE_FALLING) 1067 1067 - irqflags |= test_bit(FLAG_ACTIVE_LOW, &line->desc->flags) ? 1067 1067 + irqflags |= test_bit(GPIOD_FLAG_ACTIVE_LOW, &line->desc->flags) ? 1068 1068 IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING; 1069 1069 irqflags |= IRQF_ONESHOT; 1070 1070 ··· 1237 1237 { 1238 1238 unsigned long flags = READ_ONCE(*flagsp); 1239 1239 1240 1240 - assign_bit(FLAG_ACTIVE_LOW, &flags, 1240 1240 + assign_bit(GPIOD_FLAG_ACTIVE_LOW, &flags, 1241 1241 lflags & GPIO_V2_LINE_FLAG_ACTIVE_LOW); 1242 1242 1243 1243 if (lflags & GPIO_V2_LINE_FLAG_OUTPUT) 1244 1244 - set_bit(FLAG_IS_OUT, &flags); 1244 1244 + set_bit(GPIOD_FLAG_IS_OUT, &flags); 1245 1245 else if (lflags & GPIO_V2_LINE_FLAG_INPUT) 1246 1246 - clear_bit(FLAG_IS_OUT, &flags); 1246 1246 + clear_bit(GPIOD_FLAG_IS_OUT, &flags); 1247 1247 1248 1248 - assign_bit(FLAG_EDGE_RISING, &flags, 1248 1248 + assign_bit(GPIOD_FLAG_EDGE_RISING, &flags, 1249 1249 lflags & GPIO_V2_LINE_FLAG_EDGE_RISING); 1250 1250 - assign_bit(FLAG_EDGE_FALLING, &flags, 1250 1250 + assign_bit(GPIOD_FLAG_EDGE_FALLING, &flags, 1251 1251 lflags & GPIO_V2_LINE_FLAG_EDGE_FALLING); 1252 1252 1253 1253 - assign_bit(FLAG_OPEN_DRAIN, &flags, 1253 1253 + assign_bit(GPIOD_FLAG_OPEN_DRAIN, &flags, 1254 1254 lflags & GPIO_V2_LINE_FLAG_OPEN_DRAIN); 1255 1255 - assign_bit(FLAG_OPEN_SOURCE, &flags, 1255 1255 + assign_bit(GPIOD_FLAG_OPEN_SOURCE, &flags, 1256 1256 lflags & GPIO_V2_LINE_FLAG_OPEN_SOURCE); 1257 1257 1258 1258 - assign_bit(FLAG_PULL_UP, &flags, 1258 1258 + assign_bit(GPIOD_FLAG_PULL_UP, &flags, 1259 1259 lflags & GPIO_V2_LINE_FLAG_BIAS_PULL_UP); 1260 1260 - assign_bit(FLAG_PULL_DOWN, &flags, 1260 1260 + assign_bit(GPIOD_FLAG_PULL_DOWN, &flags, 1261 1261 lflags & GPIO_V2_LINE_FLAG_BIAS_PULL_DOWN); 1262 1262 - assign_bit(FLAG_BIAS_DISABLE, &flags, 1262 1262 + assign_bit(GPIOD_FLAG_BIAS_DISABLE, &flags, 1263 1263 lflags & GPIO_V2_LINE_FLAG_BIAS_DISABLED); 1264 1264 1265 1265 - assign_bit(FLAG_EVENT_CLOCK_REALTIME, &flags, 1265 1265 + assign_bit(GPIOD_FLAG_EVENT_CLOCK_REALTIME, &flags, 1266 1266 lflags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME); 1267 1267 - assign_bit(FLAG_EVENT_CLOCK_HTE, &flags, 1267 1267 + assign_bit(GPIOD_FLAG_EVENT_CLOCK_HTE, &flags, 1268 1268 lflags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE); 1269 1269 1270 1270 WRITE_ONCE(*flagsp, flags); ··· 2115 2115 } 2116 2116 2117 2117 if (eflags & GPIOEVENT_REQUEST_RISING_EDGE) 2118 2118 - irqflags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ? 2118 2118 + irqflags |= test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags) ? 2119 2119 IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING; 2120 2120 if (eflags & GPIOEVENT_REQUEST_FALLING_EDGE) 2121 2121 - irqflags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ? 2121 2121 + irqflags |= test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags) ? 2122 2122 IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING; 2123 2123 irqflags |= IRQF_ONESHOT; 2124 2124 ··· 2253 2253 2254 2254 scoped_guard(srcu, &desc->gdev->desc_srcu) { 2255 2255 label = gpiod_get_label(desc); 2256 2256 - if (label && test_bit(FLAG_REQUESTED, &dflags)) 2256 2256 + if (label && test_bit(GPIOD_FLAG_REQUESTED, &dflags)) 2257 2257 strscpy(info->consumer, label, 2258 2258 sizeof(info->consumer)); 2259 2259 } ··· 2270 2270 * The definitive test that a line is available to userspace is to 2271 2271 * request it. 2272 2272 */ 2273 2273 - if (test_bit(FLAG_REQUESTED, &dflags) || 2274 2274 - test_bit(FLAG_IS_HOGGED, &dflags) || 2275 2275 - test_bit(FLAG_EXPORT, &dflags) || 2276 2276 - test_bit(FLAG_SYSFS, &dflags) || 2273 2273 + if (test_bit(GPIOD_FLAG_REQUESTED, &dflags) || 2274 2274 + test_bit(GPIOD_FLAG_IS_HOGGED, &dflags) || 2275 2275 + test_bit(GPIOD_FLAG_EXPORT, &dflags) || 2276 2276 + test_bit(GPIOD_FLAG_SYSFS, &dflags) || 2277 2277 !gpiochip_line_is_valid(guard.gc, info->offset)) { 2278 2278 info->flags |= GPIO_V2_LINE_FLAG_USED; 2279 2279 } else if (!atomic) { ··· 2281 2281 info->flags |= GPIO_V2_LINE_FLAG_USED; 2282 2282 } 2283 2283 2284 2284 - if (test_bit(FLAG_IS_OUT, &dflags)) 2284 2284 + if (test_bit(GPIOD_FLAG_IS_OUT, &dflags)) 2285 2285 info->flags |= GPIO_V2_LINE_FLAG_OUTPUT; 2286 2286 else 2287 2287 info->flags |= GPIO_V2_LINE_FLAG_INPUT; 2288 2288 2289 2289 - if (test_bit(FLAG_ACTIVE_LOW, &dflags)) 2289 2289 + if (test_bit(GPIOD_FLAG_ACTIVE_LOW, &dflags)) 2290 2290 info->flags |= GPIO_V2_LINE_FLAG_ACTIVE_LOW; 2291 2291 2292 2292 - if (test_bit(FLAG_OPEN_DRAIN, &dflags)) 2292 2292 + if (test_bit(GPIOD_FLAG_OPEN_DRAIN, &dflags)) 2293 2293 info->flags |= GPIO_V2_LINE_FLAG_OPEN_DRAIN; 2294 2294 - if (test_bit(FLAG_OPEN_SOURCE, &dflags)) 2294 2294 + if (test_bit(GPIOD_FLAG_OPEN_SOURCE, &dflags)) 2295 2295 info->flags |= GPIO_V2_LINE_FLAG_OPEN_SOURCE; 2296 2296 2297 2297 - if (test_bit(FLAG_BIAS_DISABLE, &dflags)) 2297 2297 + if (test_bit(GPIOD_FLAG_BIAS_DISABLE, &dflags)) 2298 2298 info->flags |= GPIO_V2_LINE_FLAG_BIAS_DISABLED; 2299 2299 - if (test_bit(FLAG_PULL_DOWN, &dflags)) 2299 2299 + if (test_bit(GPIOD_FLAG_PULL_DOWN, &dflags)) 2300 2300 info->flags |= GPIO_V2_LINE_FLAG_BIAS_PULL_DOWN; 2301 2301 - if (test_bit(FLAG_PULL_UP, &dflags)) 2301 2301 + if (test_bit(GPIOD_FLAG_PULL_UP, &dflags)) 2302 2302 info->flags |= GPIO_V2_LINE_FLAG_BIAS_PULL_UP; 2303 2303 2304 2304 - if (test_bit(FLAG_EDGE_RISING, &dflags)) 2304 2304 + if (test_bit(GPIOD_FLAG_EDGE_RISING, &dflags)) 2305 2305 info->flags |= GPIO_V2_LINE_FLAG_EDGE_RISING; 2306 2306 - if (test_bit(FLAG_EDGE_FALLING, &dflags)) 2306 2306 + if (test_bit(GPIOD_FLAG_EDGE_FALLING, &dflags)) 2307 2307 info->flags |= GPIO_V2_LINE_FLAG_EDGE_FALLING; 2308 2308 2309 2309 - if (test_bit(FLAG_EVENT_CLOCK_REALTIME, &dflags)) 2309 2309 + if (test_bit(GPIOD_FLAG_EVENT_CLOCK_REALTIME, &dflags)) 2310 2310 info->flags |= GPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME; 2311 2311 - else if (test_bit(FLAG_EVENT_CLOCK_HTE, &dflags)) 2311 2311 + else if (test_bit(GPIOD_FLAG_EVENT_CLOCK_HTE, &dflags)) 2312 2312 info->flags |= GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE; 2313 2313 2314 2314 debounce_period_us = READ_ONCE(desc->debounce_period_us);

+1 -1

drivers/gpio/gpiolib-of.c

reviewed

··· 878 878 { 879 879 struct gpio_desc *desc; 880 880 881 881 - for_each_gpio_desc_with_flag(chip, desc, FLAG_IS_HOGGED) 881 881 + for_each_gpio_desc_with_flag(chip, desc, GPIOD_FLAG_IS_HOGGED) 882 882 if (READ_ONCE(desc->hog) == hog) 883 883 gpiochip_free_own_desc(desc); 884 884 }

+23 -23

drivers/gpio/gpiolib-sysfs.c

reviewed

··· 131 131 132 132 scoped_guard(mutex, &data->mutex) { 133 133 gpiod_get_direction(desc); 134 134 - value = !!test_bit(FLAG_IS_OUT, &desc->flags); 134 134 + value = !!test_bit(GPIOD_FLAG_IS_OUT, &desc->flags); 135 135 } 136 136 137 137 return sysfs_emit(buf, "%s\n", value ? "out" : "in"); ··· 226 226 227 227 irq_flags = IRQF_SHARED; 228 228 if (flags & GPIO_IRQF_TRIGGER_FALLING) { 229 229 - irq_flags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ? 229 229 + irq_flags |= test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags) ? 230 230 IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING; 231 231 - set_bit(FLAG_EDGE_FALLING, &desc->flags); 231 231 + set_bit(GPIOD_FLAG_EDGE_FALLING, &desc->flags); 232 232 } 233 233 if (flags & GPIO_IRQF_TRIGGER_RISING) { 234 234 - irq_flags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ? 234 234 + irq_flags |= test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags) ? 235 235 IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING; 236 236 - set_bit(FLAG_EDGE_RISING, &desc->flags); 236 236 + set_bit(GPIOD_FLAG_EDGE_RISING, &desc->flags); 237 237 } 238 238 239 239 /* ··· 260 260 err_unlock: 261 261 gpiochip_unlock_as_irq(guard.gc, gpio_chip_hwgpio(desc)); 262 262 err_clr_bits: 263 263 - clear_bit(FLAG_EDGE_RISING, &desc->flags); 264 264 - clear_bit(FLAG_EDGE_FALLING, &desc->flags); 263 263 + clear_bit(GPIOD_FLAG_EDGE_RISING, &desc->flags); 264 264 + clear_bit(GPIOD_FLAG_EDGE_FALLING, &desc->flags); 265 265 266 266 return ret; 267 267 } ··· 281 281 data->irq_flags = 0; 282 282 free_irq(data->irq, data); 283 283 gpiochip_unlock_as_irq(guard.gc, gpio_chip_hwgpio(desc)); 284 284 - clear_bit(FLAG_EDGE_RISING, &desc->flags); 285 285 - clear_bit(FLAG_EDGE_FALLING, &desc->flags); 284 284 + clear_bit(GPIOD_FLAG_EDGE_RISING, &desc->flags); 285 285 + clear_bit(GPIOD_FLAG_EDGE_FALLING, &desc->flags); 286 286 } 287 287 288 288 static const char *const trigger_names[] = { ··· 347 347 struct gpio_desc *desc = data->desc; 348 348 int status = 0; 349 349 350 350 - if (!!test_bit(FLAG_ACTIVE_LOW, &desc->flags) == !!value) 350 350 + if (!!test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags) == !!value) 351 351 return 0; 352 352 353 353 - assign_bit(FLAG_ACTIVE_LOW, &desc->flags, value); 353 353 + assign_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags, value); 354 354 355 355 /* reconfigure poll(2) support if enabled on one edge only */ 356 356 if (flags == GPIO_IRQF_TRIGGER_FALLING || ··· 373 373 int value; 374 374 375 375 scoped_guard(mutex, &data->mutex) 376 376 - value = !!test_bit(FLAG_ACTIVE_LOW, &desc->flags); 376 376 + value = !!test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags); 377 377 378 378 return sysfs_emit(buf, "%d\n", value); 379 379 } ··· 418 418 mode = 0; 419 419 420 420 if (!data->direction_can_change && 421 421 - test_bit(FLAG_IS_OUT, &data->desc->flags)) 421 421 + test_bit(GPIOD_FLAG_IS_OUT, &data->desc->flags)) 422 422 mode = 0; 423 423 #endif /* CONFIG_GPIO_SYSFS_LEGACY */ 424 424 } ··· 486 486 } 487 487 488 488 /* 489 489 - * No extra locking here; FLAG_SYSFS just signifies that the 489 489 + * No extra locking here; GPIOD_FLAG_SYSFS just signifies that the 490 490 * request and export were done by on behalf of userspace, so 491 491 * they may be undone on its behalf too. 492 492 */ ··· 505 505 if (ret < 0) { 506 506 gpiod_free(desc); 507 507 } else { 508 508 - set_bit(FLAG_SYSFS, &desc->flags); 508 508 + set_bit(GPIOD_FLAG_SYSFS, &desc->flags); 509 509 gpiod_line_state_notify(desc, GPIO_V2_LINE_CHANGED_REQUESTED); 510 510 } 511 511 ··· 515 515 static int unexport_gpio_desc(struct gpio_desc *desc) 516 516 { 517 517 /* 518 518 - * No extra locking here; FLAG_SYSFS just signifies that the 518 518 + * No extra locking here; GPIOD_FLAG_SYSFS just signifies that the 519 519 * request and export were done by on behalf of userspace, so 520 520 * they may be undone on its behalf too. 521 521 */ 522 522 - if (!test_and_clear_bit(FLAG_SYSFS, &desc->flags)) 522 522 + if (!test_and_clear_bit(GPIOD_FLAG_SYSFS, &desc->flags)) 523 523 return -EINVAL; 524 524 525 525 gpiod_unexport(desc); ··· 748 748 if (!guard.gc) 749 749 return -ENODEV; 750 750 751 751 - if (test_and_set_bit(FLAG_EXPORT, &desc->flags)) 751 751 + if (test_and_set_bit(GPIOD_FLAG_EXPORT, &desc->flags)) 752 752 return -EPERM; 753 753 754 754 gdev = desc->gdev; 755 755 756 756 guard(mutex)(&sysfs_lock); 757 757 758 758 - if (!test_bit(FLAG_REQUESTED, &desc->flags)) { 758 758 + if (!test_bit(GPIOD_FLAG_REQUESTED, &desc->flags)) { 759 759 gpiod_dbg(desc, "%s: unavailable (not requested)\n", __func__); 760 760 status = -EPERM; 761 761 goto err_clear_bit; ··· 866 866 #endif /* CONFIG_GPIO_SYSFS_LEGACY */ 867 867 kfree(desc_data); 868 868 err_clear_bit: 869 869 - clear_bit(FLAG_EXPORT, &desc->flags); 869 869 + clear_bit(GPIOD_FLAG_EXPORT, &desc->flags); 870 870 gpiod_dbg(desc, "%s: status %d\n", __func__, status); 871 871 return status; 872 872 } ··· 937 937 } 938 938 939 939 scoped_guard(mutex, &sysfs_lock) { 940 940 - if (!test_bit(FLAG_EXPORT, &desc->flags)) 940 940 + if (!test_bit(GPIOD_FLAG_EXPORT, &desc->flags)) 941 941 return; 942 942 943 943 gdev = gpiod_to_gpio_device(desc); ··· 956 956 return; 957 957 958 958 list_del(&desc_data->list); 959 959 - clear_bit(FLAG_EXPORT, &desc->flags); 959 959 + clear_bit(GPIOD_FLAG_EXPORT, &desc->flags); 960 960 #if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY) 961 961 sysfs_put(desc_data->value_kn); 962 962 device_unregister(desc_data->dev); ··· 1073 1073 return; 1074 1074 1075 1075 /* unregister gpiod class devices owned by sysfs */ 1076 1076 - for_each_gpio_desc_with_flag(chip, desc, FLAG_SYSFS) { 1076 1076 + for_each_gpio_desc_with_flag(chip, desc, GPIOD_FLAG_SYSFS) { 1077 1077 gpiod_unexport(desc); 1078 1078 gpiod_free(desc); 1079 1079 }

+103 -92

drivers/gpio/gpiolib.c

reviewed

··· 127 127 label = srcu_dereference_check(desc->label, &desc->gdev->desc_srcu, 128 128 srcu_read_lock_held(&desc->gdev->desc_srcu)); 129 129 130 130 - if (test_bit(FLAG_USED_AS_IRQ, &flags)) 130 130 + if (test_bit(GPIOD_FLAG_USED_AS_IRQ, &flags)) 131 131 return label ? label->str : "interrupt"; 132 132 133 133 - if (!test_bit(FLAG_REQUESTED, &flags)) 133 133 + if (!test_bit(GPIOD_FLAG_REQUESTED, &flags)) 134 134 return NULL; 135 135 136 136 return label ? label->str : NULL; ··· 450 450 * Open drain emulation using input mode may incorrectly report 451 451 * input here, fix that up. 452 452 */ 453 453 - if (test_bit(FLAG_OPEN_DRAIN, &flags) && 454 454 - test_bit(FLAG_IS_OUT, &flags)) 453 453 + if (test_bit(GPIOD_FLAG_OPEN_DRAIN, &flags) && 454 454 + test_bit(GPIOD_FLAG_IS_OUT, &flags)) 455 455 return 0; 456 456 457 457 if (!guard.gc->get_direction) ··· 468 468 if (ret > 0) 469 469 ret = 1; 470 470 471 471 - assign_bit(FLAG_IS_OUT, &flags, !ret); 471 471 + assign_bit(GPIOD_FLAG_IS_OUT, &flags, !ret); 472 472 WRITE_ONCE(desc->flags, flags); 473 473 474 474 return ret; ··· 846 846 { 847 847 struct gpio_desc *desc; 848 848 849 849 - for_each_gpio_desc_with_flag(gc, desc, FLAG_USED_AS_IRQ) 849 849 + for_each_gpio_desc_with_flag(gc, desc, GPIOD_FLAG_USED_AS_IRQ) 850 850 gpiod_free_irqs(desc); 851 851 } 852 852 ··· 1169 1169 * lock here. 1170 1170 */ 1171 1171 if (gc->get_direction && gpiochip_line_is_valid(gc, desc_index)) 1172 1172 - assign_bit(FLAG_IS_OUT, &desc->flags, 1172 1172 + assign_bit(GPIOD_FLAG_IS_OUT, &desc->flags, 1173 1173 !gc->get_direction(gc, desc_index)); 1174 1174 else 1175 1175 - assign_bit(FLAG_IS_OUT, 1175 1175 + assign_bit(GPIOD_FLAG_IS_OUT, 1176 1176 &desc->flags, !gc->direction_input); 1177 1177 } 1178 1178 ··· 2349 2349 EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range); 2350 2350 2351 2351 /** 2352 2352 - * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping 2352 2352 + * gpiochip_add_pin_range_with_pins() - add a range for GPIO <-> pin mapping 2353 2353 * @gc: the gpiochip to add the range for 2354 2354 * @pinctl_name: the dev_name() of the pin controller to map to 2355 2355 * @gpio_offset: the start offset in the current gpio_chip number space 2356 2356 * @pin_offset: the start offset in the pin controller number space 2357 2357 + * @pins: the list of non consecutive pins to accumulate in this range (if not 2358 2358 + * NULL, pin_offset is ignored by pinctrl core) 2357 2359 * @npins: the number of pins from the offset of each pin space (GPIO and 2358 2360 * pin controller) to accumulate in this range 2359 2361 * ··· 2367 2365 * Returns: 2368 2366 * 0 on success, or a negative errno on failure. 2369 2367 */ 2370 2370 - int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 2371 2371 - unsigned int gpio_offset, unsigned int pin_offset, 2372 2372 - unsigned int npins) 2368 2368 + int gpiochip_add_pin_range_with_pins(struct gpio_chip *gc, 2369 2369 + const char *pinctl_name, 2370 2370 + unsigned int gpio_offset, 2371 2371 + unsigned int pin_offset, 2372 2372 + unsigned int const *pins, 2373 2373 + unsigned int npins) 2373 2374 { 2374 2375 struct gpio_pin_range *pin_range; 2375 2376 struct gpio_device *gdev = gc->gpiodev; ··· 2390 2385 pin_range->range.name = gc->label; 2391 2386 pin_range->range.base = gdev->base + gpio_offset; 2392 2387 pin_range->range.pin_base = pin_offset; 2388 2388 + pin_range->range.pins = pins; 2393 2389 pin_range->range.npins = npins; 2394 2390 pin_range->pctldev = pinctrl_find_and_add_gpio_range(pinctl_name, 2395 2391 &pin_range->range); ··· 2400 2394 kfree(pin_range); 2401 2395 return ret; 2402 2396 } 2403 2403 - chip_dbg(gc, "created GPIO range %d->%d ==> %s PIN %d->%d\n", 2404 2404 - gpio_offset, gpio_offset + npins - 1, 2405 2405 - pinctl_name, 2406 2406 - pin_offset, pin_offset + npins - 1); 2397 2397 + if (pin_range->range.pins) 2398 2398 + chip_dbg(gc, "created GPIO range %d->%d ==> %s %d sparse PIN range { %d, ... }", 2399 2399 + gpio_offset, gpio_offset + npins - 1, 2400 2400 + pinctl_name, npins, pins[0]); 2401 2401 + else 2402 2402 + chip_dbg(gc, "created GPIO range %d->%d ==> %s PIN %d->%d\n", 2403 2403 + gpio_offset, gpio_offset + npins - 1, 2404 2404 + pinctl_name, 2405 2405 + pin_offset, pin_offset + npins - 1); 2407 2406 2408 2407 list_add_tail(&pin_range->node, &gdev->pin_ranges); 2409 2408 2410 2409 return 0; 2411 2410 } 2412 2412 - EXPORT_SYMBOL_GPL(gpiochip_add_pin_range); 2411 2411 + EXPORT_SYMBOL_GPL(gpiochip_add_pin_range_with_pins); 2413 2412 2414 2413 /** 2415 2414 * gpiochip_remove_pin_ranges() - remove all the GPIO <-> pin mappings ··· 2449 2438 if (!guard.gc) 2450 2439 return -ENODEV; 2451 2440 2452 2452 - if (test_and_set_bit(FLAG_REQUESTED, &desc->flags)) 2441 2441 + if (test_and_set_bit(GPIOD_FLAG_REQUESTED, &desc->flags)) 2453 2442 return -EBUSY; 2454 2443 2455 2444 offset = gpio_chip_hwgpio(desc); ··· 2478 2467 return 0; 2479 2468 2480 2469 out_clear_bit: 2481 2481 - clear_bit(FLAG_REQUESTED, &desc->flags); 2470 2470 + clear_bit(GPIOD_FLAG_REQUESTED, &desc->flags); 2482 2471 return ret; 2483 2472 } 2484 2473 ··· 2512 2501 2513 2502 flags = READ_ONCE(desc->flags); 2514 2503 2515 2515 - if (guard.gc && test_bit(FLAG_REQUESTED, &flags)) { 2504 2504 + if (guard.gc && test_bit(GPIOD_FLAG_REQUESTED, &flags)) { 2516 2505 if (guard.gc->free) 2517 2506 guard.gc->free(guard.gc, gpio_chip_hwgpio(desc)); 2518 2507 2519 2519 - clear_bit(FLAG_ACTIVE_LOW, &flags); 2520 2520 - clear_bit(FLAG_REQUESTED, &flags); 2521 2521 - clear_bit(FLAG_OPEN_DRAIN, &flags); 2522 2522 - clear_bit(FLAG_OPEN_SOURCE, &flags); 2523 2523 - clear_bit(FLAG_PULL_UP, &flags); 2524 2524 - clear_bit(FLAG_PULL_DOWN, &flags); 2525 2525 - clear_bit(FLAG_BIAS_DISABLE, &flags); 2526 2526 - clear_bit(FLAG_EDGE_RISING, &flags); 2527 2527 - clear_bit(FLAG_EDGE_FALLING, &flags); 2528 2528 - clear_bit(FLAG_IS_HOGGED, &flags); 2508 2508 + clear_bit(GPIOD_FLAG_ACTIVE_LOW, &flags); 2509 2509 + clear_bit(GPIOD_FLAG_REQUESTED, &flags); 2510 2510 + clear_bit(GPIOD_FLAG_OPEN_DRAIN, &flags); 2511 2511 + clear_bit(GPIOD_FLAG_OPEN_SOURCE, &flags); 2512 2512 + clear_bit(GPIOD_FLAG_PULL_UP, &flags); 2513 2513 + clear_bit(GPIOD_FLAG_PULL_DOWN, &flags); 2514 2514 + clear_bit(GPIOD_FLAG_BIAS_DISABLE, &flags); 2515 2515 + clear_bit(GPIOD_FLAG_EDGE_RISING, &flags); 2516 2516 + clear_bit(GPIOD_FLAG_EDGE_FALLING, &flags); 2517 2517 + clear_bit(GPIOD_FLAG_IS_HOGGED, &flags); 2529 2518 #ifdef CONFIG_OF_DYNAMIC 2530 2519 WRITE_ONCE(desc->hog, NULL); 2531 2520 #endif ··· 2568 2557 if (IS_ERR(desc)) 2569 2558 return NULL; 2570 2559 2571 2571 - if (!test_bit(FLAG_REQUESTED, &desc->flags)) 2560 2560 + if (!test_bit(GPIOD_FLAG_REQUESTED, &desc->flags)) 2572 2561 return NULL; 2573 2562 2574 2563 guard(srcu)(&desc->gdev->desc_srcu); ··· 2736 2725 2737 2726 flags = READ_ONCE(desc->flags); 2738 2727 2739 2739 - if (test_bit(FLAG_BIAS_DISABLE, &flags)) 2728 2728 + if (test_bit(GPIOD_FLAG_BIAS_DISABLE, &flags)) 2740 2729 bias = PIN_CONFIG_BIAS_DISABLE; 2741 2741 - else if (test_bit(FLAG_PULL_UP, &flags)) 2730 2730 + else if (test_bit(GPIOD_FLAG_PULL_UP, &flags)) 2742 2731 bias = PIN_CONFIG_BIAS_PULL_UP; 2743 2743 - else if (test_bit(FLAG_PULL_DOWN, &flags)) 2732 2732 + else if (test_bit(GPIOD_FLAG_PULL_DOWN, &flags)) 2744 2733 bias = PIN_CONFIG_BIAS_PULL_DOWN; 2745 2734 else 2746 2735 return 0; ··· 2882 2871 } 2883 2872 } 2884 2873 if (ret == 0) { 2885 2885 - clear_bit(FLAG_IS_OUT, &desc->flags); 2874 2874 + clear_bit(GPIOD_FLAG_IS_OUT, &desc->flags); 2886 2875 ret = gpio_set_bias(desc); 2887 2876 } 2888 2877 ··· 2955 2944 } 2956 2945 2957 2946 if (!ret) 2958 2958 - set_bit(FLAG_IS_OUT, &desc->flags); 2947 2947 + set_bit(GPIOD_FLAG_IS_OUT, &desc->flags); 2959 2948 trace_gpio_value(desc_to_gpio(desc), 0, val); 2960 2949 trace_gpio_direction(desc_to_gpio(desc), 0, ret); 2961 2950 return ret; ··· 3021 3010 3022 3011 flags = READ_ONCE(desc->flags); 3023 3012 3024 3024 - if (test_bit(FLAG_ACTIVE_LOW, &flags)) 3013 3013 + if (test_bit(GPIOD_FLAG_ACTIVE_LOW, &flags)) 3025 3014 value = !value; 3026 3015 else 3027 3016 value = !!value; 3028 3017 3029 3018 /* GPIOs used for enabled IRQs shall not be set as output */ 3030 3030 - if (test_bit(FLAG_USED_AS_IRQ, &flags) && 3031 3031 - test_bit(FLAG_IRQ_IS_ENABLED, &flags)) { 3019 3019 + if (test_bit(GPIOD_FLAG_USED_AS_IRQ, &flags) && 3020 3020 + test_bit(GPIOD_FLAG_IRQ_IS_ENABLED, &flags)) { 3032 3021 gpiod_err(desc, 3033 3022 "%s: tried to set a GPIO tied to an IRQ as output\n", 3034 3023 __func__); 3035 3024 return -EIO; 3036 3025 } 3037 3026 3038 3038 - if (test_bit(FLAG_OPEN_DRAIN, &flags)) { 3027 3027 + if (test_bit(GPIOD_FLAG_OPEN_DRAIN, &flags)) { 3039 3028 /* First see if we can enable open drain in hardware */ 3040 3029 ret = gpio_set_config(desc, PIN_CONFIG_DRIVE_OPEN_DRAIN); 3041 3030 if (!ret) ··· 3043 3032 /* Emulate open drain by not actively driving the line high */ 3044 3033 if (value) 3045 3034 goto set_output_flag; 3046 3046 - } else if (test_bit(FLAG_OPEN_SOURCE, &flags)) { 3035 3035 + } else if (test_bit(GPIOD_FLAG_OPEN_SOURCE, &flags)) { 3047 3036 ret = gpio_set_config(desc, PIN_CONFIG_DRIVE_OPEN_SOURCE); 3048 3037 if (!ret) 3049 3038 goto set_output_value; ··· 3070 3059 * set the IS_OUT flag or otherwise we won't be able to set the line 3071 3060 * value anymore. 3072 3061 */ 3073 3073 - set_bit(FLAG_IS_OUT, &desc->flags); 3062 3062 + set_bit(GPIOD_FLAG_IS_OUT, &desc->flags); 3074 3063 return 0; 3075 3064 } 3076 3065 ··· 3210 3199 { 3211 3200 VALIDATE_DESC(desc); 3212 3201 /* 3213 3213 - * Handle FLAG_TRANSITORY first, enabling queries to gpiolib for 3202 3202 + * Handle GPIOD_FLAG_TRANSITORY first, enabling queries to gpiolib for 3214 3203 * persistence state. 3215 3204 */ 3216 3216 - assign_bit(FLAG_TRANSITORY, &desc->flags, transitory); 3205 3205 + assign_bit(GPIOD_FLAG_TRANSITORY, &desc->flags, transitory); 3217 3206 3218 3207 /* If the driver supports it, set the persistence state now */ 3219 3208 return gpio_set_config_with_argument_optional(desc, ··· 3231 3220 int gpiod_is_active_low(const struct gpio_desc *desc) 3232 3221 { 3233 3222 VALIDATE_DESC(desc); 3234 3234 - return test_bit(FLAG_ACTIVE_LOW, &desc->flags); 3223 3223 + return test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags); 3235 3224 } 3236 3225 EXPORT_SYMBOL_GPL(gpiod_is_active_low); 3237 3226 ··· 3242 3231 void gpiod_toggle_active_low(struct gpio_desc *desc) 3243 3232 { 3244 3233 VALIDATE_DESC_VOID(desc); 3245 3245 - change_bit(FLAG_ACTIVE_LOW, &desc->flags); 3234 3234 + change_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags); 3246 3235 gpiod_line_state_notify(desc, GPIO_V2_LINE_CHANGED_CONFIG); 3247 3236 } 3248 3237 EXPORT_SYMBOL_GPL(gpiod_toggle_active_low); ··· 3448 3437 int hwgpio = gpio_chip_hwgpio(desc); 3449 3438 int value = test_bit(hwgpio, bits); 3450 3439 3451 3451 - if (!raw && test_bit(FLAG_ACTIVE_LOW, &desc->flags)) 3440 3440 + if (!raw && test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags)) 3452 3441 value = !value; 3453 3442 __assign_bit(j, value_bitmap, value); 3454 3443 trace_gpio_value(desc_to_gpio(desc), 1, value); ··· 3510 3499 if (value < 0) 3511 3500 return value; 3512 3501 3513 3513 - if (test_bit(FLAG_ACTIVE_LOW, &desc->flags)) 3502 3502 + if (test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags)) 3514 3503 value = !value; 3515 3504 3516 3505 return value; ··· 3593 3582 } else { 3594 3583 ret = gpiochip_direction_output(guard.gc, offset, 0); 3595 3584 if (!ret) 3596 3596 - set_bit(FLAG_IS_OUT, &desc->flags); 3585 3585 + set_bit(GPIOD_FLAG_IS_OUT, &desc->flags); 3597 3586 } 3598 3587 trace_gpio_direction(desc_to_gpio(desc), value, ret); 3599 3588 if (ret < 0) ··· 3620 3609 if (value) { 3621 3610 ret = gpiochip_direction_output(guard.gc, offset, 1); 3622 3611 if (!ret) 3623 3623 - set_bit(FLAG_IS_OUT, &desc->flags); 3612 3612 + set_bit(GPIOD_FLAG_IS_OUT, &desc->flags); 3624 3613 } else { 3625 3614 ret = gpiochip_direction_input(guard.gc, offset); 3626 3615 } ··· 3635 3624 3636 3625 static int gpiod_set_raw_value_commit(struct gpio_desc *desc, bool value) 3637 3626 { 3638 3638 - if (unlikely(!test_bit(FLAG_IS_OUT, &desc->flags))) 3627 3627 + if (unlikely(!test_bit(GPIOD_FLAG_IS_OUT, &desc->flags))) 3639 3628 return -EPERM; 3640 3629 3641 3630 CLASS(gpio_chip_guard, guard)(desc); ··· 3705 3694 WARN_ON(array_info->gdev->can_sleep); 3706 3695 3707 3696 for (i = 0; i < array_size; i++) { 3708 3708 - if (unlikely(!test_bit(FLAG_IS_OUT, 3697 3697 + if (unlikely(!test_bit(GPIOD_FLAG_IS_OUT, 3709 3698 &desc_array[i]->flags))) 3710 3699 return -EPERM; 3711 3700 } ··· 3769 3758 int hwgpio = gpio_chip_hwgpio(desc); 3770 3759 int value = test_bit(i, value_bitmap); 3771 3760 3772 3772 - if (unlikely(!test_bit(FLAG_IS_OUT, &desc->flags))) 3761 3761 + if (unlikely(!test_bit(GPIOD_FLAG_IS_OUT, &desc->flags))) 3773 3762 return -EPERM; 3774 3763 3775 3764 /* ··· 3779 3768 */ 3780 3769 if (!raw && !(array_info && 3781 3770 test_bit(i, array_info->invert_mask)) && 3782 3782 - test_bit(FLAG_ACTIVE_LOW, &desc->flags)) 3771 3771 + test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags)) 3783 3772 value = !value; 3784 3773 trace_gpio_value(desc_to_gpio(desc), 0, value); 3785 3774 /* 3786 3775 * collect all normal outputs belonging to the same chip 3787 3776 * open drain and open source outputs are set individually 3788 3777 */ 3789 3789 - if (test_bit(FLAG_OPEN_DRAIN, &desc->flags) && !raw) { 3778 3778 + if (test_bit(GPIOD_FLAG_OPEN_DRAIN, &desc->flags) && !raw) { 3790 3779 gpio_set_open_drain_value_commit(desc, value); 3791 3791 - } else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags) && !raw) { 3780 3780 + } else if (test_bit(GPIOD_FLAG_OPEN_SOURCE, &desc->flags) && !raw) { 3792 3781 gpio_set_open_source_value_commit(desc, value); 3793 3782 } else { 3794 3783 __set_bit(hwgpio, mask); ··· 3854 3843 */ 3855 3844 static int gpiod_set_value_nocheck(struct gpio_desc *desc, int value) 3856 3845 { 3857 3857 - if (test_bit(FLAG_ACTIVE_LOW, &desc->flags)) 3846 3846 + if (test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags)) 3858 3847 value = !value; 3859 3848 3860 3860 - if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) 3849 3849 + if (test_bit(GPIOD_FLAG_OPEN_DRAIN, &desc->flags)) 3861 3850 return gpio_set_open_drain_value_commit(desc, value); 3862 3862 - else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) 3851 3851 + else if (test_bit(GPIOD_FLAG_OPEN_SOURCE, &desc->flags)) 3863 3852 return gpio_set_open_source_value_commit(desc, value); 3864 3853 3865 3854 return gpiod_set_raw_value_commit(desc, value); ··· 4063 4052 } 4064 4053 4065 4054 /* To be valid for IRQ the line needs to be input or open drain */ 4066 4066 - if (test_bit(FLAG_IS_OUT, &desc->flags) && 4067 4067 - !test_bit(FLAG_OPEN_DRAIN, &desc->flags)) { 4055 4055 + if (test_bit(GPIOD_FLAG_IS_OUT, &desc->flags) && 4056 4056 + !test_bit(GPIOD_FLAG_OPEN_DRAIN, &desc->flags)) { 4068 4057 chip_err(gc, 4069 4058 "%s: tried to flag a GPIO set as output for IRQ\n", 4070 4059 __func__); 4071 4060 return -EIO; 4072 4061 } 4073 4062 4074 4074 - set_bit(FLAG_USED_AS_IRQ, &desc->flags); 4075 4075 - set_bit(FLAG_IRQ_IS_ENABLED, &desc->flags); 4063 4063 + set_bit(GPIOD_FLAG_USED_AS_IRQ, &desc->flags); 4064 4064 + set_bit(GPIOD_FLAG_IRQ_IS_ENABLED, &desc->flags); 4076 4065 4077 4066 return 0; 4078 4067 } ··· 4094 4083 if (IS_ERR(desc)) 4095 4084 return; 4096 4085 4097 4097 - clear_bit(FLAG_USED_AS_IRQ, &desc->flags); 4098 4098 - clear_bit(FLAG_IRQ_IS_ENABLED, &desc->flags); 4086 4086 + clear_bit(GPIOD_FLAG_USED_AS_IRQ, &desc->flags); 4087 4087 + clear_bit(GPIOD_FLAG_IRQ_IS_ENABLED, &desc->flags); 4099 4088 } 4100 4089 EXPORT_SYMBOL_GPL(gpiochip_unlock_as_irq); 4101 4090 ··· 4104 4093 struct gpio_desc *desc = gpiochip_get_desc(gc, offset); 4105 4094 4106 4095 if (!IS_ERR(desc) && 4107 4107 - !WARN_ON(!test_bit(FLAG_USED_AS_IRQ, &desc->flags))) 4108 4108 - clear_bit(FLAG_IRQ_IS_ENABLED, &desc->flags); 4096 4096 + !WARN_ON(!test_bit(GPIOD_FLAG_USED_AS_IRQ, &desc->flags))) 4097 4097 + clear_bit(GPIOD_FLAG_IRQ_IS_ENABLED, &desc->flags); 4109 4098 } 4110 4099 EXPORT_SYMBOL_GPL(gpiochip_disable_irq); 4111 4100 ··· 4114 4103 struct gpio_desc *desc = gpiochip_get_desc(gc, offset); 4115 4104 4116 4105 if (!IS_ERR(desc) && 4117 4117 - !WARN_ON(!test_bit(FLAG_USED_AS_IRQ, &desc->flags))) { 4106 4106 + !WARN_ON(!test_bit(GPIOD_FLAG_USED_AS_IRQ, &desc->flags))) { 4118 4107 /* 4119 4108 * We must not be output when using IRQ UNLESS we are 4120 4109 * open drain. 4121 4110 */ 4122 4122 - WARN_ON(test_bit(FLAG_IS_OUT, &desc->flags) && 4123 4123 - !test_bit(FLAG_OPEN_DRAIN, &desc->flags)); 4124 4124 - set_bit(FLAG_IRQ_IS_ENABLED, &desc->flags); 4111 4111 + WARN_ON(test_bit(GPIOD_FLAG_IS_OUT, &desc->flags) && 4112 4112 + !test_bit(GPIOD_FLAG_OPEN_DRAIN, &desc->flags)); 4113 4113 + set_bit(GPIOD_FLAG_IRQ_IS_ENABLED, &desc->flags); 4125 4114 } 4126 4115 } 4127 4116 EXPORT_SYMBOL_GPL(gpiochip_enable_irq); ··· 4131 4120 if (offset >= gc->ngpio) 4132 4121 return false; 4133 4122 4134 4134 - return test_bit(FLAG_USED_AS_IRQ, &gc->gpiodev->descs[offset].flags); 4123 4123 + return test_bit(GPIOD_FLAG_USED_AS_IRQ, &gc->gpiodev->descs[offset].flags); 4135 4124 } 4136 4125 EXPORT_SYMBOL_GPL(gpiochip_line_is_irq); 4137 4126 ··· 4164 4153 if (offset >= gc->ngpio) 4165 4154 return false; 4166 4155 4167 4167 - return test_bit(FLAG_OPEN_DRAIN, &gc->gpiodev->descs[offset].flags); 4156 4156 + return test_bit(GPIOD_FLAG_OPEN_DRAIN, &gc->gpiodev->descs[offset].flags); 4168 4157 } 4169 4158 EXPORT_SYMBOL_GPL(gpiochip_line_is_open_drain); 4170 4159 ··· 4173 4162 if (offset >= gc->ngpio) 4174 4163 return false; 4175 4164 4176 4176 - return test_bit(FLAG_OPEN_SOURCE, &gc->gpiodev->descs[offset].flags); 4165 4165 + return test_bit(GPIOD_FLAG_OPEN_SOURCE, &gc->gpiodev->descs[offset].flags); 4177 4166 } 4178 4167 EXPORT_SYMBOL_GPL(gpiochip_line_is_open_source); 4179 4168 ··· 4182 4171 if (offset >= gc->ngpio) 4183 4172 return false; 4184 4173 4185 4185 - return !test_bit(FLAG_TRANSITORY, &gc->gpiodev->descs[offset].flags); 4174 4174 + return !test_bit(GPIOD_FLAG_TRANSITORY, &gc->gpiodev->descs[offset].flags); 4186 4175 } 4187 4176 EXPORT_SYMBOL_GPL(gpiochip_line_is_persistent); 4188 4177 ··· 4224 4213 if (value < 0) 4225 4214 return value; 4226 4215 4227 4227 - if (test_bit(FLAG_ACTIVE_LOW, &desc->flags)) 4216 4216 + if (test_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags)) 4228 4217 value = !value; 4229 4218 4230 4219 return value; ··· 4823 4812 int ret; 4824 4813 4825 4814 if (lflags & GPIO_ACTIVE_LOW) 4826 4826 - set_bit(FLAG_ACTIVE_LOW, &desc->flags); 4815 4815 + set_bit(GPIOD_FLAG_ACTIVE_LOW, &desc->flags); 4827 4816 4828 4817 if (lflags & GPIO_OPEN_DRAIN) 4829 4829 - set_bit(FLAG_OPEN_DRAIN, &desc->flags); 4818 4818 + set_bit(GPIOD_FLAG_OPEN_DRAIN, &desc->flags); 4830 4819 else if (dflags & GPIOD_FLAGS_BIT_OPEN_DRAIN) { 4831 4820 /* 4832 4821 * This enforces open drain mode from the consumer side. ··· 4834 4823 * should *REALLY* have specified them as open drain in the 4835 4824 * first place, so print a little warning here. 4836 4825 */ 4837 4837 - set_bit(FLAG_OPEN_DRAIN, &desc->flags); 4826 4826 + set_bit(GPIOD_FLAG_OPEN_DRAIN, &desc->flags); 4838 4827 gpiod_warn(desc, 4839 4828 "enforced open drain please flag it properly in DT/ACPI DSDT/board file\n"); 4840 4829 } 4841 4830 4842 4831 if (lflags & GPIO_OPEN_SOURCE) 4843 4843 - set_bit(FLAG_OPEN_SOURCE, &desc->flags); 4832 4832 + set_bit(GPIOD_FLAG_OPEN_SOURCE, &desc->flags); 4844 4833 4845 4834 if (((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DOWN)) || 4846 4835 ((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DISABLE)) || ··· 4851 4840 } 4852 4841 4853 4842 if (lflags & GPIO_PULL_UP) 4854 4854 - set_bit(FLAG_PULL_UP, &desc->flags); 4843 4843 + set_bit(GPIOD_FLAG_PULL_UP, &desc->flags); 4855 4844 else if (lflags & GPIO_PULL_DOWN) 4856 4856 - set_bit(FLAG_PULL_DOWN, &desc->flags); 4845 4845 + set_bit(GPIOD_FLAG_PULL_DOWN, &desc->flags); 4857 4846 else if (lflags & GPIO_PULL_DISABLE) 4858 4858 - set_bit(FLAG_BIAS_DISABLE, &desc->flags); 4847 4847 + set_bit(GPIOD_FLAG_BIAS_DISABLE, &desc->flags); 4859 4848 4860 4849 ret = gpiod_set_transitory(desc, (lflags & GPIO_TRANSITORY)); 4861 4850 if (ret < 0) ··· 4960 4949 if (!guard.gc) 4961 4950 return -ENODEV; 4962 4951 4963 4963 - if (test_and_set_bit(FLAG_IS_HOGGED, &desc->flags)) 4952 4952 + if (test_and_set_bit(GPIOD_FLAG_IS_HOGGED, &desc->flags)) 4964 4953 return 0; 4965 4954 4966 4955 hwnum = gpio_chip_hwgpio(desc); ··· 4968 4957 local_desc = gpiochip_request_own_desc(guard.gc, hwnum, name, 4969 4958 lflags, dflags); 4970 4959 if (IS_ERR(local_desc)) { 4971 4971 - clear_bit(FLAG_IS_HOGGED, &desc->flags); 4960 4960 + clear_bit(GPIOD_FLAG_IS_HOGGED, &desc->flags); 4972 4961 ret = PTR_ERR(local_desc); 4973 4962 pr_err("requesting hog GPIO %s (chip %s, offset %d) failed, %d\n", 4974 4963 name, gdev->label, hwnum, ret); ··· 4991 4980 { 4992 4981 struct gpio_desc *desc; 4993 4982 4994 4994 - for_each_gpio_desc_with_flag(gc, desc, FLAG_IS_HOGGED) 4983 4983 + for_each_gpio_desc_with_flag(gc, desc, GPIOD_FLAG_IS_HOGGED) 4995 4984 gpiochip_free_own_desc(desc); 4996 4985 } 4997 4986 ··· 5106 5095 } else { 5107 5096 dflags = READ_ONCE(desc->flags); 5108 5097 /* Exclude open drain or open source from fast output */ 5109 5109 - if (test_bit(FLAG_OPEN_DRAIN, &dflags) || 5110 5110 - test_bit(FLAG_OPEN_SOURCE, &dflags)) 5098 5098 + if (test_bit(GPIOD_FLAG_OPEN_DRAIN, &dflags) || 5099 5099 + test_bit(GPIOD_FLAG_OPEN_SOURCE, &dflags)) 5111 5100 __clear_bit(descs->ndescs, 5112 5101 array_info->set_mask); 5113 5102 /* Identify 'fast' pins which require invertion */ ··· 5265 5254 for_each_gpio_desc(gc, desc) { 5266 5255 guard(srcu)(&desc->gdev->desc_srcu); 5267 5256 flags = READ_ONCE(desc->flags); 5268 5268 - is_irq = test_bit(FLAG_USED_AS_IRQ, &flags); 5269 5269 - if (is_irq || test_bit(FLAG_REQUESTED, &flags)) { 5257 5257 + is_irq = test_bit(GPIOD_FLAG_USED_AS_IRQ, &flags); 5258 5258 + if (is_irq || test_bit(GPIOD_FLAG_REQUESTED, &flags)) { 5270 5259 gpiod_get_direction(desc); 5271 5271 - is_out = test_bit(FLAG_IS_OUT, &flags); 5260 5260 + is_out = test_bit(GPIOD_FLAG_IS_OUT, &flags); 5272 5261 value = gpio_chip_get_value(gc, desc); 5273 5273 - active_low = test_bit(FLAG_ACTIVE_LOW, &flags); 5262 5262 + active_low = test_bit(GPIOD_FLAG_ACTIVE_LOW, &flags); 5274 5263 seq_printf(s, " gpio-%-3u (%-20.20s|%-20.20s) %s %s %s%s\n", 5275 5264 gpio, desc->name ?: "", gpiod_get_label(desc), 5276 5265 is_out ? "out" : "in ",

+18 -18

drivers/gpio/gpiolib.h

reviewed

··· 186 186 struct gpio_device *gdev; 187 187 unsigned long flags; 188 188 /* flag symbols are bit numbers */ 189 189 - #define FLAG_REQUESTED 0 190 190 - #define FLAG_IS_OUT 1 191 191 - #define FLAG_EXPORT 2 /* protected by sysfs_lock */ 192 192 - #define FLAG_SYSFS 3 /* exported via /sys/class/gpio/control */ 193 193 - #define FLAG_ACTIVE_LOW 6 /* value has active low */ 194 194 - #define FLAG_OPEN_DRAIN 7 /* Gpio is open drain type */ 195 195 - #define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */ 196 196 - #define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */ 197 197 - #define FLAG_IRQ_IS_ENABLED 10 /* GPIO is connected to an enabled IRQ */ 198 198 - #define FLAG_IS_HOGGED 11 /* GPIO is hogged */ 199 199 - #define FLAG_TRANSITORY 12 /* GPIO may lose value in sleep or reset */ 200 200 - #define FLAG_PULL_UP 13 /* GPIO has pull up enabled */ 201 201 - #define FLAG_PULL_DOWN 14 /* GPIO has pull down enabled */ 202 202 - #define FLAG_BIAS_DISABLE 15 /* GPIO has pull disabled */ 203 203 - #define FLAG_EDGE_RISING 16 /* GPIO CDEV detects rising edge events */ 204 204 - #define FLAG_EDGE_FALLING 17 /* GPIO CDEV detects falling edge events */ 205 205 - #define FLAG_EVENT_CLOCK_REALTIME 18 /* GPIO CDEV reports REALTIME timestamps in events */ 206 206 - #define FLAG_EVENT_CLOCK_HTE 19 /* GPIO CDEV reports hardware timestamps in events */ 189 189 + #define GPIOD_FLAG_REQUESTED 0 /* GPIO is in use */ 190 190 + #define GPIOD_FLAG_IS_OUT 1 /* GPIO is in output mode */ 191 191 + #define GPIOD_FLAG_EXPORT 2 /* GPIO is exported to user-space */ 192 192 + #define GPIOD_FLAG_SYSFS 3 /* GPIO is exported via /sys/class/gpio */ 193 193 + #define GPIOD_FLAG_ACTIVE_LOW 6 /* GPIO is active-low */ 194 194 + #define GPIOD_FLAG_OPEN_DRAIN 7 /* GPIO is open drain type */ 195 195 + #define GPIOD_FLAG_OPEN_SOURCE 8 /* GPIO is open source type */ 196 196 + #define GPIOD_FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */ 197 197 + #define GPIOD_FLAG_IRQ_IS_ENABLED 10 /* GPIO is connected to an enabled IRQ */ 198 198 + #define GPIOD_FLAG_IS_HOGGED 11 /* GPIO is hogged */ 199 199 + #define GPIOD_FLAG_TRANSITORY 12 /* GPIO may lose value in sleep or reset */ 200 200 + #define GPIOD_FLAG_PULL_UP 13 /* GPIO has pull up enabled */ 201 201 + #define GPIOD_FLAG_PULL_DOWN 14 /* GPIO has pull down enabled */ 202 202 + #define GPIOD_FLAG_BIAS_DISABLE 15 /* GPIO has pull disabled */ 203 203 + #define GPIOD_FLAG_EDGE_RISING 16 /* GPIO CDEV detects rising edge events */ 204 204 + #define GPIOD_FLAG_EDGE_FALLING 17 /* GPIO CDEV detects falling edge events */ 205 205 + #define GPIOD_FLAG_EVENT_CLOCK_REALTIME 18 /* GPIO CDEV reports REALTIME timestamps in events */ 206 206 + #define GPIOD_FLAG_EVENT_CLOCK_HTE 19 /* GPIO CDEV reports hardware timestamps in events */ 207 207 208 208 /* Connection label */ 209 209 struct gpio_desc_label __rcu *label;

+10

drivers/hwmon/Kconfig

reviewed

··· 1708 1708 This driver can also be built as a module. If so, the module 1709 1709 will be called nct6683. 1710 1710 1711 1711 + config SENSORS_NCT6694 1712 1712 + tristate "Nuvoton NCT6694 Hardware Monitor support" 1713 1713 + depends on MFD_NCT6694 1714 1714 + help 1715 1715 + Say Y here to support Nuvoton NCT6694 hardware monitoring 1716 1716 + functionality. 1717 1717 + 1718 1718 + This driver can also be built as a module. If so, the module 1719 1719 + will be called nct6694-hwmon. 1720 1720 + 1711 1721 config SENSORS_NCT6775_CORE 1712 1722 tristate 1713 1723 select REGMAP

+1

drivers/hwmon/Makefile

reviewed

··· 175 175 obj-$(CONFIG_SENSORS_MENF21BMC_HWMON) += menf21bmc_hwmon.o 176 176 obj-$(CONFIG_SENSORS_MR75203) += mr75203.o 177 177 obj-$(CONFIG_SENSORS_NCT6683) += nct6683.o 178 178 + obj-$(CONFIG_SENSORS_NCT6694) += nct6694-hwmon.o 178 179 obj-$(CONFIG_SENSORS_NCT6775_CORE) += nct6775-core.o 179 180 nct6775-objs := nct6775-platform.o 180 181 obj-$(CONFIG_SENSORS_NCT6775) += nct6775.o

+949

drivers/hwmon/nct6694-hwmon.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Nuvoton NCT6694 HWMON driver based on USB interface. 4 4 + * 5 5 + * Copyright (C) 2025 Nuvoton Technology Corp. 6 6 + */ 7 7 + 8 8 + #include <linux/bits.h> 9 9 + #include <linux/bitfield.h> 10 10 + #include <linux/hwmon.h> 11 11 + #include <linux/kernel.h> 12 12 + #include <linux/mfd/core.h> 13 13 + #include <linux/mfd/nct6694.h> 14 14 + #include <linux/module.h> 15 15 + #include <linux/platform_device.h> 16 16 + #include <linux/slab.h> 17 17 + 18 18 + /* 19 19 + * USB command module type for NCT6694 report channel 20 20 + * This defines the module type used for communication with the NCT6694 21 21 + * report channel over the USB interface. 22 22 + */ 23 23 + #define NCT6694_RPT_MOD 0xFF 24 24 + 25 25 + /* Report channel */ 26 26 + /* 27 27 + * The report channel is used to report the status of the hardware monitor 28 28 + * devices, such as voltage, temperature, fan speed, and PWM. 29 29 + */ 30 30 + #define NCT6694_VIN_IDX(x) (0x00 + (x)) 31 31 + #define NCT6694_TIN_IDX(x) \ 32 32 + ({ typeof(x) (_x) = (x); \ 33 33 + ((_x) < 10) ? (0x10 + ((_x) * 2)) : \ 34 34 + (0x30 + (((_x) - 10) * 2)); }) 35 35 + #define NCT6694_FIN_IDX(x) (0x50 + ((x) * 2)) 36 36 + #define NCT6694_PWM_IDX(x) (0x70 + (x)) 37 37 + #define NCT6694_VIN_STS(x) (0x68 + (x)) 38 38 + #define NCT6694_TIN_STS(x) (0x6A + (x)) 39 39 + #define NCT6694_FIN_STS(x) (0x6E + (x)) 40 40 + 41 41 + /* 42 42 + * USB command module type for NCT6694 HWMON controller. 43 43 + * This defines the module type used for communication with the NCT6694 44 44 + * HWMON controller over the USB interface. 45 45 + */ 46 46 + #define NCT6694_HWMON_MOD 0x00 47 47 + 48 48 + /* Command 00h - Hardware Monitor Control */ 49 49 + #define NCT6694_HWMON_CONTROL 0x00 50 50 + #define NCT6694_HWMON_CONTROL_SEL 0x00 51 51 + 52 52 + /* Command 02h - Alarm Control */ 53 53 + #define NCT6694_HWMON_ALARM 0x02 54 54 + #define NCT6694_HWMON_ALARM_SEL 0x00 55 55 + 56 56 + /* 57 57 + * USB command module type for NCT6694 PWM controller. 58 58 + * This defines the module type used for communication with the NCT6694 59 59 + * PWM controller over the USB interface. 60 60 + */ 61 61 + #define NCT6694_PWM_MOD 0x01 62 62 + 63 63 + /* PWM Command - Manual Control */ 64 64 + #define NCT6694_PWM_CONTROL 0x01 65 65 + #define NCT6694_PWM_CONTROL_SEL 0x00 66 66 + 67 67 + #define NCT6694_FREQ_FROM_REG(reg) ((reg) * 25000 / 255) 68 68 + #define NCT6694_FREQ_TO_REG(val) \ 69 69 + (DIV_ROUND_CLOSEST(clamp_val((val), 100, 25000) * 255, 25000)) 70 70 + 71 71 + #define NCT6694_LSB_REG_MASK GENMASK(7, 5) 72 72 + #define NCT6694_TIN_HYST_MASK GENMASK(7, 5) 73 73 + 74 74 + enum nct6694_hwmon_temp_mode { 75 75 + NCT6694_HWMON_TWOTIME_IRQ = 0, 76 76 + NCT6694_HWMON_ONETIME_IRQ, 77 77 + NCT6694_HWMON_REALTIME_IRQ, 78 78 + NCT6694_HWMON_COMPARE_IRQ, 79 79 + }; 80 80 + 81 81 + struct __packed nct6694_hwmon_control { 82 82 + u8 vin_en[2]; 83 83 + u8 tin_en[2]; 84 84 + u8 fin_en[2]; 85 85 + u8 pwm_en[2]; 86 86 + u8 reserved1[40]; 87 87 + u8 pwm_freq[10]; 88 88 + u8 reserved2[6]; 89 89 + }; 90 90 + 91 91 + struct __packed nct6694_hwmon_alarm { 92 92 + u8 smi_ctrl; 93 93 + u8 reserved1[15]; 94 94 + struct { 95 95 + u8 hl; 96 96 + u8 ll; 97 97 + } vin_limit[16]; 98 98 + struct { 99 99 + u8 hyst; 100 100 + s8 hl; 101 101 + } tin_cfg[32]; 102 102 + __be16 fin_ll[10]; 103 103 + u8 reserved2[4]; 104 104 + }; 105 105 + 106 106 + struct __packed nct6694_pwm_control { 107 107 + u8 mal_en[2]; 108 108 + u8 mal_val[10]; 109 109 + u8 reserved[12]; 110 110 + }; 111 111 + 112 112 + union __packed nct6694_hwmon_rpt { 113 113 + u8 vin; 114 114 + struct { 115 115 + u8 msb; 116 116 + u8 lsb; 117 117 + } tin; 118 118 + __be16 fin; 119 119 + u8 pwm; 120 120 + u8 status; 121 121 + }; 122 122 + 123 123 + union __packed nct6694_hwmon_msg { 124 124 + struct nct6694_hwmon_alarm hwmon_alarm; 125 125 + struct nct6694_pwm_control pwm_ctrl; 126 126 + }; 127 127 + 128 128 + struct nct6694_hwmon_data { 129 129 + struct nct6694 *nct6694; 130 130 + struct mutex lock; 131 131 + struct nct6694_hwmon_control hwmon_en; 132 132 + union nct6694_hwmon_rpt *rpt; 133 133 + union nct6694_hwmon_msg *msg; 134 134 + }; 135 135 + 136 136 + static inline long in_from_reg(u8 reg) 137 137 + { 138 138 + return reg * 16; 139 139 + } 140 140 + 141 141 + static inline u8 in_to_reg(long val) 142 142 + { 143 143 + return DIV_ROUND_CLOSEST(val, 16); 144 144 + } 145 145 + 146 146 + static inline long temp_from_reg(s8 reg) 147 147 + { 148 148 + return reg * 1000; 149 149 + } 150 150 + 151 151 + static inline s8 temp_to_reg(long val) 152 152 + { 153 153 + return DIV_ROUND_CLOSEST(val, 1000); 154 154 + } 155 155 + 156 156 + #define NCT6694_HWMON_IN_CONFIG (HWMON_I_INPUT | HWMON_I_ENABLE | \ 157 157 + HWMON_I_MAX | HWMON_I_MIN | \ 158 158 + HWMON_I_ALARM) 159 159 + #define NCT6694_HWMON_TEMP_CONFIG (HWMON_T_INPUT | HWMON_T_ENABLE | \ 160 160 + HWMON_T_MAX | HWMON_T_MAX_HYST | \ 161 161 + HWMON_T_MAX_ALARM) 162 162 + #define NCT6694_HWMON_FAN_CONFIG (HWMON_F_INPUT | HWMON_F_ENABLE | \ 163 163 + HWMON_F_MIN | HWMON_F_MIN_ALARM) 164 164 + #define NCT6694_HWMON_PWM_CONFIG (HWMON_PWM_INPUT | HWMON_PWM_ENABLE | \ 165 165 + HWMON_PWM_FREQ) 166 166 + static const struct hwmon_channel_info *nct6694_info[] = { 167 167 + HWMON_CHANNEL_INFO(in, 168 168 + NCT6694_HWMON_IN_CONFIG, /* VIN0 */ 169 169 + NCT6694_HWMON_IN_CONFIG, /* VIN1 */ 170 170 + NCT6694_HWMON_IN_CONFIG, /* VIN2 */ 171 171 + NCT6694_HWMON_IN_CONFIG, /* VIN3 */ 172 172 + NCT6694_HWMON_IN_CONFIG, /* VIN5 */ 173 173 + NCT6694_HWMON_IN_CONFIG, /* VIN6 */ 174 174 + NCT6694_HWMON_IN_CONFIG, /* VIN7 */ 175 175 + NCT6694_HWMON_IN_CONFIG, /* VIN14 */ 176 176 + NCT6694_HWMON_IN_CONFIG, /* VIN15 */ 177 177 + NCT6694_HWMON_IN_CONFIG, /* VIN16 */ 178 178 + NCT6694_HWMON_IN_CONFIG, /* VBAT */ 179 179 + NCT6694_HWMON_IN_CONFIG, /* VSB */ 180 180 + NCT6694_HWMON_IN_CONFIG, /* AVSB */ 181 181 + NCT6694_HWMON_IN_CONFIG, /* VCC */ 182 182 + NCT6694_HWMON_IN_CONFIG, /* VHIF */ 183 183 + NCT6694_HWMON_IN_CONFIG), /* VTT */ 184 184 + 185 185 + HWMON_CHANNEL_INFO(temp, 186 186 + NCT6694_HWMON_TEMP_CONFIG, /* THR1 */ 187 187 + NCT6694_HWMON_TEMP_CONFIG, /* THR2 */ 188 188 + NCT6694_HWMON_TEMP_CONFIG, /* THR14 */ 189 189 + NCT6694_HWMON_TEMP_CONFIG, /* THR15 */ 190 190 + NCT6694_HWMON_TEMP_CONFIG, /* THR16 */ 191 191 + NCT6694_HWMON_TEMP_CONFIG, /* TDP0 */ 192 192 + NCT6694_HWMON_TEMP_CONFIG, /* TDP1 */ 193 193 + NCT6694_HWMON_TEMP_CONFIG, /* TDP2 */ 194 194 + NCT6694_HWMON_TEMP_CONFIG, /* TDP3 */ 195 195 + NCT6694_HWMON_TEMP_CONFIG, /* TDP4 */ 196 196 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN0 */ 197 197 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN1 */ 198 198 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN2 */ 199 199 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN3 */ 200 200 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN4 */ 201 201 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN5 */ 202 202 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN6 */ 203 203 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN7 */ 204 204 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN8 */ 205 205 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN9 */ 206 206 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN10 */ 207 207 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN11 */ 208 208 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN12 */ 209 209 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN13 */ 210 210 + NCT6694_HWMON_TEMP_CONFIG, /* DTIN14 */ 211 211 + NCT6694_HWMON_TEMP_CONFIG), /* DTIN15 */ 212 212 + 213 213 + HWMON_CHANNEL_INFO(fan, 214 214 + NCT6694_HWMON_FAN_CONFIG, /* FIN0 */ 215 215 + NCT6694_HWMON_FAN_CONFIG, /* FIN1 */ 216 216 + NCT6694_HWMON_FAN_CONFIG, /* FIN2 */ 217 217 + NCT6694_HWMON_FAN_CONFIG, /* FIN3 */ 218 218 + NCT6694_HWMON_FAN_CONFIG, /* FIN4 */ 219 219 + NCT6694_HWMON_FAN_CONFIG, /* FIN5 */ 220 220 + NCT6694_HWMON_FAN_CONFIG, /* FIN6 */ 221 221 + NCT6694_HWMON_FAN_CONFIG, /* FIN7 */ 222 222 + NCT6694_HWMON_FAN_CONFIG, /* FIN8 */ 223 223 + NCT6694_HWMON_FAN_CONFIG), /* FIN9 */ 224 224 + 225 225 + HWMON_CHANNEL_INFO(pwm, 226 226 + NCT6694_HWMON_PWM_CONFIG, /* PWM0 */ 227 227 + NCT6694_HWMON_PWM_CONFIG, /* PWM1 */ 228 228 + NCT6694_HWMON_PWM_CONFIG, /* PWM2 */ 229 229 + NCT6694_HWMON_PWM_CONFIG, /* PWM3 */ 230 230 + NCT6694_HWMON_PWM_CONFIG, /* PWM4 */ 231 231 + NCT6694_HWMON_PWM_CONFIG, /* PWM5 */ 232 232 + NCT6694_HWMON_PWM_CONFIG, /* PWM6 */ 233 233 + NCT6694_HWMON_PWM_CONFIG, /* PWM7 */ 234 234 + NCT6694_HWMON_PWM_CONFIG, /* PWM8 */ 235 235 + NCT6694_HWMON_PWM_CONFIG), /* PWM9 */ 236 236 + NULL 237 237 + }; 238 238 + 239 239 + static int nct6694_in_read(struct device *dev, u32 attr, int channel, 240 240 + long *val) 241 241 + { 242 242 + struct nct6694_hwmon_data *data = dev_get_drvdata(dev); 243 243 + struct nct6694_cmd_header cmd_hd; 244 244 + unsigned char vin_en; 245 245 + int ret; 246 246 + 247 247 + guard(mutex)(&data->lock); 248 248 + 249 249 + switch (attr) { 250 250 + case hwmon_in_enable: 251 251 + vin_en = data->hwmon_en.vin_en[(channel / 8)]; 252 252 + *val = !!(vin_en & BIT(channel % 8)); 253 253 + 254 254 + return 0; 255 255 + case hwmon_in_input: 256 256 + cmd_hd = (struct nct6694_cmd_header) { 257 257 + .mod = NCT6694_RPT_MOD, 258 258 + .offset = cpu_to_le16(NCT6694_VIN_IDX(channel)), 259 259 + .len = cpu_to_le16(sizeof(data->rpt->vin)) 260 260 + }; 261 261 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 262 262 + &data->rpt->vin); 263 263 + if (ret) 264 264 + return ret; 265 265 + 266 266 + *val = in_from_reg(data->rpt->vin); 267 267 + 268 268 + return 0; 269 269 + case hwmon_in_max: 270 270 + cmd_hd = (struct nct6694_cmd_header) { 271 271 + .mod = NCT6694_HWMON_MOD, 272 272 + .cmd = NCT6694_HWMON_ALARM, 273 273 + .sel = NCT6694_HWMON_ALARM_SEL, 274 274 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 275 275 + }; 276 276 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 277 277 + &data->msg->hwmon_alarm); 278 278 + if (ret) 279 279 + return ret; 280 280 + 281 281 + *val = in_from_reg(data->msg->hwmon_alarm.vin_limit[channel].hl); 282 282 + 283 283 + return 0; 284 284 + case hwmon_in_min: 285 285 + cmd_hd = (struct nct6694_cmd_header) { 286 286 + .mod = NCT6694_HWMON_MOD, 287 287 + .cmd = NCT6694_HWMON_ALARM, 288 288 + .sel = NCT6694_HWMON_ALARM_SEL, 289 289 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 290 290 + }; 291 291 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 292 292 + &data->msg->hwmon_alarm); 293 293 + if (ret) 294 294 + return ret; 295 295 + 296 296 + *val = in_from_reg(data->msg->hwmon_alarm.vin_limit[channel].ll); 297 297 + 298 298 + return 0; 299 299 + case hwmon_in_alarm: 300 300 + cmd_hd = (struct nct6694_cmd_header) { 301 301 + .mod = NCT6694_RPT_MOD, 302 302 + .offset = cpu_to_le16(NCT6694_VIN_STS(channel / 8)), 303 303 + .len = cpu_to_le16(sizeof(data->rpt->status)) 304 304 + }; 305 305 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 306 306 + &data->rpt->status); 307 307 + if (ret) 308 308 + return ret; 309 309 + 310 310 + *val = !!(data->rpt->status & BIT(channel % 8)); 311 311 + 312 312 + return 0; 313 313 + default: 314 314 + return -EOPNOTSUPP; 315 315 + } 316 316 + } 317 317 + 318 318 + static int nct6694_temp_read(struct device *dev, u32 attr, int channel, 319 319 + long *val) 320 320 + { 321 321 + struct nct6694_hwmon_data *data = dev_get_drvdata(dev); 322 322 + struct nct6694_cmd_header cmd_hd; 323 323 + unsigned char temp_en, temp_hyst; 324 324 + signed char temp_max; 325 325 + int ret, temp_raw; 326 326 + 327 327 + guard(mutex)(&data->lock); 328 328 + 329 329 + switch (attr) { 330 330 + case hwmon_temp_enable: 331 331 + temp_en = data->hwmon_en.tin_en[channel / 8]; 332 332 + *val = !!(temp_en & BIT(channel % 8)); 333 333 + 334 334 + return 0; 335 335 + case hwmon_temp_input: 336 336 + cmd_hd = (struct nct6694_cmd_header) { 337 337 + .mod = NCT6694_RPT_MOD, 338 338 + .offset = cpu_to_le16(NCT6694_TIN_IDX(channel)), 339 339 + .len = cpu_to_le16(sizeof(data->rpt->tin)) 340 340 + }; 341 341 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 342 342 + &data->rpt->tin); 343 343 + if (ret) 344 344 + return ret; 345 345 + 346 346 + temp_raw = data->rpt->tin.msb << 3; 347 347 + temp_raw |= FIELD_GET(NCT6694_LSB_REG_MASK, data->rpt->tin.lsb); 348 348 + 349 349 + /* Real temperature(milli degrees Celsius) = temp_raw * 1000 * 0.125 */ 350 350 + *val = sign_extend32(temp_raw, 10) * 125; 351 351 + 352 352 + return 0; 353 353 + case hwmon_temp_max: 354 354 + cmd_hd = (struct nct6694_cmd_header) { 355 355 + .mod = NCT6694_HWMON_MOD, 356 356 + .cmd = NCT6694_HWMON_ALARM, 357 357 + .sel = NCT6694_HWMON_ALARM_SEL, 358 358 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 359 359 + }; 360 360 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 361 361 + &data->msg->hwmon_alarm); 362 362 + if (ret) 363 363 + return ret; 364 364 + 365 365 + *val = temp_from_reg(data->msg->hwmon_alarm.tin_cfg[channel].hl); 366 366 + 367 367 + return 0; 368 368 + case hwmon_temp_max_hyst: 369 369 + cmd_hd = (struct nct6694_cmd_header) { 370 370 + .mod = NCT6694_HWMON_MOD, 371 371 + .cmd = NCT6694_HWMON_ALARM, 372 372 + .sel = NCT6694_HWMON_ALARM_SEL, 373 373 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 374 374 + }; 375 375 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 376 376 + &data->msg->hwmon_alarm); 377 377 + if (ret) 378 378 + return ret; 379 379 + 380 380 + temp_max = data->msg->hwmon_alarm.tin_cfg[channel].hl; 381 381 + temp_hyst = FIELD_GET(NCT6694_TIN_HYST_MASK, 382 382 + data->msg->hwmon_alarm.tin_cfg[channel].hyst); 383 383 + *val = temp_from_reg(temp_max - temp_hyst); 384 384 + 385 385 + return 0; 386 386 + case hwmon_temp_max_alarm: 387 387 + cmd_hd = (struct nct6694_cmd_header) { 388 388 + .mod = NCT6694_RPT_MOD, 389 389 + .offset = cpu_to_le16(NCT6694_TIN_STS(channel / 8)), 390 390 + .len = cpu_to_le16(sizeof(data->rpt->status)) 391 391 + }; 392 392 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 393 393 + &data->rpt->status); 394 394 + if (ret) 395 395 + return ret; 396 396 + 397 397 + *val = !!(data->rpt->status & BIT(channel % 8)); 398 398 + 399 399 + return 0; 400 400 + default: 401 401 + return -EOPNOTSUPP; 402 402 + } 403 403 + } 404 404 + 405 405 + static int nct6694_fan_read(struct device *dev, u32 attr, int channel, 406 406 + long *val) 407 407 + { 408 408 + struct nct6694_hwmon_data *data = dev_get_drvdata(dev); 409 409 + struct nct6694_cmd_header cmd_hd; 410 410 + unsigned char fanin_en; 411 411 + int ret; 412 412 + 413 413 + guard(mutex)(&data->lock); 414 414 + 415 415 + switch (attr) { 416 416 + case hwmon_fan_enable: 417 417 + fanin_en = data->hwmon_en.fin_en[channel / 8]; 418 418 + *val = !!(fanin_en & BIT(channel % 8)); 419 419 + 420 420 + return 0; 421 421 + case hwmon_fan_input: 422 422 + cmd_hd = (struct nct6694_cmd_header) { 423 423 + .mod = NCT6694_RPT_MOD, 424 424 + .offset = cpu_to_le16(NCT6694_FIN_IDX(channel)), 425 425 + .len = cpu_to_le16(sizeof(data->rpt->fin)) 426 426 + }; 427 427 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 428 428 + &data->rpt->fin); 429 429 + if (ret) 430 430 + return ret; 431 431 + 432 432 + *val = be16_to_cpu(data->rpt->fin); 433 433 + 434 434 + return 0; 435 435 + case hwmon_fan_min: 436 436 + cmd_hd = (struct nct6694_cmd_header) { 437 437 + .mod = NCT6694_HWMON_MOD, 438 438 + .cmd = NCT6694_HWMON_ALARM, 439 439 + .sel = NCT6694_HWMON_ALARM_SEL, 440 440 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 441 441 + }; 442 442 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 443 443 + &data->msg->hwmon_alarm); 444 444 + if (ret) 445 445 + return ret; 446 446 + 447 447 + *val = be16_to_cpu(data->msg->hwmon_alarm.fin_ll[channel]); 448 448 + 449 449 + return 0; 450 450 + case hwmon_fan_min_alarm: 451 451 + cmd_hd = (struct nct6694_cmd_header) { 452 452 + .mod = NCT6694_RPT_MOD, 453 453 + .offset = cpu_to_le16(NCT6694_FIN_STS(channel / 8)), 454 454 + .len = cpu_to_le16(sizeof(data->rpt->status)) 455 455 + }; 456 456 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 457 457 + &data->rpt->status); 458 458 + if (ret) 459 459 + return ret; 460 460 + 461 461 + *val = !!(data->rpt->status & BIT(channel % 8)); 462 462 + 463 463 + return 0; 464 464 + default: 465 465 + return -EOPNOTSUPP; 466 466 + } 467 467 + } 468 468 + 469 469 + static int nct6694_pwm_read(struct device *dev, u32 attr, int channel, 470 470 + long *val) 471 471 + { 472 472 + struct nct6694_hwmon_data *data = dev_get_drvdata(dev); 473 473 + struct nct6694_cmd_header cmd_hd; 474 474 + unsigned char pwm_en; 475 475 + int ret; 476 476 + 477 477 + guard(mutex)(&data->lock); 478 478 + 479 479 + switch (attr) { 480 480 + case hwmon_pwm_enable: 481 481 + pwm_en = data->hwmon_en.pwm_en[channel / 8]; 482 482 + *val = !!(pwm_en & BIT(channel % 8)); 483 483 + 484 484 + return 0; 485 485 + case hwmon_pwm_input: 486 486 + cmd_hd = (struct nct6694_cmd_header) { 487 487 + .mod = NCT6694_RPT_MOD, 488 488 + .offset = cpu_to_le16(NCT6694_PWM_IDX(channel)), 489 489 + .len = cpu_to_le16(sizeof(data->rpt->pwm)) 490 490 + }; 491 491 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 492 492 + &data->rpt->pwm); 493 493 + if (ret) 494 494 + return ret; 495 495 + 496 496 + *val = data->rpt->pwm; 497 497 + 498 498 + return 0; 499 499 + case hwmon_pwm_freq: 500 500 + *val = NCT6694_FREQ_FROM_REG(data->hwmon_en.pwm_freq[channel]); 501 501 + 502 502 + return 0; 503 503 + default: 504 504 + return -EOPNOTSUPP; 505 505 + } 506 506 + } 507 507 + 508 508 + static int nct6694_in_write(struct device *dev, u32 attr, int channel, 509 509 + long val) 510 510 + { 511 511 + struct nct6694_hwmon_data *data = dev_get_drvdata(dev); 512 512 + struct nct6694_cmd_header cmd_hd; 513 513 + int ret; 514 514 + 515 515 + guard(mutex)(&data->lock); 516 516 + 517 517 + switch (attr) { 518 518 + case hwmon_in_enable: 519 519 + if (val == 0) 520 520 + data->hwmon_en.vin_en[channel / 8] &= ~BIT(channel % 8); 521 521 + else if (val == 1) 522 522 + data->hwmon_en.vin_en[channel / 8] |= BIT(channel % 8); 523 523 + else 524 524 + return -EINVAL; 525 525 + 526 526 + cmd_hd = (struct nct6694_cmd_header) { 527 527 + .mod = NCT6694_HWMON_MOD, 528 528 + .cmd = NCT6694_HWMON_CONTROL, 529 529 + .sel = NCT6694_HWMON_CONTROL_SEL, 530 530 + .len = cpu_to_le16(sizeof(data->hwmon_en)) 531 531 + }; 532 532 + 533 533 + return nct6694_write_msg(data->nct6694, &cmd_hd, 534 534 + &data->hwmon_en); 535 535 + case hwmon_in_max: 536 536 + cmd_hd = (struct nct6694_cmd_header) { 537 537 + .mod = NCT6694_HWMON_MOD, 538 538 + .cmd = NCT6694_HWMON_ALARM, 539 539 + .sel = NCT6694_HWMON_ALARM_SEL, 540 540 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 541 541 + }; 542 542 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 543 543 + &data->msg->hwmon_alarm); 544 544 + if (ret) 545 545 + return ret; 546 546 + 547 547 + val = clamp_val(val, 0, 2032); 548 548 + data->msg->hwmon_alarm.vin_limit[channel].hl = in_to_reg(val); 549 549 + 550 550 + return nct6694_write_msg(data->nct6694, &cmd_hd, 551 551 + &data->msg->hwmon_alarm); 552 552 + case hwmon_in_min: 553 553 + cmd_hd = (struct nct6694_cmd_header) { 554 554 + .mod = NCT6694_HWMON_MOD, 555 555 + .cmd = NCT6694_HWMON_ALARM, 556 556 + .sel = NCT6694_HWMON_ALARM_SEL, 557 557 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 558 558 + }; 559 559 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 560 560 + &data->msg->hwmon_alarm); 561 561 + if (ret) 562 562 + return ret; 563 563 + 564 564 + val = clamp_val(val, 0, 2032); 565 565 + data->msg->hwmon_alarm.vin_limit[channel].ll = in_to_reg(val); 566 566 + 567 567 + return nct6694_write_msg(data->nct6694, &cmd_hd, 568 568 + &data->msg->hwmon_alarm); 569 569 + default: 570 570 + return -EOPNOTSUPP; 571 571 + } 572 572 + } 573 573 + 574 574 + static int nct6694_temp_write(struct device *dev, u32 attr, int channel, 575 575 + long val) 576 576 + { 577 577 + struct nct6694_hwmon_data *data = dev_get_drvdata(dev); 578 578 + struct nct6694_cmd_header cmd_hd; 579 579 + unsigned char temp_hyst; 580 580 + signed char temp_max; 581 581 + int ret; 582 582 + 583 583 + guard(mutex)(&data->lock); 584 584 + 585 585 + switch (attr) { 586 586 + case hwmon_temp_enable: 587 587 + if (val == 0) 588 588 + data->hwmon_en.tin_en[channel / 8] &= ~BIT(channel % 8); 589 589 + else if (val == 1) 590 590 + data->hwmon_en.tin_en[channel / 8] |= BIT(channel % 8); 591 591 + else 592 592 + return -EINVAL; 593 593 + 594 594 + cmd_hd = (struct nct6694_cmd_header) { 595 595 + .mod = NCT6694_HWMON_MOD, 596 596 + .cmd = NCT6694_HWMON_CONTROL, 597 597 + .sel = NCT6694_HWMON_CONTROL_SEL, 598 598 + .len = cpu_to_le16(sizeof(data->hwmon_en)) 599 599 + }; 600 600 + 601 601 + return nct6694_write_msg(data->nct6694, &cmd_hd, 602 602 + &data->hwmon_en); 603 603 + case hwmon_temp_max: 604 604 + cmd_hd = (struct nct6694_cmd_header) { 605 605 + .mod = NCT6694_HWMON_MOD, 606 606 + .cmd = NCT6694_HWMON_ALARM, 607 607 + .sel = NCT6694_HWMON_ALARM_SEL, 608 608 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 609 609 + }; 610 610 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 611 611 + &data->msg->hwmon_alarm); 612 612 + if (ret) 613 613 + return ret; 614 614 + 615 615 + val = clamp_val(val, -127000, 127000); 616 616 + data->msg->hwmon_alarm.tin_cfg[channel].hl = temp_to_reg(val); 617 617 + 618 618 + return nct6694_write_msg(data->nct6694, &cmd_hd, 619 619 + &data->msg->hwmon_alarm); 620 620 + case hwmon_temp_max_hyst: 621 621 + cmd_hd = (struct nct6694_cmd_header) { 622 622 + .mod = NCT6694_HWMON_MOD, 623 623 + .cmd = NCT6694_HWMON_ALARM, 624 624 + .sel = NCT6694_HWMON_ALARM_SEL, 625 625 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 626 626 + }; 627 627 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 628 628 + &data->msg->hwmon_alarm); 629 629 + 630 630 + val = clamp_val(val, -127000, 127000); 631 631 + temp_max = data->msg->hwmon_alarm.tin_cfg[channel].hl; 632 632 + temp_hyst = temp_max - temp_to_reg(val); 633 633 + temp_hyst = clamp_val(temp_hyst, 0, 7); 634 634 + data->msg->hwmon_alarm.tin_cfg[channel].hyst = 635 635 + (data->msg->hwmon_alarm.tin_cfg[channel].hyst & ~NCT6694_TIN_HYST_MASK) | 636 636 + FIELD_PREP(NCT6694_TIN_HYST_MASK, temp_hyst); 637 637 + 638 638 + return nct6694_write_msg(data->nct6694, &cmd_hd, 639 639 + &data->msg->hwmon_alarm); 640 640 + default: 641 641 + return -EOPNOTSUPP; 642 642 + } 643 643 + } 644 644 + 645 645 + static int nct6694_fan_write(struct device *dev, u32 attr, int channel, 646 646 + long val) 647 647 + { 648 648 + struct nct6694_hwmon_data *data = dev_get_drvdata(dev); 649 649 + struct nct6694_cmd_header cmd_hd; 650 650 + int ret; 651 651 + 652 652 + guard(mutex)(&data->lock); 653 653 + 654 654 + switch (attr) { 655 655 + case hwmon_fan_enable: 656 656 + if (val == 0) 657 657 + data->hwmon_en.fin_en[channel / 8] &= ~BIT(channel % 8); 658 658 + else if (val == 1) 659 659 + data->hwmon_en.fin_en[channel / 8] |= BIT(channel % 8); 660 660 + else 661 661 + return -EINVAL; 662 662 + 663 663 + cmd_hd = (struct nct6694_cmd_header) { 664 664 + .mod = NCT6694_HWMON_MOD, 665 665 + .cmd = NCT6694_HWMON_CONTROL, 666 666 + .sel = NCT6694_HWMON_CONTROL_SEL, 667 667 + .len = cpu_to_le16(sizeof(data->hwmon_en)) 668 668 + }; 669 669 + 670 670 + return nct6694_write_msg(data->nct6694, &cmd_hd, 671 671 + &data->hwmon_en); 672 672 + case hwmon_fan_min: 673 673 + cmd_hd = (struct nct6694_cmd_header) { 674 674 + .mod = NCT6694_HWMON_MOD, 675 675 + .cmd = NCT6694_HWMON_ALARM, 676 676 + .sel = NCT6694_HWMON_ALARM_SEL, 677 677 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 678 678 + }; 679 679 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 680 680 + &data->msg->hwmon_alarm); 681 681 + if (ret) 682 682 + return ret; 683 683 + 684 684 + val = clamp_val(val, 1, 65535); 685 685 + data->msg->hwmon_alarm.fin_ll[channel] = cpu_to_be16(val); 686 686 + 687 687 + return nct6694_write_msg(data->nct6694, &cmd_hd, 688 688 + &data->msg->hwmon_alarm); 689 689 + default: 690 690 + return -EOPNOTSUPP; 691 691 + } 692 692 + } 693 693 + 694 694 + static int nct6694_pwm_write(struct device *dev, u32 attr, int channel, 695 695 + long val) 696 696 + { 697 697 + struct nct6694_hwmon_data *data = dev_get_drvdata(dev); 698 698 + struct nct6694_cmd_header cmd_hd; 699 699 + int ret; 700 700 + 701 701 + guard(mutex)(&data->lock); 702 702 + 703 703 + switch (attr) { 704 704 + case hwmon_pwm_enable: 705 705 + if (val == 0) 706 706 + data->hwmon_en.pwm_en[channel / 8] &= ~BIT(channel % 8); 707 707 + else if (val == 1) 708 708 + data->hwmon_en.pwm_en[channel / 8] |= BIT(channel % 8); 709 709 + else 710 710 + return -EINVAL; 711 711 + 712 712 + cmd_hd = (struct nct6694_cmd_header) { 713 713 + .mod = NCT6694_HWMON_MOD, 714 714 + .cmd = NCT6694_HWMON_CONTROL, 715 715 + .sel = NCT6694_HWMON_CONTROL_SEL, 716 716 + .len = cpu_to_le16(sizeof(data->hwmon_en)) 717 717 + }; 718 718 + 719 719 + return nct6694_write_msg(data->nct6694, &cmd_hd, 720 720 + &data->hwmon_en); 721 721 + case hwmon_pwm_input: 722 722 + if (val < 0 || val > 255) 723 723 + return -EINVAL; 724 724 + 725 725 + cmd_hd = (struct nct6694_cmd_header) { 726 726 + .mod = NCT6694_PWM_MOD, 727 727 + .cmd = NCT6694_PWM_CONTROL, 728 728 + .sel = NCT6694_PWM_CONTROL_SEL, 729 729 + .len = cpu_to_le16(sizeof(data->msg->pwm_ctrl)) 730 730 + }; 731 731 + 732 732 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 733 733 + &data->msg->pwm_ctrl); 734 734 + if (ret) 735 735 + return ret; 736 736 + 737 737 + data->msg->pwm_ctrl.mal_val[channel] = val; 738 738 + 739 739 + return nct6694_write_msg(data->nct6694, &cmd_hd, 740 740 + &data->msg->pwm_ctrl); 741 741 + case hwmon_pwm_freq: 742 742 + cmd_hd = (struct nct6694_cmd_header) { 743 743 + .mod = NCT6694_HWMON_MOD, 744 744 + .cmd = NCT6694_HWMON_CONTROL, 745 745 + .sel = NCT6694_HWMON_CONTROL_SEL, 746 746 + .len = cpu_to_le16(sizeof(data->hwmon_en)) 747 747 + }; 748 748 + 749 749 + data->hwmon_en.pwm_freq[channel] = NCT6694_FREQ_TO_REG(val); 750 750 + 751 751 + return nct6694_write_msg(data->nct6694, &cmd_hd, 752 752 + &data->hwmon_en); 753 753 + default: 754 754 + return -EOPNOTSUPP; 755 755 + } 756 756 + } 757 757 + 758 758 + static int nct6694_read(struct device *dev, enum hwmon_sensor_types type, 759 759 + u32 attr, int channel, long *val) 760 760 + { 761 761 + switch (type) { 762 762 + case hwmon_in: 763 763 + /* in mV */ 764 764 + return nct6694_in_read(dev, attr, channel, val); 765 765 + case hwmon_temp: 766 766 + /* in mC */ 767 767 + return nct6694_temp_read(dev, attr, channel, val); 768 768 + case hwmon_fan: 769 769 + /* in RPM */ 770 770 + return nct6694_fan_read(dev, attr, channel, val); 771 771 + case hwmon_pwm: 772 772 + /* in value 0~255 */ 773 773 + return nct6694_pwm_read(dev, attr, channel, val); 774 774 + default: 775 775 + return -EOPNOTSUPP; 776 776 + } 777 777 + } 778 778 + 779 779 + static int nct6694_write(struct device *dev, enum hwmon_sensor_types type, 780 780 + u32 attr, int channel, long val) 781 781 + { 782 782 + switch (type) { 783 783 + case hwmon_in: 784 784 + return nct6694_in_write(dev, attr, channel, val); 785 785 + case hwmon_temp: 786 786 + return nct6694_temp_write(dev, attr, channel, val); 787 787 + case hwmon_fan: 788 788 + return nct6694_fan_write(dev, attr, channel, val); 789 789 + case hwmon_pwm: 790 790 + return nct6694_pwm_write(dev, attr, channel, val); 791 791 + default: 792 792 + return -EOPNOTSUPP; 793 793 + } 794 794 + } 795 795 + 796 796 + static umode_t nct6694_is_visible(const void *data, 797 797 + enum hwmon_sensor_types type, 798 798 + u32 attr, int channel) 799 799 + { 800 800 + switch (type) { 801 801 + case hwmon_in: 802 802 + switch (attr) { 803 803 + case hwmon_in_enable: 804 804 + case hwmon_in_max: 805 805 + case hwmon_in_min: 806 806 + return 0644; 807 807 + case hwmon_in_alarm: 808 808 + case hwmon_in_input: 809 809 + return 0444; 810 810 + default: 811 811 + return 0; 812 812 + } 813 813 + case hwmon_temp: 814 814 + switch (attr) { 815 815 + case hwmon_temp_enable: 816 816 + case hwmon_temp_max: 817 817 + case hwmon_temp_max_hyst: 818 818 + return 0644; 819 819 + case hwmon_temp_input: 820 820 + case hwmon_temp_max_alarm: 821 821 + return 0444; 822 822 + default: 823 823 + return 0; 824 824 + } 825 825 + case hwmon_fan: 826 826 + switch (attr) { 827 827 + case hwmon_fan_enable: 828 828 + case hwmon_fan_min: 829 829 + return 0644; 830 830 + case hwmon_fan_input: 831 831 + case hwmon_fan_min_alarm: 832 832 + return 0444; 833 833 + default: 834 834 + return 0; 835 835 + } 836 836 + case hwmon_pwm: 837 837 + switch (attr) { 838 838 + case hwmon_pwm_enable: 839 839 + case hwmon_pwm_freq: 840 840 + case hwmon_pwm_input: 841 841 + return 0644; 842 842 + default: 843 843 + return 0; 844 844 + } 845 845 + default: 846 846 + return 0; 847 847 + } 848 848 + } 849 849 + 850 850 + static const struct hwmon_ops nct6694_hwmon_ops = { 851 851 + .is_visible = nct6694_is_visible, 852 852 + .read = nct6694_read, 853 853 + .write = nct6694_write, 854 854 + }; 855 855 + 856 856 + static const struct hwmon_chip_info nct6694_chip_info = { 857 857 + .ops = &nct6694_hwmon_ops, 858 858 + .info = nct6694_info, 859 859 + }; 860 860 + 861 861 + static int nct6694_hwmon_init(struct nct6694_hwmon_data *data) 862 862 + { 863 863 + struct nct6694_cmd_header cmd_hd = { 864 864 + .mod = NCT6694_HWMON_MOD, 865 865 + .cmd = NCT6694_HWMON_CONTROL, 866 866 + .sel = NCT6694_HWMON_CONTROL_SEL, 867 867 + .len = cpu_to_le16(sizeof(data->hwmon_en)) 868 868 + }; 869 869 + int ret; 870 870 + 871 871 + /* 872 872 + * Record each Hardware Monitor Channel enable status 873 873 + * and PWM frequency register 874 874 + */ 875 875 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 876 876 + &data->hwmon_en); 877 877 + if (ret) 878 878 + return ret; 879 879 + 880 880 + cmd_hd = (struct nct6694_cmd_header) { 881 881 + .mod = NCT6694_HWMON_MOD, 882 882 + .cmd = NCT6694_HWMON_ALARM, 883 883 + .sel = NCT6694_HWMON_ALARM_SEL, 884 884 + .len = cpu_to_le16(sizeof(data->msg->hwmon_alarm)) 885 885 + }; 886 886 + 887 887 + /* Select hwmon device alarm mode */ 888 888 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, 889 889 + &data->msg->hwmon_alarm); 890 890 + if (ret) 891 891 + return ret; 892 892 + 893 893 + data->msg->hwmon_alarm.smi_ctrl = NCT6694_HWMON_REALTIME_IRQ; 894 894 + 895 895 + return nct6694_write_msg(data->nct6694, &cmd_hd, 896 896 + &data->msg->hwmon_alarm); 897 897 + } 898 898 + 899 899 + static int nct6694_hwmon_probe(struct platform_device *pdev) 900 900 + { 901 901 + struct nct6694_hwmon_data *data; 902 902 + struct nct6694 *nct6694 = dev_get_drvdata(pdev->dev.parent); 903 903 + struct device *hwmon_dev; 904 904 + int ret; 905 905 + 906 906 + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 907 907 + if (!data) 908 908 + return -ENOMEM; 909 909 + 910 910 + data->rpt = devm_kzalloc(&pdev->dev, sizeof(union nct6694_hwmon_rpt), 911 911 + GFP_KERNEL); 912 912 + if (!data->rpt) 913 913 + return -ENOMEM; 914 914 + 915 915 + data->msg = devm_kzalloc(&pdev->dev, sizeof(union nct6694_hwmon_msg), 916 916 + GFP_KERNEL); 917 917 + if (!data->msg) 918 918 + return -ENOMEM; 919 919 + 920 920 + data->nct6694 = nct6694; 921 921 + ret = devm_mutex_init(&pdev->dev, &data->lock); 922 922 + if (ret) 923 923 + return ret; 924 924 + 925 925 + ret = nct6694_hwmon_init(data); 926 926 + if (ret) 927 927 + return ret; 928 928 + 929 929 + /* Register hwmon device to HWMON framework */ 930 930 + hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, 931 931 + "nct6694", data, 932 932 + &nct6694_chip_info, 933 933 + NULL); 934 934 + return PTR_ERR_OR_ZERO(hwmon_dev); 935 935 + } 936 936 + 937 937 + static struct platform_driver nct6694_hwmon_driver = { 938 938 + .driver = { 939 939 + .name = "nct6694-hwmon", 940 940 + }, 941 941 + .probe = nct6694_hwmon_probe, 942 942 + }; 943 943 + 944 944 + module_platform_driver(nct6694_hwmon_driver); 945 945 + 946 946 + MODULE_DESCRIPTION("USB-HWMON driver for NCT6694"); 947 947 + MODULE_AUTHOR("Ming Yu <tmyu0@nuvoton.com>"); 948 948 + MODULE_LICENSE("GPL"); 949 949 + MODULE_ALIAS("platform:nct6694-hwmon");

+10

drivers/i2c/busses/Kconfig

reviewed

··· 1357 1357 This driver can also be built as a module. If so, the module 1358 1358 will be called i2c-ljca. 1359 1359 1360 1360 + config I2C_NCT6694 1361 1361 + tristate "Nuvoton NCT6694 I2C adapter support" 1362 1362 + depends on MFD_NCT6694 1363 1363 + help 1364 1364 + If you say yes to this option, support will be included for Nuvoton 1365 1365 + NCT6694, a USB to I2C interface. 1366 1366 + 1367 1367 + This driver can also be built as a module. If so, the module will 1368 1368 + be called i2c-nct6694. 1369 1369 + 1360 1370 config I2C_CP2615 1361 1371 tristate "Silicon Labs CP2615 USB sound card and I2C adapter" 1362 1372 depends on USB

+1

drivers/i2c/busses/Makefile

reviewed

··· 135 135 obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o 136 136 obj-$(CONFIG_I2C_DLN2) += i2c-dln2.o 137 137 obj-$(CONFIG_I2C_LJCA) += i2c-ljca.o 138 138 + obj-$(CONFIG_I2C_NCT6694) += i2c-nct6694.o 138 139 obj-$(CONFIG_I2C_CP2615) += i2c-cp2615.o 139 140 obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o 140 141 obj-$(CONFIG_I2C_PCI1XXXX) += i2c-mchp-pci1xxxx.o

+196

drivers/i2c/busses/i2c-nct6694.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Nuvoton NCT6694 I2C adapter driver based on USB interface. 4 4 + * 5 5 + * Copyright (C) 2025 Nuvoton Technology Corp. 6 6 + */ 7 7 + 8 8 + #include <linux/i2c.h> 9 9 + #include <linux/idr.h> 10 10 + #include <linux/kernel.h> 11 11 + #include <linux/mfd/nct6694.h> 12 12 + #include <linux/module.h> 13 13 + #include <linux/platform_device.h> 14 14 + 15 15 + /* 16 16 + * USB command module type for NCT6694 I2C controller. 17 17 + * This defines the module type used for communication with the NCT6694 18 18 + * I2C controller over the USB interface. 19 19 + */ 20 20 + #define NCT6694_I2C_MOD 0x03 21 21 + 22 22 + /* Command 00h - I2C Deliver */ 23 23 + #define NCT6694_I2C_DELIVER 0x00 24 24 + #define NCT6694_I2C_DELIVER_SEL 0x00 25 25 + 26 26 + #define NCT6694_I2C_MAX_XFER_SIZE 64 27 27 + #define NCT6694_I2C_MAX_DEVS 6 28 28 + 29 29 + static unsigned char br_reg[NCT6694_I2C_MAX_DEVS] = {[0 ... (NCT6694_I2C_MAX_DEVS - 1)] = 0xFF}; 30 30 + 31 31 + module_param_array(br_reg, byte, NULL, 0644); 32 32 + MODULE_PARM_DESC(br_reg, 33 33 + "I2C Baudrate register per adapter: (0=25K, 1=50K, 2=100K, 3=200K, 4=400K, 5=800K, 6=1M), default=2"); 34 34 + 35 35 + enum nct6694_i2c_baudrate { 36 36 + NCT6694_I2C_BR_25K = 0, 37 37 + NCT6694_I2C_BR_50K, 38 38 + NCT6694_I2C_BR_100K, 39 39 + NCT6694_I2C_BR_200K, 40 40 + NCT6694_I2C_BR_400K, 41 41 + NCT6694_I2C_BR_800K, 42 42 + NCT6694_I2C_BR_1M 43 43 + }; 44 44 + 45 45 + struct __packed nct6694_i2c_deliver { 46 46 + u8 port; 47 47 + u8 br; 48 48 + u8 addr; 49 49 + u8 w_cnt; 50 50 + u8 r_cnt; 51 51 + u8 rsv[11]; 52 52 + u8 write_data[NCT6694_I2C_MAX_XFER_SIZE]; 53 53 + u8 read_data[NCT6694_I2C_MAX_XFER_SIZE]; 54 54 + }; 55 55 + 56 56 + struct nct6694_i2c_data { 57 57 + struct device *dev; 58 58 + struct nct6694 *nct6694; 59 59 + struct i2c_adapter adapter; 60 60 + struct nct6694_i2c_deliver deliver; 61 61 + unsigned char port; 62 62 + unsigned char br; 63 63 + }; 64 64 + 65 65 + static int nct6694_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 66 66 + { 67 67 + struct nct6694_i2c_data *data = adap->algo_data; 68 68 + struct nct6694_i2c_deliver *deliver = &data->deliver; 69 69 + static const struct nct6694_cmd_header cmd_hd = { 70 70 + .mod = NCT6694_I2C_MOD, 71 71 + .cmd = NCT6694_I2C_DELIVER, 72 72 + .sel = NCT6694_I2C_DELIVER_SEL, 73 73 + .len = cpu_to_le16(sizeof(*deliver)) 74 74 + }; 75 75 + int ret, i; 76 76 + 77 77 + for (i = 0; i < num; i++) { 78 78 + struct i2c_msg *msg_temp = &msgs[i]; 79 79 + 80 80 + memset(deliver, 0, sizeof(*deliver)); 81 81 + 82 82 + deliver->port = data->port; 83 83 + deliver->br = data->br; 84 84 + deliver->addr = i2c_8bit_addr_from_msg(msg_temp); 85 85 + if (msg_temp->flags & I2C_M_RD) { 86 86 + deliver->r_cnt = msg_temp->len; 87 87 + ret = nct6694_write_msg(data->nct6694, &cmd_hd, deliver); 88 88 + if (ret < 0) 89 89 + return ret; 90 90 + 91 91 + memcpy(msg_temp->buf, deliver->read_data, msg_temp->len); 92 92 + } else { 93 93 + deliver->w_cnt = msg_temp->len; 94 94 + memcpy(deliver->write_data, msg_temp->buf, msg_temp->len); 95 95 + ret = nct6694_write_msg(data->nct6694, &cmd_hd, deliver); 96 96 + if (ret < 0) 97 97 + return ret; 98 98 + } 99 99 + } 100 100 + 101 101 + return num; 102 102 + } 103 103 + 104 104 + static u32 nct6694_i2c_func(struct i2c_adapter *adapter) 105 105 + { 106 106 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 107 107 + } 108 108 + 109 109 + static const struct i2c_adapter_quirks nct6694_i2c_quirks = { 110 110 + .max_read_len = NCT6694_I2C_MAX_XFER_SIZE, 111 111 + .max_write_len = NCT6694_I2C_MAX_XFER_SIZE, 112 112 + }; 113 113 + 114 114 + static const struct i2c_algorithm nct6694_i2c_algo = { 115 115 + .xfer = nct6694_i2c_xfer, 116 116 + .functionality = nct6694_i2c_func, 117 117 + }; 118 118 + 119 119 + static int nct6694_i2c_set_baudrate(struct nct6694_i2c_data *data) 120 120 + { 121 121 + if (data->port >= NCT6694_I2C_MAX_DEVS) { 122 122 + dev_err(data->dev, "Invalid I2C port index %d\n", data->port); 123 123 + return -EINVAL; 124 124 + } 125 125 + 126 126 + if (br_reg[data->port] > NCT6694_I2C_BR_1M) { 127 127 + dev_warn(data->dev, "Invalid baudrate %d for I2C%d, using 100K\n", 128 128 + br_reg[data->port], data->port); 129 129 + br_reg[data->port] = NCT6694_I2C_BR_100K; 130 130 + } 131 131 + 132 132 + data->br = br_reg[data->port]; 133 133 + 134 134 + return 0; 135 135 + } 136 136 + 137 137 + static void nct6694_i2c_ida_free(void *d) 138 138 + { 139 139 + struct nct6694_i2c_data *data = d; 140 140 + struct nct6694 *nct6694 = data->nct6694; 141 141 + 142 142 + ida_free(&nct6694->i2c_ida, data->port); 143 143 + } 144 144 + 145 145 + static int nct6694_i2c_probe(struct platform_device *pdev) 146 146 + { 147 147 + struct device *dev = &pdev->dev; 148 148 + struct nct6694 *nct6694 = dev_get_drvdata(dev->parent); 149 149 + struct nct6694_i2c_data *data; 150 150 + int ret; 151 151 + 152 152 + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 153 153 + if (!data) 154 154 + return -ENOMEM; 155 155 + 156 156 + data->dev = dev; 157 157 + data->nct6694 = nct6694; 158 158 + 159 159 + ret = ida_alloc(&nct6694->i2c_ida, GFP_KERNEL); 160 160 + if (ret < 0) 161 161 + return ret; 162 162 + data->port = ret; 163 163 + 164 164 + ret = devm_add_action_or_reset(dev, nct6694_i2c_ida_free, data); 165 165 + if (ret) 166 166 + return ret; 167 167 + 168 168 + ret = nct6694_i2c_set_baudrate(data); 169 169 + if (ret) 170 170 + return ret; 171 171 + 172 172 + sprintf(data->adapter.name, "NCT6694 I2C Adapter %d", data->port); 173 173 + data->adapter.owner = THIS_MODULE; 174 174 + data->adapter.algo = &nct6694_i2c_algo; 175 175 + data->adapter.quirks = &nct6694_i2c_quirks; 176 176 + data->adapter.dev.parent = dev; 177 177 + data->adapter.algo_data = data; 178 178 + 179 179 + platform_set_drvdata(pdev, data); 180 180 + 181 181 + return devm_i2c_add_adapter(dev, &data->adapter); 182 182 + } 183 183 + 184 184 + static struct platform_driver nct6694_i2c_driver = { 185 185 + .driver = { 186 186 + .name = "nct6694-i2c", 187 187 + }, 188 188 + .probe = nct6694_i2c_probe, 189 189 + }; 190 190 + 191 191 + module_platform_driver(nct6694_i2c_driver); 192 192 + 193 193 + MODULE_DESCRIPTION("USB-I2C adapter driver for NCT6694"); 194 194 + MODULE_AUTHOR("Ming Yu <tmyu0@nuvoton.com>"); 195 195 + MODULE_LICENSE("GPL"); 196 196 + MODULE_ALIAS("platform:nct6694-i2c");

+12

drivers/input/keyboard/Kconfig

reviewed

··· 422 422 To compile this driver as a module, choose M here: the 423 423 module will be called max7359_keypad. 424 424 425 425 + config KEYBOARD_MAX7360 426 426 + tristate "Maxim MAX7360 Key Switch Controller" 427 427 + select INPUT_MATRIXKMAP 428 428 + depends on I2C 429 429 + depends on MFD_MAX7360 430 430 + help 431 431 + If you say yes here you get support for the keypad controller on the 432 432 + Maxim MAX7360 I/O Expander. 433 433 + 434 434 + To compile this driver as a module, choose M here: the module will be 435 435 + called max7360_keypad. 436 436 + 425 437 config KEYBOARD_MPR121 426 438 tristate "Freescale MPR121 Touchkey" 427 439 depends on I2C

+1

drivers/input/keyboard/Makefile

reviewed

··· 42 42 obj-$(CONFIG_KEYBOARD_MAPLE) += maple_keyb.o 43 43 obj-$(CONFIG_KEYBOARD_MATRIX) += matrix_keypad.o 44 44 obj-$(CONFIG_KEYBOARD_MAX7359) += max7359_keypad.o 45 45 + obj-$(CONFIG_KEYBOARD_MAX7360) += max7360-keypad.o 45 46 obj-$(CONFIG_KEYBOARD_MPR121) += mpr121_touchkey.o 46 47 obj-$(CONFIG_KEYBOARD_MT6779) += mt6779-keypad.o 47 48 obj-$(CONFIG_KEYBOARD_MTK_PMIC) += mtk-pmic-keys.o

+308

drivers/input/keyboard/max7360-keypad.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright 2025 Bootlin 4 4 + * 5 5 + * Author: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 6 6 + */ 7 7 + 8 8 + #include <linux/bitfield.h> 9 9 + #include <linux/bitops.h> 10 10 + #include <linux/dev_printk.h> 11 11 + #include <linux/device/devres.h> 12 12 + #include <linux/err.h> 13 13 + #include <linux/init.h> 14 14 + #include <linux/input.h> 15 15 + #include <linux/input/matrix_keypad.h> 16 16 + #include <linux/interrupt.h> 17 17 + #include <linux/mfd/max7360.h> 18 18 + #include <linux/mod_devicetable.h> 19 19 + #include <linux/minmax.h> 20 20 + #include <linux/module.h> 21 21 + #include <linux/property.h> 22 22 + #include <linux/platform_device.h> 23 23 + #include <linux/pm_wakeirq.h> 24 24 + #include <linux/regmap.h> 25 25 + 26 26 + struct max7360_keypad { 27 27 + struct input_dev *input; 28 28 + unsigned int rows; 29 29 + unsigned int cols; 30 30 + unsigned int debounce_ms; 31 31 + int irq; 32 32 + struct regmap *regmap; 33 33 + unsigned short keycodes[MAX7360_MAX_KEY_ROWS * MAX7360_MAX_KEY_COLS]; 34 34 + }; 35 35 + 36 36 + static irqreturn_t max7360_keypad_irq(int irq, void *data) 37 37 + { 38 38 + struct max7360_keypad *max7360_keypad = data; 39 39 + struct device *dev = max7360_keypad->input->dev.parent; 40 40 + unsigned int val; 41 41 + unsigned int row, col; 42 42 + unsigned int release; 43 43 + unsigned int code; 44 44 + int error; 45 45 + 46 46 + error = regmap_read(max7360_keypad->regmap, MAX7360_REG_KEYFIFO, &val); 47 47 + if (error) { 48 48 + dev_err(dev, "Failed to read MAX7360 FIFO"); 49 49 + return IRQ_NONE; 50 50 + } 51 51 + 52 52 + /* FIFO overflow: ignore it and get next event. */ 53 53 + if (val == MAX7360_FIFO_OVERFLOW) { 54 54 + dev_warn(dev, "max7360 FIFO overflow"); 55 55 + error = regmap_read_poll_timeout(max7360_keypad->regmap, MAX7360_REG_KEYFIFO, 56 56 + val, val != MAX7360_FIFO_OVERFLOW, 0, 1000); 57 57 + if (error) { 58 58 + dev_err(dev, "Failed to empty MAX7360 FIFO"); 59 59 + return IRQ_NONE; 60 60 + } 61 61 + } 62 62 + 63 63 + if (val == MAX7360_FIFO_EMPTY) { 64 64 + dev_dbg(dev, "Got a spurious interrupt"); 65 65 + 66 66 + return IRQ_NONE; 67 67 + } 68 68 + 69 69 + row = FIELD_GET(MAX7360_FIFO_ROW, val); 70 70 + col = FIELD_GET(MAX7360_FIFO_COL, val); 71 71 + release = val & MAX7360_FIFO_RELEASE; 72 72 + 73 73 + code = MATRIX_SCAN_CODE(row, col, get_count_order(max7360_keypad->cols)); 74 74 + 75 75 + dev_dbg(dev, "key[%d:%d] %s\n", row, col, release ? "release" : "press"); 76 76 + 77 77 + input_event(max7360_keypad->input, EV_MSC, MSC_SCAN, code); 78 78 + input_report_key(max7360_keypad->input, max7360_keypad->keycodes[code], !release); 79 79 + input_sync(max7360_keypad->input); 80 80 + 81 81 + return IRQ_HANDLED; 82 82 + } 83 83 + 84 84 + static int max7360_keypad_open(struct input_dev *pdev) 85 85 + { 86 86 + struct max7360_keypad *max7360_keypad = input_get_drvdata(pdev); 87 87 + struct device *dev = max7360_keypad->input->dev.parent; 88 88 + int error; 89 89 + 90 90 + /* Somebody is using the device: get out of sleep. */ 91 91 + error = regmap_write_bits(max7360_keypad->regmap, MAX7360_REG_CONFIG, 92 92 + MAX7360_CFG_SLEEP, MAX7360_CFG_SLEEP); 93 93 + if (error) 94 94 + dev_err(dev, "Failed to write max7360 configuration: %d\n", error); 95 95 + 96 96 + return error; 97 97 + } 98 98 + 99 99 + static void max7360_keypad_close(struct input_dev *pdev) 100 100 + { 101 101 + struct max7360_keypad *max7360_keypad = input_get_drvdata(pdev); 102 102 + struct device *dev = max7360_keypad->input->dev.parent; 103 103 + int error; 104 104 + 105 105 + /* Nobody is using the device anymore: go to sleep. */ 106 106 + error = regmap_write_bits(max7360_keypad->regmap, MAX7360_REG_CONFIG, MAX7360_CFG_SLEEP, 0); 107 107 + if (error) 108 108 + dev_err(dev, "Failed to write max7360 configuration: %d\n", error); 109 109 + } 110 110 + 111 111 + static int max7360_keypad_hw_init(struct max7360_keypad *max7360_keypad) 112 112 + { 113 113 + struct device *dev = max7360_keypad->input->dev.parent; 114 114 + unsigned int val; 115 115 + int error; 116 116 + 117 117 + val = max7360_keypad->debounce_ms - MAX7360_DEBOUNCE_MIN; 118 118 + error = regmap_write_bits(max7360_keypad->regmap, MAX7360_REG_DEBOUNCE, 119 119 + MAX7360_DEBOUNCE, 120 120 + FIELD_PREP(MAX7360_DEBOUNCE, val)); 121 121 + if (error) 122 122 + return dev_err_probe(dev, error, 123 123 + "Failed to write max7360 debounce configuration\n"); 124 124 + 125 125 + error = regmap_write_bits(max7360_keypad->regmap, MAX7360_REG_INTERRUPT, 126 126 + MAX7360_INTERRUPT_TIME_MASK, 127 127 + FIELD_PREP(MAX7360_INTERRUPT_TIME_MASK, 1)); 128 128 + if (error) 129 129 + return dev_err_probe(dev, error, 130 130 + "Failed to write max7360 keypad interrupt configuration\n"); 131 131 + 132 132 + return 0; 133 133 + } 134 134 + 135 135 + static int max7360_keypad_build_keymap(struct max7360_keypad *max7360_keypad) 136 136 + { 137 137 + struct input_dev *input_dev = max7360_keypad->input; 138 138 + struct device *dev = input_dev->dev.parent->parent; 139 139 + struct matrix_keymap_data keymap_data; 140 140 + const char *propname = "linux,keymap"; 141 141 + unsigned int max_keys; 142 142 + int error; 143 143 + int size; 144 144 + 145 145 + size = device_property_count_u32(dev, propname); 146 146 + if (size <= 0) { 147 147 + dev_err(dev, "missing or malformed property %s: %d\n", propname, size); 148 148 + return size < 0 ? size : -EINVAL; 149 149 + } 150 150 + 151 151 + max_keys = max7360_keypad->cols * max7360_keypad->rows; 152 152 + if (size > max_keys) { 153 153 + dev_err(dev, "%s size overflow (%d vs max %u)\n", propname, size, max_keys); 154 154 + return -EINVAL; 155 155 + } 156 156 + 157 157 + u32 *keys __free(kfree) = kmalloc_array(size, sizeof(*keys), GFP_KERNEL); 158 158 + if (!keys) 159 159 + return -ENOMEM; 160 160 + 161 161 + error = device_property_read_u32_array(dev, propname, keys, size); 162 162 + if (error) { 163 163 + dev_err(dev, "failed to read %s property: %d\n", propname, error); 164 164 + return error; 165 165 + } 166 166 + 167 167 + keymap_data.keymap = keys; 168 168 + keymap_data.keymap_size = size; 169 169 + error = matrix_keypad_build_keymap(&keymap_data, NULL, 170 170 + max7360_keypad->rows, max7360_keypad->cols, 171 171 + max7360_keypad->keycodes, max7360_keypad->input); 172 172 + if (error) 173 173 + return error; 174 174 + 175 175 + return 0; 176 176 + } 177 177 + 178 178 + static int max7360_keypad_parse_fw(struct device *dev, 179 179 + struct max7360_keypad *max7360_keypad, 180 180 + bool *autorepeat) 181 181 + { 182 182 + int error; 183 183 + 184 184 + error = matrix_keypad_parse_properties(dev->parent, &max7360_keypad->rows, 185 185 + &max7360_keypad->cols); 186 186 + if (error) 187 187 + return error; 188 188 + 189 189 + if (!max7360_keypad->rows || !max7360_keypad->cols || 190 190 + max7360_keypad->rows > MAX7360_MAX_KEY_ROWS || 191 191 + max7360_keypad->cols > MAX7360_MAX_KEY_COLS) { 192 192 + dev_err(dev, "Invalid number of columns or rows (%ux%u)\n", 193 193 + max7360_keypad->cols, max7360_keypad->rows); 194 194 + return -EINVAL; 195 195 + } 196 196 + 197 197 + *autorepeat = device_property_read_bool(dev->parent, "autorepeat"); 198 198 + 199 199 + max7360_keypad->debounce_ms = MAX7360_DEBOUNCE_MIN; 200 200 + error = device_property_read_u32(dev->parent, "keypad-debounce-delay-ms", 201 201 + &max7360_keypad->debounce_ms); 202 202 + if (error == -EINVAL) { 203 203 + dev_info(dev, "Using default keypad-debounce-delay-ms: %u\n", 204 204 + max7360_keypad->debounce_ms); 205 205 + } else if (error < 0) { 206 206 + dev_err(dev, "Failed to read keypad-debounce-delay-ms property\n"); 207 207 + return error; 208 208 + } 209 209 + 210 210 + if (!in_range(max7360_keypad->debounce_ms, MAX7360_DEBOUNCE_MIN, 211 211 + MAX7360_DEBOUNCE_MAX - MAX7360_DEBOUNCE_MIN + 1)) { 212 212 + dev_err(dev, "Invalid keypad-debounce-delay-ms: %u, should be between %u and %u.\n", 213 213 + max7360_keypad->debounce_ms, MAX7360_DEBOUNCE_MIN, MAX7360_DEBOUNCE_MAX); 214 214 + return -EINVAL; 215 215 + } 216 216 + 217 217 + return 0; 218 218 + } 219 219 + 220 220 + static int max7360_keypad_probe(struct platform_device *pdev) 221 221 + { 222 222 + struct max7360_keypad *max7360_keypad; 223 223 + struct device *dev = &pdev->dev; 224 224 + struct input_dev *input; 225 225 + struct regmap *regmap; 226 226 + bool autorepeat; 227 227 + int error; 228 228 + int irq; 229 229 + 230 230 + regmap = dev_get_regmap(dev->parent, NULL); 231 231 + if (!regmap) 232 232 + return dev_err_probe(dev, -ENODEV, "Could not get parent regmap\n"); 233 233 + 234 234 + irq = fwnode_irq_get_byname(dev_fwnode(dev->parent), "intk"); 235 235 + if (irq < 0) 236 236 + return dev_err_probe(dev, irq, "Failed to get IRQ\n"); 237 237 + 238 238 + max7360_keypad = devm_kzalloc(dev, sizeof(*max7360_keypad), GFP_KERNEL); 239 239 + if (!max7360_keypad) 240 240 + return -ENOMEM; 241 241 + 242 242 + max7360_keypad->regmap = regmap; 243 243 + 244 244 + error = max7360_keypad_parse_fw(dev, max7360_keypad, &autorepeat); 245 245 + if (error) 246 246 + return error; 247 247 + 248 248 + input = devm_input_allocate_device(dev); 249 249 + if (!input) 250 250 + return -ENOMEM; 251 251 + 252 252 + max7360_keypad->input = input; 253 253 + 254 254 + input->id.bustype = BUS_I2C; 255 255 + input->name = pdev->name; 256 256 + input->open = max7360_keypad_open; 257 257 + input->close = max7360_keypad_close; 258 258 + 259 259 + error = max7360_keypad_build_keymap(max7360_keypad); 260 260 + if (error) 261 261 + return dev_err_probe(dev, error, "Failed to build keymap\n"); 262 262 + 263 263 + input_set_capability(input, EV_MSC, MSC_SCAN); 264 264 + if (autorepeat) 265 265 + __set_bit(EV_REP, input->evbit); 266 266 + 267 267 + input_set_drvdata(input, max7360_keypad); 268 268 + 269 269 + error = devm_request_threaded_irq(dev, irq, NULL, max7360_keypad_irq, 270 270 + IRQF_ONESHOT, 271 271 + "max7360-keypad", max7360_keypad); 272 272 + if (error) 273 273 + return dev_err_probe(dev, error, "Failed to register interrupt\n"); 274 274 + 275 275 + error = input_register_device(input); 276 276 + if (error) 277 277 + return dev_err_probe(dev, error, "Could not register input device\n"); 278 278 + 279 279 + error = max7360_keypad_hw_init(max7360_keypad); 280 280 + if (error) 281 281 + return dev_err_probe(dev, error, "Failed to initialize max7360 keypad\n"); 282 282 + 283 283 + device_init_wakeup(dev, true); 284 284 + error = dev_pm_set_wake_irq(dev, irq); 285 285 + if (error) 286 286 + dev_warn(dev, "Failed to set up wakeup irq: %d\n", error); 287 287 + 288 288 + return 0; 289 289 + } 290 290 + 291 291 + static void max7360_keypad_remove(struct platform_device *pdev) 292 292 + { 293 293 + dev_pm_clear_wake_irq(&pdev->dev); 294 294 + device_init_wakeup(&pdev->dev, false); 295 295 + } 296 296 + 297 297 + static struct platform_driver max7360_keypad_driver = { 298 298 + .driver = { 299 299 + .name = "max7360-keypad", 300 300 + }, 301 301 + .probe = max7360_keypad_probe, 302 302 + .remove = max7360_keypad_remove, 303 303 + }; 304 304 + module_platform_driver(max7360_keypad_driver); 305 305 + 306 306 + MODULE_DESCRIPTION("MAX7360 Keypad driver"); 307 307 + MODULE_AUTHOR("Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>"); 308 308 + MODULE_LICENSE("GPL");

+10

drivers/input/misc/Kconfig

reviewed

··· 230 230 tristate "M68k Beeper support" 231 231 depends on M68K 232 232 233 233 + config INPUT_MAX7360_ROTARY 234 234 + tristate "Maxim MAX7360 Rotary Encoder" 235 235 + depends on MFD_MAX7360 236 236 + help 237 237 + If you say yes here you get support for the rotary encoder on the 238 238 + Maxim MAX7360 I/O Expander. 239 239 + 240 240 + To compile this driver as a module, choose M here: the module will be 241 241 + called max7360_rotary. 242 242 + 233 243 config INPUT_MAX77650_ONKEY 234 244 tristate "Maxim MAX77650 ONKEY support" 235 245 depends on MFD_MAX77650

+1

drivers/input/misc/Makefile

reviewed

··· 51 51 obj-$(CONFIG_INPUT_KEYSPAN_REMOTE) += keyspan_remote.o 52 52 obj-$(CONFIG_INPUT_KXTJ9) += kxtj9.o 53 53 obj-$(CONFIG_INPUT_M68K_BEEP) += m68kspkr.o 54 54 + obj-$(CONFIG_INPUT_MAX7360_ROTARY) += max7360-rotary.o 54 55 obj-$(CONFIG_INPUT_MAX77650_ONKEY) += max77650-onkey.o 55 56 obj-$(CONFIG_INPUT_MAX77693_HAPTIC) += max77693-haptic.o 56 57 obj-$(CONFIG_INPUT_MAX8925_ONKEY) += max8925_onkey.o

+192

drivers/input/misc/max7360-rotary.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright 2025 Bootlin 4 4 + * 5 5 + * Author: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 6 6 + */ 7 7 + 8 8 + #include <linux/bitfield.h> 9 9 + #include <linux/device/devres.h> 10 10 + #include <linux/dev_printk.h> 11 11 + #include <linux/init.h> 12 12 + #include <linux/input.h> 13 13 + #include <linux/interrupt.h> 14 14 + #include <linux/mfd/max7360.h> 15 15 + #include <linux/property.h> 16 16 + #include <linux/platform_device.h> 17 17 + #include <linux/pm_wakeirq.h> 18 18 + #include <linux/regmap.h> 19 19 + #include <linux/types.h> 20 20 + 21 21 + #define MAX7360_ROTARY_DEFAULT_STEPS 24 22 22 + 23 23 + struct max7360_rotary { 24 24 + struct input_dev *input; 25 25 + struct regmap *regmap; 26 26 + unsigned int debounce_ms; 27 27 + 28 28 + unsigned int pos; 29 29 + 30 30 + u32 steps; 31 31 + u32 axis; 32 32 + bool relative_axis; 33 33 + bool rollover; 34 34 + }; 35 35 + 36 36 + static void max7360_rotary_report_event(struct max7360_rotary *max7360_rotary, int steps) 37 37 + { 38 38 + if (max7360_rotary->relative_axis) { 39 39 + input_report_rel(max7360_rotary->input, max7360_rotary->axis, steps); 40 40 + } else { 41 41 + int pos = max7360_rotary->pos; 42 42 + int maxval = max7360_rotary->steps; 43 43 + 44 44 + /* 45 45 + * Add steps to the position. 46 46 + * Make sure added steps are always in ]-maxval; maxval[ 47 47 + * interval, so (pos + maxval) is always >= 0. 48 48 + * Then set back pos to the [0; maxval[ interval. 49 49 + */ 50 50 + pos += steps % maxval; 51 51 + if (max7360_rotary->rollover) 52 52 + pos = (pos + maxval) % maxval; 53 53 + else 54 54 + pos = clamp(pos, 0, maxval - 1); 55 55 + 56 56 + max7360_rotary->pos = pos; 57 57 + input_report_abs(max7360_rotary->input, max7360_rotary->axis, max7360_rotary->pos); 58 58 + } 59 59 + 60 60 + input_sync(max7360_rotary->input); 61 61 + } 62 62 + 63 63 + static irqreturn_t max7360_rotary_irq(int irq, void *data) 64 64 + { 65 65 + struct max7360_rotary *max7360_rotary = data; 66 66 + struct device *dev = max7360_rotary->input->dev.parent; 67 67 + unsigned int val; 68 68 + int error; 69 69 + 70 70 + error = regmap_read(max7360_rotary->regmap, MAX7360_REG_RTR_CNT, &val); 71 71 + if (error < 0) { 72 72 + dev_err(dev, "Failed to read rotary counter\n"); 73 73 + return IRQ_NONE; 74 74 + } 75 75 + 76 76 + if (val == 0) 77 77 + return IRQ_NONE; 78 78 + 79 79 + max7360_rotary_report_event(max7360_rotary, sign_extend32(val, 7)); 80 80 + 81 81 + return IRQ_HANDLED; 82 82 + } 83 83 + 84 84 + static int max7360_rotary_hw_init(struct max7360_rotary *max7360_rotary) 85 85 + { 86 86 + struct device *dev = max7360_rotary->input->dev.parent; 87 87 + int val; 88 88 + int error; 89 89 + 90 90 + val = FIELD_PREP(MAX7360_ROT_DEBOUNCE, max7360_rotary->debounce_ms) | 91 91 + FIELD_PREP(MAX7360_ROT_INTCNT, 1) | MAX7360_ROT_INTCNT_DLY; 92 92 + error = regmap_write(max7360_rotary->regmap, MAX7360_REG_RTRCFG, val); 93 93 + if (error) 94 94 + dev_err(dev, "Failed to set max7360 rotary encoder configuration\n"); 95 95 + 96 96 + return error; 97 97 + } 98 98 + 99 99 + static int max7360_rotary_probe(struct platform_device *pdev) 100 100 + { 101 101 + struct max7360_rotary *max7360_rotary; 102 102 + struct device *dev = &pdev->dev; 103 103 + struct input_dev *input; 104 104 + struct regmap *regmap; 105 105 + int irq; 106 106 + int error; 107 107 + 108 108 + regmap = dev_get_regmap(dev->parent, NULL); 109 109 + if (!regmap) 110 110 + return dev_err_probe(dev, -ENODEV, "Could not get parent regmap\n"); 111 111 + 112 112 + irq = fwnode_irq_get_byname(dev_fwnode(dev->parent), "inti"); 113 113 + if (irq < 0) 114 114 + return dev_err_probe(dev, irq, "Failed to get IRQ\n"); 115 115 + 116 116 + max7360_rotary = devm_kzalloc(dev, sizeof(*max7360_rotary), GFP_KERNEL); 117 117 + if (!max7360_rotary) 118 118 + return -ENOMEM; 119 119 + 120 120 + max7360_rotary->regmap = regmap; 121 121 + 122 122 + device_property_read_u32(dev->parent, "linux,axis", &max7360_rotary->axis); 123 123 + max7360_rotary->rollover = device_property_read_bool(dev->parent, 124 124 + "rotary-encoder,rollover"); 125 125 + max7360_rotary->relative_axis = 126 126 + device_property_read_bool(dev->parent, "rotary-encoder,relative-axis"); 127 127 + 128 128 + error = device_property_read_u32(dev->parent, "rotary-encoder,steps", 129 129 + &max7360_rotary->steps); 130 130 + if (error) 131 131 + max7360_rotary->steps = MAX7360_ROTARY_DEFAULT_STEPS; 132 132 + 133 133 + device_property_read_u32(dev->parent, "rotary-debounce-delay-ms", 134 134 + &max7360_rotary->debounce_ms); 135 135 + if (max7360_rotary->debounce_ms > MAX7360_ROT_DEBOUNCE_MAX) 136 136 + return dev_err_probe(dev, -EINVAL, "Invalid debounce timing: %u\n", 137 137 + max7360_rotary->debounce_ms); 138 138 + 139 139 + input = devm_input_allocate_device(dev); 140 140 + if (!input) 141 141 + return -ENOMEM; 142 142 + 143 143 + max7360_rotary->input = input; 144 144 + 145 145 + input->id.bustype = BUS_I2C; 146 146 + input->name = pdev->name; 147 147 + 148 148 + if (max7360_rotary->relative_axis) 149 149 + input_set_capability(input, EV_REL, max7360_rotary->axis); 150 150 + else 151 151 + input_set_abs_params(input, max7360_rotary->axis, 0, max7360_rotary->steps, 0, 1); 152 152 + 153 153 + error = devm_request_threaded_irq(dev, irq, NULL, max7360_rotary_irq, 154 154 + IRQF_ONESHOT | IRQF_SHARED, 155 155 + "max7360-rotary", max7360_rotary); 156 156 + if (error) 157 157 + return dev_err_probe(dev, error, "Failed to register interrupt\n"); 158 158 + 159 159 + error = input_register_device(input); 160 160 + if (error) 161 161 + return dev_err_probe(dev, error, "Could not register input device\n"); 162 162 + 163 163 + error = max7360_rotary_hw_init(max7360_rotary); 164 164 + if (error) 165 165 + return dev_err_probe(dev, error, "Failed to initialize max7360 rotary\n"); 166 166 + 167 167 + device_init_wakeup(dev, true); 168 168 + error = dev_pm_set_wake_irq(dev, irq); 169 169 + if (error) 170 170 + dev_warn(dev, "Failed to set up wakeup irq: %d\n", error); 171 171 + 172 172 + return 0; 173 173 + } 174 174 + 175 175 + static void max7360_rotary_remove(struct platform_device *pdev) 176 176 + { 177 177 + dev_pm_clear_wake_irq(&pdev->dev); 178 178 + device_init_wakeup(&pdev->dev, false); 179 179 + } 180 180 + 181 181 + static struct platform_driver max7360_rotary_driver = { 182 182 + .driver = { 183 183 + .name = "max7360-rotary", 184 184 + }, 185 185 + .probe = max7360_rotary_probe, 186 186 + .remove = max7360_rotary_remove, 187 187 + }; 188 188 + module_platform_driver(max7360_rotary_driver); 189 189 + 190 190 + MODULE_DESCRIPTION("MAX7360 Rotary driver"); 191 191 + MODULE_AUTHOR("Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>"); 192 192 + MODULE_LICENSE("GPL");

+34 -5

drivers/mfd/Kconfig

reviewed

··· 1134 1134 This driver can also be built as a module. If so the module 1135 1135 will be called menf21bmc. 1136 1136 1137 1137 + config MFD_NCT6694 1138 1138 + tristate "Nuvoton NCT6694 support" 1139 1139 + select MFD_CORE 1140 1140 + depends on USB 1141 1141 + help 1142 1142 + This enables support for the Nuvoton USB device NCT6694, which shares 1143 1143 + peripherals. 1144 1144 + The Nuvoton NCT6694 is a peripheral expander with 16 GPIO chips, 1145 1145 + 6 I2C controllers, 2 CANfd controllers, 2 Watchdog timers, ADC, 1146 1146 + PWM, and RTC. 1147 1147 + This driver provides core APIs to access the NCT6694 hardware 1148 1148 + monitoring and control features. 1149 1149 + Additional drivers must be enabled to utilize the specific 1150 1150 + functionalities of the device. 1151 1151 + 1137 1152 config MFD_OCELOT 1138 1153 tristate "Microsemi Ocelot External Control Support" 1139 1154 depends on SPI_MASTER ··· 1554 1539 through a register map. 1555 1540 1556 1541 config MFD_STMPE 1557 1557 - bool "STMicroelectronics STMPE" 1558 1558 - depends on I2C=y || SPI_MASTER=y 1542 1542 + tristate "STMicroelectronics STMPE" 1543 1543 + depends on I2C || SPI_MASTER 1559 1544 depends on OF 1560 1545 select MFD_CORE 1561 1546 help ··· 1583 1568 depends on MFD_STMPE 1584 1569 1585 1570 config STMPE_I2C 1586 1586 - bool "STMicroelectronics STMPE I2C Interface" 1587 1587 - depends on I2C=y 1571 1571 + tristate "STMicroelectronics STMPE I2C Interface" 1572 1572 + depends on I2C 1588 1573 default y 1589 1574 help 1590 1575 This is used to enable I2C interface of STMPE 1591 1576 1592 1577 config STMPE_SPI 1593 1593 - bool "STMicroelectronics STMPE SPI Interface" 1578 1578 + tristate "STMicroelectronics STMPE SPI Interface" 1594 1579 depends on SPI_MASTER 1595 1580 help 1596 1581 This is used to enable SPI interface of STMPE ··· 2495 2480 2496 2481 To compile this driver as a module, choose M here: the module will be 2497 2482 called upboard-fpga. 2483 2483 + 2484 2484 + config MFD_MAX7360 2485 2485 + tristate "Maxim MAX7360 I2C IO Expander" 2486 2486 + depends on I2C 2487 2487 + select MFD_CORE 2488 2488 + select REGMAP_I2C 2489 2489 + select REGMAP_IRQ 2490 2490 + help 2491 2491 + Say yes here to add support for Maxim MAX7360 device, embedding 2492 2492 + keypad, rotary encoder, PWM and GPIO features. 2493 2493 + 2494 2494 + This driver provides common support for accessing the device; 2495 2495 + additional drivers must be enabled in order to use the functionality 2496 2496 + of the device. 2498 2497 2499 2498 endmenu 2500 2499 endif

+3

drivers/mfd/Makefile

reviewed

··· 121 121 obj-$(CONFIG_MFD_MC13XXX_SPI) += mc13xxx-spi.o 122 122 obj-$(CONFIG_MFD_MC13XXX_I2C) += mc13xxx-i2c.o 123 123 124 124 + obj-$(CONFIG_MFD_NCT6694) += nct6694.o 125 125 + 124 126 obj-$(CONFIG_MFD_CORE) += mfd-core.o 125 127 126 128 ocelot-soc-objs := ocelot-core.o ocelot-spi.o ··· 165 163 obj-$(CONFIG_MFD_DA9150) += da9150-core.o 166 164 167 165 obj-$(CONFIG_MFD_MAX14577) += max14577.o 166 166 + obj-$(CONFIG_MFD_MAX7360) += max7360.o 168 167 obj-$(CONFIG_MFD_MAX77541) += max77541.o 169 168 obj-$(CONFIG_MFD_MAX77620) += max77620.o 170 169 obj-$(CONFIG_MFD_MAX77650) += max77650.o

+171

drivers/mfd/max7360.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Maxim MAX7360 Core Driver 4 4 + * 5 5 + * Copyright 2025 Bootlin 6 6 + * 7 7 + * Authors: 8 8 + * Kamel Bouhara <kamel.bouhara@bootlin.com> 9 9 + * Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 10 10 + */ 11 11 + 12 12 + #include <linux/array_size.h> 13 13 + #include <linux/bits.h> 14 14 + #include <linux/delay.h> 15 15 + #include <linux/device/devres.h> 16 16 + #include <linux/dev_printk.h> 17 17 + #include <linux/err.h> 18 18 + #include <linux/i2c.h> 19 19 + #include <linux/interrupt.h> 20 20 + #include <linux/mfd/core.h> 21 21 + #include <linux/mfd/max7360.h> 22 22 + #include <linux/mod_devicetable.h> 23 23 + #include <linux/module.h> 24 24 + #include <linux/regmap.h> 25 25 + #include <linux/types.h> 26 26 + 27 27 + static const struct mfd_cell max7360_cells[] = { 28 28 + { .name = "max7360-pinctrl" }, 29 29 + { .name = "max7360-pwm" }, 30 30 + { .name = "max7360-keypad" }, 31 31 + { .name = "max7360-rotary" }, 32 32 + { 33 33 + .name = "max7360-gpo", 34 34 + .of_compatible = "maxim,max7360-gpo", 35 35 + }, 36 36 + { 37 37 + .name = "max7360-gpio", 38 38 + .of_compatible = "maxim,max7360-gpio", 39 39 + }, 40 40 + }; 41 41 + 42 42 + static const struct regmap_range max7360_volatile_ranges[] = { 43 43 + regmap_reg_range(MAX7360_REG_KEYFIFO, MAX7360_REG_KEYFIFO), 44 44 + regmap_reg_range(MAX7360_REG_I2C_TIMEOUT, MAX7360_REG_RTR_CNT), 45 45 + }; 46 46 + 47 47 + static const struct regmap_access_table max7360_volatile_table = { 48 48 + .yes_ranges = max7360_volatile_ranges, 49 49 + .n_yes_ranges = ARRAY_SIZE(max7360_volatile_ranges), 50 50 + }; 51 51 + 52 52 + static const struct regmap_config max7360_regmap_config = { 53 53 + .reg_bits = 8, 54 54 + .val_bits = 8, 55 55 + .max_register = MAX7360_REG_PWMCFG(MAX7360_PORT_PWM_COUNT - 1), 56 56 + .volatile_table = &max7360_volatile_table, 57 57 + .cache_type = REGCACHE_MAPLE, 58 58 + }; 59 59 + 60 60 + static int max7360_mask_irqs(struct regmap *regmap) 61 61 + { 62 62 + struct device *dev = regmap_get_device(regmap); 63 63 + unsigned int val; 64 64 + int ret; 65 65 + 66 66 + /* 67 67 + * GPIO/PWM interrupts are not masked on reset: as the MAX7360 "INTI" 68 68 + * interrupt line is shared between GPIOs and rotary encoder, this could 69 69 + * result in repeated spurious interrupts on the rotary encoder driver 70 70 + * if the GPIO driver is not loaded. Mask them now to avoid this 71 71 + * situation. 72 72 + */ 73 73 + for (unsigned int i = 0; i < MAX7360_PORT_PWM_COUNT; i++) { 74 74 + ret = regmap_write_bits(regmap, MAX7360_REG_PWMCFG(i), 75 75 + MAX7360_PORT_CFG_INTERRUPT_MASK, 76 76 + MAX7360_PORT_CFG_INTERRUPT_MASK); 77 77 + if (ret) 78 78 + return dev_err_probe(dev, ret, 79 79 + "Failed to write MAX7360 port configuration\n"); 80 80 + } 81 81 + 82 82 + /* Read GPIO in register, to ACK any pending IRQ. */ 83 83 + ret = regmap_read(regmap, MAX7360_REG_GPIOIN, &val); 84 84 + if (ret) 85 85 + return dev_err_probe(dev, ret, "Failed to read GPIO values\n"); 86 86 + 87 87 + return 0; 88 88 + } 89 89 + 90 90 + static int max7360_reset(struct regmap *regmap) 91 91 + { 92 92 + struct device *dev = regmap_get_device(regmap); 93 93 + int ret; 94 94 + 95 95 + ret = regmap_write(regmap, MAX7360_REG_GPIOCFG, MAX7360_GPIO_CFG_GPIO_RST); 96 96 + if (ret) { 97 97 + dev_err(dev, "Failed to reset GPIO configuration: %x\n", ret); 98 98 + return ret; 99 99 + } 100 100 + 101 101 + ret = regcache_drop_region(regmap, MAX7360_REG_GPIOCFG, MAX7360_REG_GPIO_LAST); 102 102 + if (ret) { 103 103 + dev_err(dev, "Failed to drop regmap cache: %x\n", ret); 104 104 + return ret; 105 105 + } 106 106 + 107 107 + ret = regmap_write(regmap, MAX7360_REG_SLEEP, 0); 108 108 + if (ret) { 109 109 + dev_err(dev, "Failed to reset autosleep configuration: %x\n", ret); 110 110 + return ret; 111 111 + } 112 112 + 113 113 + ret = regmap_write(regmap, MAX7360_REG_DEBOUNCE, 0); 114 114 + if (ret) 115 115 + dev_err(dev, "Failed to reset GPO port count: %x\n", ret); 116 116 + 117 117 + return ret; 118 118 + } 119 119 + 120 120 + static int max7360_probe(struct i2c_client *client) 121 121 + { 122 122 + struct device *dev = &client->dev; 123 123 + struct regmap *regmap; 124 124 + int ret; 125 125 + 126 126 + regmap = devm_regmap_init_i2c(client, &max7360_regmap_config); 127 127 + if (IS_ERR(regmap)) 128 128 + return dev_err_probe(dev, PTR_ERR(regmap), "Failed to initialise regmap\n"); 129 129 + 130 130 + ret = max7360_reset(regmap); 131 131 + if (ret) 132 132 + return dev_err_probe(dev, ret, "Failed to reset device\n"); 133 133 + 134 134 + /* Get the device out of shutdown mode. */ 135 135 + ret = regmap_write_bits(regmap, MAX7360_REG_GPIOCFG, 136 136 + MAX7360_GPIO_CFG_GPIO_EN, 137 137 + MAX7360_GPIO_CFG_GPIO_EN); 138 138 + if (ret) 139 139 + return dev_err_probe(dev, ret, "Failed to enable GPIO and PWM module\n"); 140 140 + 141 141 + ret = max7360_mask_irqs(regmap); 142 142 + if (ret) 143 143 + return dev_err_probe(dev, ret, "Could not mask interrupts\n"); 144 144 + 145 145 + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, 146 146 + max7360_cells, ARRAY_SIZE(max7360_cells), 147 147 + NULL, 0, NULL); 148 148 + if (ret) 149 149 + return dev_err_probe(dev, ret, "Failed to register child devices\n"); 150 150 + 151 151 + return 0; 152 152 + } 153 153 + 154 154 + static const struct of_device_id max7360_dt_match[] = { 155 155 + { .compatible = "maxim,max7360" }, 156 156 + {} 157 157 + }; 158 158 + MODULE_DEVICE_TABLE(of, max7360_dt_match); 159 159 + 160 160 + static struct i2c_driver max7360_driver = { 161 161 + .driver = { 162 162 + .name = "max7360", 163 163 + .of_match_table = max7360_dt_match, 164 164 + }, 165 165 + .probe = max7360_probe, 166 166 + }; 167 167 + module_i2c_driver(max7360_driver); 168 168 + 169 169 + MODULE_DESCRIPTION("Maxim MAX7360 I2C IO Expander core driver"); 170 170 + MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>"); 171 171 + MODULE_LICENSE("GPL");

+388

drivers/mfd/nct6694.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2025 Nuvoton Technology Corp. 4 4 + * 5 5 + * Nuvoton NCT6694 core driver using USB interface to provide 6 6 + * access to the NCT6694 hardware monitoring and control features. 7 7 + * 8 8 + * The NCT6694 is an integrated controller that provides GPIO, I2C, 9 9 + * CAN, WDT, HWMON and RTC management. 10 10 + */ 11 11 + 12 12 + #include <linux/bits.h> 13 13 + #include <linux/interrupt.h> 14 14 + #include <linux/idr.h> 15 15 + #include <linux/irq.h> 16 16 + #include <linux/irqdomain.h> 17 17 + #include <linux/kernel.h> 18 18 + #include <linux/mfd/core.h> 19 19 + #include <linux/mfd/nct6694.h> 20 20 + #include <linux/module.h> 21 21 + #include <linux/slab.h> 22 22 + #include <linux/spinlock.h> 23 23 + #include <linux/usb.h> 24 24 + 25 25 + static const struct mfd_cell nct6694_devs[] = { 26 26 + MFD_CELL_NAME("nct6694-gpio"), 27 27 + MFD_CELL_NAME("nct6694-gpio"), 28 28 + MFD_CELL_NAME("nct6694-gpio"), 29 29 + MFD_CELL_NAME("nct6694-gpio"), 30 30 + MFD_CELL_NAME("nct6694-gpio"), 31 31 + MFD_CELL_NAME("nct6694-gpio"), 32 32 + MFD_CELL_NAME("nct6694-gpio"), 33 33 + MFD_CELL_NAME("nct6694-gpio"), 34 34 + MFD_CELL_NAME("nct6694-gpio"), 35 35 + MFD_CELL_NAME("nct6694-gpio"), 36 36 + MFD_CELL_NAME("nct6694-gpio"), 37 37 + MFD_CELL_NAME("nct6694-gpio"), 38 38 + MFD_CELL_NAME("nct6694-gpio"), 39 39 + MFD_CELL_NAME("nct6694-gpio"), 40 40 + MFD_CELL_NAME("nct6694-gpio"), 41 41 + MFD_CELL_NAME("nct6694-gpio"), 42 42 + 43 43 + MFD_CELL_NAME("nct6694-i2c"), 44 44 + MFD_CELL_NAME("nct6694-i2c"), 45 45 + MFD_CELL_NAME("nct6694-i2c"), 46 46 + MFD_CELL_NAME("nct6694-i2c"), 47 47 + MFD_CELL_NAME("nct6694-i2c"), 48 48 + MFD_CELL_NAME("nct6694-i2c"), 49 49 + 50 50 + MFD_CELL_NAME("nct6694-canfd"), 51 51 + MFD_CELL_NAME("nct6694-canfd"), 52 52 + 53 53 + MFD_CELL_NAME("nct6694-wdt"), 54 54 + MFD_CELL_NAME("nct6694-wdt"), 55 55 + 56 56 + MFD_CELL_NAME("nct6694-hwmon"), 57 57 + 58 58 + MFD_CELL_NAME("nct6694-rtc"), 59 59 + }; 60 60 + 61 61 + static int nct6694_response_err_handling(struct nct6694 *nct6694, unsigned char err_status) 62 62 + { 63 63 + switch (err_status) { 64 64 + case NCT6694_NO_ERROR: 65 65 + return 0; 66 66 + case NCT6694_NOT_SUPPORT_ERROR: 67 67 + dev_err(nct6694->dev, "Command is not supported!\n"); 68 68 + break; 69 69 + case NCT6694_NO_RESPONSE_ERROR: 70 70 + dev_warn(nct6694->dev, "Command received no response!\n"); 71 71 + break; 72 72 + case NCT6694_TIMEOUT_ERROR: 73 73 + dev_warn(nct6694->dev, "Command timed out!\n"); 74 74 + break; 75 75 + case NCT6694_PENDING: 76 76 + dev_err(nct6694->dev, "Command is pending!\n"); 77 77 + break; 78 78 + default: 79 79 + return -EINVAL; 80 80 + } 81 81 + 82 82 + return -EIO; 83 83 + } 84 84 + 85 85 + /** 86 86 + * nct6694_read_msg() - Read message from NCT6694 device 87 87 + * @nct6694: NCT6694 device pointer 88 88 + * @cmd_hd: command header structure 89 89 + * @buf: buffer to store the response data 90 90 + * 91 91 + * Sends a command to the NCT6694 device and reads the response. 92 92 + * The command header is specified in @cmd_hd, and the response 93 93 + * data is stored in @buf. 94 94 + * 95 95 + * Return: Negative value on error or 0 on success. 96 96 + */ 97 97 + int nct6694_read_msg(struct nct6694 *nct6694, const struct nct6694_cmd_header *cmd_hd, void *buf) 98 98 + { 99 99 + union nct6694_usb_msg *msg = nct6694->usb_msg; 100 100 + struct usb_device *udev = nct6694->udev; 101 101 + int tx_len, rx_len, ret; 102 102 + 103 103 + guard(mutex)(&nct6694->access_lock); 104 104 + 105 105 + memcpy(&msg->cmd_header, cmd_hd, sizeof(*cmd_hd)); 106 106 + msg->cmd_header.hctrl = NCT6694_HCTRL_GET; 107 107 + 108 108 + /* Send command packet to USB device */ 109 109 + ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, NCT6694_BULK_OUT_EP), &msg->cmd_header, 110 110 + sizeof(*msg), &tx_len, NCT6694_URB_TIMEOUT); 111 111 + if (ret) 112 112 + return ret; 113 113 + 114 114 + /* Receive response packet from USB device */ 115 115 + ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, NCT6694_BULK_IN_EP), &msg->response_header, 116 116 + sizeof(*msg), &rx_len, NCT6694_URB_TIMEOUT); 117 117 + if (ret) 118 118 + return ret; 119 119 + 120 120 + /* Receive data packet from USB device */ 121 121 + ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, NCT6694_BULK_IN_EP), buf, 122 122 + le16_to_cpu(cmd_hd->len), &rx_len, NCT6694_URB_TIMEOUT); 123 123 + if (ret) 124 124 + return ret; 125 125 + 126 126 + if (rx_len != le16_to_cpu(cmd_hd->len)) { 127 127 + dev_err(nct6694->dev, "Expected received length %d, but got %d\n", 128 128 + le16_to_cpu(cmd_hd->len), rx_len); 129 129 + return -EIO; 130 130 + } 131 131 + 132 132 + return nct6694_response_err_handling(nct6694, msg->response_header.sts); 133 133 + } 134 134 + EXPORT_SYMBOL_GPL(nct6694_read_msg); 135 135 + 136 136 + /** 137 137 + * nct6694_write_msg() - Write message to NCT6694 device 138 138 + * @nct6694: NCT6694 device pointer 139 139 + * @cmd_hd: command header structure 140 140 + * @buf: buffer containing the data to be sent 141 141 + * 142 142 + * Sends a command to the NCT6694 device and writes the data 143 143 + * from @buf. The command header is specified in @cmd_hd. 144 144 + * 145 145 + * Return: Negative value on error or 0 on success. 146 146 + */ 147 147 + int nct6694_write_msg(struct nct6694 *nct6694, const struct nct6694_cmd_header *cmd_hd, void *buf) 148 148 + { 149 149 + union nct6694_usb_msg *msg = nct6694->usb_msg; 150 150 + struct usb_device *udev = nct6694->udev; 151 151 + int tx_len, rx_len, ret; 152 152 + 153 153 + guard(mutex)(&nct6694->access_lock); 154 154 + 155 155 + memcpy(&msg->cmd_header, cmd_hd, sizeof(*cmd_hd)); 156 156 + msg->cmd_header.hctrl = NCT6694_HCTRL_SET; 157 157 + 158 158 + /* Send command packet to USB device */ 159 159 + ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, NCT6694_BULK_OUT_EP), &msg->cmd_header, 160 160 + sizeof(*msg), &tx_len, NCT6694_URB_TIMEOUT); 161 161 + if (ret) 162 162 + return ret; 163 163 + 164 164 + /* Send data packet to USB device */ 165 165 + ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, NCT6694_BULK_OUT_EP), buf, 166 166 + le16_to_cpu(cmd_hd->len), &tx_len, NCT6694_URB_TIMEOUT); 167 167 + if (ret) 168 168 + return ret; 169 169 + 170 170 + /* Receive response packet from USB device */ 171 171 + ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, NCT6694_BULK_IN_EP), &msg->response_header, 172 172 + sizeof(*msg), &rx_len, NCT6694_URB_TIMEOUT); 173 173 + if (ret) 174 174 + return ret; 175 175 + 176 176 + /* Receive data packet from USB device */ 177 177 + ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, NCT6694_BULK_IN_EP), buf, 178 178 + le16_to_cpu(cmd_hd->len), &rx_len, NCT6694_URB_TIMEOUT); 179 179 + if (ret) 180 180 + return ret; 181 181 + 182 182 + if (rx_len != le16_to_cpu(cmd_hd->len)) { 183 183 + dev_err(nct6694->dev, "Expected transmitted length %d, but got %d\n", 184 184 + le16_to_cpu(cmd_hd->len), rx_len); 185 185 + return -EIO; 186 186 + } 187 187 + 188 188 + return nct6694_response_err_handling(nct6694, msg->response_header.sts); 189 189 + } 190 190 + EXPORT_SYMBOL_GPL(nct6694_write_msg); 191 191 + 192 192 + static void usb_int_callback(struct urb *urb) 193 193 + { 194 194 + struct nct6694 *nct6694 = urb->context; 195 195 + __le32 *status_le = urb->transfer_buffer; 196 196 + u32 int_status; 197 197 + int ret; 198 198 + 199 199 + switch (urb->status) { 200 200 + case 0: 201 201 + break; 202 202 + case -ECONNRESET: 203 203 + case -ENOENT: 204 204 + case -ESHUTDOWN: 205 205 + return; 206 206 + default: 207 207 + goto resubmit; 208 208 + } 209 209 + 210 210 + int_status = le32_to_cpu(*status_le); 211 211 + 212 212 + while (int_status) { 213 213 + int irq = __ffs(int_status); 214 214 + 215 215 + generic_handle_irq_safe(irq_find_mapping(nct6694->domain, irq)); 216 216 + int_status &= ~BIT(irq); 217 217 + } 218 218 + 219 219 + resubmit: 220 220 + ret = usb_submit_urb(urb, GFP_ATOMIC); 221 221 + if (ret) 222 222 + dev_warn(nct6694->dev, "Failed to resubmit urb, status %pe", ERR_PTR(ret)); 223 223 + } 224 224 + 225 225 + static void nct6694_irq_enable(struct irq_data *data) 226 226 + { 227 227 + struct nct6694 *nct6694 = irq_data_get_irq_chip_data(data); 228 228 + irq_hw_number_t hwirq = irqd_to_hwirq(data); 229 229 + 230 230 + guard(spinlock_irqsave)(&nct6694->irq_lock); 231 231 + 232 232 + nct6694->irq_enable |= BIT(hwirq); 233 233 + } 234 234 + 235 235 + static void nct6694_irq_disable(struct irq_data *data) 236 236 + { 237 237 + struct nct6694 *nct6694 = irq_data_get_irq_chip_data(data); 238 238 + irq_hw_number_t hwirq = irqd_to_hwirq(data); 239 239 + 240 240 + guard(spinlock_irqsave)(&nct6694->irq_lock); 241 241 + 242 242 + nct6694->irq_enable &= ~BIT(hwirq); 243 243 + } 244 244 + 245 245 + static const struct irq_chip nct6694_irq_chip = { 246 246 + .name = "nct6694-irq", 247 247 + .flags = IRQCHIP_SKIP_SET_WAKE, 248 248 + .irq_enable = nct6694_irq_enable, 249 249 + .irq_disable = nct6694_irq_disable, 250 250 + }; 251 251 + 252 252 + static int nct6694_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 253 253 + { 254 254 + struct nct6694 *nct6694 = d->host_data; 255 255 + 256 256 + irq_set_chip_data(irq, nct6694); 257 257 + irq_set_chip_and_handler(irq, &nct6694_irq_chip, handle_simple_irq); 258 258 + 259 259 + return 0; 260 260 + } 261 261 + 262 262 + static void nct6694_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 263 263 + { 264 264 + irq_set_chip_and_handler(irq, NULL, NULL); 265 265 + irq_set_chip_data(irq, NULL); 266 266 + } 267 267 + 268 268 + static const struct irq_domain_ops nct6694_irq_domain_ops = { 269 269 + .map = nct6694_irq_domain_map, 270 270 + .unmap = nct6694_irq_domain_unmap, 271 271 + }; 272 272 + 273 273 + static int nct6694_usb_probe(struct usb_interface *iface, 274 274 + const struct usb_device_id *id) 275 275 + { 276 276 + struct usb_device *udev = interface_to_usbdev(iface); 277 277 + struct usb_endpoint_descriptor *int_endpoint; 278 278 + struct usb_host_interface *interface; 279 279 + struct device *dev = &iface->dev; 280 280 + struct nct6694 *nct6694; 281 281 + int ret; 282 282 + 283 283 + nct6694 = devm_kzalloc(dev, sizeof(*nct6694), GFP_KERNEL); 284 284 + if (!nct6694) 285 285 + return -ENOMEM; 286 286 + 287 287 + nct6694->usb_msg = devm_kzalloc(dev, sizeof(union nct6694_usb_msg), GFP_KERNEL); 288 288 + if (!nct6694->usb_msg) 289 289 + return -ENOMEM; 290 290 + 291 291 + nct6694->int_buffer = devm_kzalloc(dev, sizeof(*nct6694->int_buffer), GFP_KERNEL); 292 292 + if (!nct6694->int_buffer) 293 293 + return -ENOMEM; 294 294 + 295 295 + nct6694->int_in_urb = usb_alloc_urb(0, GFP_KERNEL); 296 296 + if (!nct6694->int_in_urb) 297 297 + return -ENOMEM; 298 298 + 299 299 + nct6694->domain = irq_domain_create_simple(NULL, NCT6694_NR_IRQS, 0, 300 300 + &nct6694_irq_domain_ops, 301 301 + nct6694); 302 302 + if (!nct6694->domain) { 303 303 + ret = -ENODEV; 304 304 + goto err_urb; 305 305 + } 306 306 + 307 307 + nct6694->dev = dev; 308 308 + nct6694->udev = udev; 309 309 + 310 310 + ida_init(&nct6694->gpio_ida); 311 311 + ida_init(&nct6694->i2c_ida); 312 312 + ida_init(&nct6694->canfd_ida); 313 313 + ida_init(&nct6694->wdt_ida); 314 314 + 315 315 + spin_lock_init(&nct6694->irq_lock); 316 316 + 317 317 + ret = devm_mutex_init(dev, &nct6694->access_lock); 318 318 + if (ret) 319 319 + goto err_ida; 320 320 + 321 321 + interface = iface->cur_altsetting; 322 322 + 323 323 + int_endpoint = &interface->endpoint[0].desc; 324 324 + if (!usb_endpoint_is_int_in(int_endpoint)) { 325 325 + ret = -ENODEV; 326 326 + goto err_ida; 327 327 + } 328 328 + 329 329 + usb_fill_int_urb(nct6694->int_in_urb, udev, usb_rcvintpipe(udev, NCT6694_INT_IN_EP), 330 330 + nct6694->int_buffer, sizeof(*nct6694->int_buffer), usb_int_callback, 331 331 + nct6694, int_endpoint->bInterval); 332 332 + 333 333 + ret = usb_submit_urb(nct6694->int_in_urb, GFP_KERNEL); 334 334 + if (ret) 335 335 + goto err_ida; 336 336 + 337 337 + usb_set_intfdata(iface, nct6694); 338 338 + 339 339 + ret = mfd_add_hotplug_devices(dev, nct6694_devs, ARRAY_SIZE(nct6694_devs)); 340 340 + if (ret) 341 341 + goto err_mfd; 342 342 + 343 343 + return 0; 344 344 + 345 345 + err_mfd: 346 346 + usb_kill_urb(nct6694->int_in_urb); 347 347 + err_ida: 348 348 + ida_destroy(&nct6694->wdt_ida); 349 349 + ida_destroy(&nct6694->canfd_ida); 350 350 + ida_destroy(&nct6694->i2c_ida); 351 351 + ida_destroy(&nct6694->gpio_ida); 352 352 + irq_domain_remove(nct6694->domain); 353 353 + err_urb: 354 354 + usb_free_urb(nct6694->int_in_urb); 355 355 + return ret; 356 356 + } 357 357 + 358 358 + static void nct6694_usb_disconnect(struct usb_interface *iface) 359 359 + { 360 360 + struct nct6694 *nct6694 = usb_get_intfdata(iface); 361 361 + 362 362 + mfd_remove_devices(nct6694->dev); 363 363 + usb_kill_urb(nct6694->int_in_urb); 364 364 + ida_destroy(&nct6694->wdt_ida); 365 365 + ida_destroy(&nct6694->canfd_ida); 366 366 + ida_destroy(&nct6694->i2c_ida); 367 367 + ida_destroy(&nct6694->gpio_ida); 368 368 + irq_domain_remove(nct6694->domain); 369 369 + usb_free_urb(nct6694->int_in_urb); 370 370 + } 371 371 + 372 372 + static const struct usb_device_id nct6694_ids[] = { 373 373 + { USB_DEVICE_AND_INTERFACE_INFO(NCT6694_VENDOR_ID, NCT6694_PRODUCT_ID, 0xFF, 0x00, 0x00) }, 374 374 + { } 375 375 + }; 376 376 + MODULE_DEVICE_TABLE(usb, nct6694_ids); 377 377 + 378 378 + static struct usb_driver nct6694_usb_driver = { 379 379 + .name = "nct6694", 380 380 + .id_table = nct6694_ids, 381 381 + .probe = nct6694_usb_probe, 382 382 + .disconnect = nct6694_usb_disconnect, 383 383 + }; 384 384 + module_usb_driver(nct6694_usb_driver); 385 385 + 386 386 + MODULE_DESCRIPTION("Nuvoton NCT6694 core driver"); 387 387 + MODULE_AUTHOR("Ming Yu <tmyu0@nuvoton.com>"); 388 388 + MODULE_LICENSE("GPL");

+1

drivers/mfd/stmpe-i2c.c

reviewed

··· 137 137 138 138 MODULE_DESCRIPTION("STMPE MFD I2C Interface Driver"); 139 139 MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); 140 140 + MODULE_LICENSE("GPL v2");

+1

drivers/mfd/stmpe-spi.c

reviewed

··· 156 156 157 157 MODULE_DESCRIPTION("STMPE MFD SPI Interface Driver"); 158 158 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); 159 159 + MODULE_LICENSE("GPL v2");

+6

drivers/mfd/stmpe.c

reviewed

··· 1482 1482 1483 1483 return ret; 1484 1484 } 1485 1485 + EXPORT_SYMBOL_GPL(stmpe_probe); 1485 1486 1486 1487 void stmpe_remove(struct stmpe *stmpe) 1487 1488 { ··· 1495 1494 1496 1495 mfd_remove_devices(stmpe->dev); 1497 1496 } 1497 1497 + EXPORT_SYMBOL_GPL(stmpe_remove); 1498 1498 1499 1499 static int stmpe_suspend(struct device *dev) 1500 1500 { ··· 1519 1517 1520 1518 EXPORT_GPL_SIMPLE_DEV_PM_OPS(stmpe_dev_pm_ops, 1521 1519 stmpe_suspend, stmpe_resume); 1520 1520 + 1521 1521 + MODULE_DESCRIPTION("STMPE Core driver"); 1522 1522 + MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); 1523 1523 + MODULE_LICENSE("GPL");

+20 -5

drivers/mfd/vexpress-sysreg.c

reviewed

··· 5 5 */ 6 6 7 7 #include <linux/gpio/driver.h> 8 8 + #include <linux/gpio/generic.h> 8 9 #include <linux/err.h> 9 10 #include <linux/io.h> 10 11 #include <linux/mfd/core.h> ··· 97 96 98 97 static int vexpress_sysreg_probe(struct platform_device *pdev) 99 98 { 99 99 + struct gpio_generic_chip *mmc_gpio_chip; 100 100 + struct gpio_generic_chip_config config; 100 101 struct resource *mem; 101 102 void __iomem *base; 102 102 - struct gpio_chip *mmc_gpio_chip; 103 103 + int ret; 103 104 104 105 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 105 106 if (!mem) ··· 119 116 GFP_KERNEL); 120 117 if (!mmc_gpio_chip) 121 118 return -ENOMEM; 122 122 - bgpio_init(mmc_gpio_chip, &pdev->dev, 0x4, base + SYS_MCI, 123 123 - NULL, NULL, NULL, NULL, 0); 124 124 - mmc_gpio_chip->ngpio = 2; 125 125 - devm_gpiochip_add_data(&pdev->dev, mmc_gpio_chip, NULL); 119 119 + 120 120 + config = (typeof(config)){ 121 121 + .dev = &pdev->dev, 122 122 + .sz = 4, 123 123 + .dat = base + SYS_MCI, 124 124 + }; 125 125 + 126 126 + ret = gpio_generic_chip_init(mmc_gpio_chip, &config); 127 127 + if (ret) 128 128 + return ret; 129 129 + 130 130 + mmc_gpio_chip->gc.ngpio = 2; 131 131 + 132 132 + ret = devm_gpiochip_add_data(&pdev->dev, &mmc_gpio_chip->gc, NULL); 133 133 + if (ret) 134 134 + return ret; 126 135 127 136 return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, 128 137 vexpress_sysreg_cells,

+11

drivers/net/can/usb/Kconfig

reviewed

··· 134 134 This driver supports the CAN BUS Analyzer interface 135 135 from Microchip (http://www.microchip.com/development-tools/). 136 136 137 137 + config CAN_NCT6694 138 138 + tristate "Nuvoton NCT6694 Socket CANfd support" 139 139 + depends on MFD_NCT6694 140 140 + select CAN_RX_OFFLOAD 141 141 + help 142 142 + If you say yes to this option, support will be included for Nuvoton 143 143 + NCT6694, a USB device to socket CANfd controller. 144 144 + 145 145 + This driver can also be built as a module. If so, the module will 146 146 + be called nct6694_canfd. 147 147 + 137 148 config CAN_PEAK_USB 138 149 tristate "PEAK PCAN-USB/USB Pro interfaces for CAN 2.0b/CAN-FD" 139 150 help

+1

drivers/net/can/usb/Makefile

reviewed

··· 11 11 obj-$(CONFIG_CAN_GS_USB) += gs_usb.o 12 12 obj-$(CONFIG_CAN_KVASER_USB) += kvaser_usb/ 13 13 obj-$(CONFIG_CAN_MCBA_USB) += mcba_usb.o 14 14 + obj-$(CONFIG_CAN_NCT6694) += nct6694_canfd.o 14 15 obj-$(CONFIG_CAN_PEAK_USB) += peak_usb/ 15 16 obj-$(CONFIG_CAN_UCAN) += ucan.o

+832

drivers/net/can/usb/nct6694_canfd.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* Nuvoton NCT6694 Socket CANfd driver based on USB interface. 3 3 + * 4 4 + * Copyright (C) 2025 Nuvoton Technology Corp. 5 5 + */ 6 6 + 7 7 + #include <linux/bitfield.h> 8 8 + #include <linux/can/dev.h> 9 9 + #include <linux/can/rx-offload.h> 10 10 + #include <linux/ethtool.h> 11 11 + #include <linux/idr.h> 12 12 + #include <linux/irqdomain.h> 13 13 + #include <linux/kernel.h> 14 14 + #include <linux/mfd/nct6694.h> 15 15 + #include <linux/module.h> 16 16 + #include <linux/netdevice.h> 17 17 + #include <linux/platform_device.h> 18 18 + 19 19 + #define DEVICE_NAME "nct6694-canfd" 20 20 + 21 21 + /* USB command module type for NCT6694 CANfd controller. 22 22 + * This defines the module type used for communication with the NCT6694 23 23 + * CANfd controller over the USB interface. 24 24 + */ 25 25 + #define NCT6694_CANFD_MOD 0x05 26 26 + 27 27 + /* Command 00h - CAN Setting and Initialization */ 28 28 + #define NCT6694_CANFD_SETTING 0x00 29 29 + #define NCT6694_CANFD_SETTING_ACTIVE_CTRL1 BIT(0) 30 30 + #define NCT6694_CANFD_SETTING_ACTIVE_CTRL2 BIT(1) 31 31 + #define NCT6694_CANFD_SETTING_ACTIVE_NBTP_DBTP BIT(2) 32 32 + #define NCT6694_CANFD_SETTING_CTRL1_MON BIT(0) 33 33 + #define NCT6694_CANFD_SETTING_CTRL1_NISO BIT(1) 34 34 + #define NCT6694_CANFD_SETTING_CTRL1_LBCK BIT(2) 35 35 + #define NCT6694_CANFD_SETTING_NBTP_NTSEG2 GENMASK(6, 0) 36 36 + #define NCT6694_CANFD_SETTING_NBTP_NTSEG1 GENMASK(15, 8) 37 37 + #define NCT6694_CANFD_SETTING_NBTP_NBRP GENMASK(24, 16) 38 38 + #define NCT6694_CANFD_SETTING_NBTP_NSJW GENMASK(31, 25) 39 39 + #define NCT6694_CANFD_SETTING_DBTP_DSJW GENMASK(3, 0) 40 40 + #define NCT6694_CANFD_SETTING_DBTP_DTSEG2 GENMASK(7, 4) 41 41 + #define NCT6694_CANFD_SETTING_DBTP_DTSEG1 GENMASK(12, 8) 42 42 + #define NCT6694_CANFD_SETTING_DBTP_DBRP GENMASK(20, 16) 43 43 + #define NCT6694_CANFD_SETTING_DBTP_TDC BIT(23) 44 44 + 45 45 + /* Command 01h - CAN Information */ 46 46 + #define NCT6694_CANFD_INFORMATION 0x01 47 47 + #define NCT6694_CANFD_INFORMATION_SEL 0x00 48 48 + 49 49 + /* Command 02h - CAN Event */ 50 50 + #define NCT6694_CANFD_EVENT 0x02 51 51 + #define NCT6694_CANFD_EVENT_SEL(idx, mask) \ 52 52 + ((idx ? 0x80 : 0x00) | ((mask) & 0x7F)) 53 53 + 54 54 + #define NCT6694_CANFD_EVENT_MASK GENMASK(5, 0) 55 55 + #define NCT6694_CANFD_EVT_TX_FIFO_EMPTY BIT(7) /* Read-clear */ 56 56 + #define NCT6694_CANFD_EVT_RX_DATA_LOST BIT(5) /* Read-clear */ 57 57 + #define NCT6694_CANFD_EVT_RX_DATA_IN BIT(7) /* Read-clear */ 58 58 + 59 59 + /* Command 10h - CAN Deliver */ 60 60 + #define NCT6694_CANFD_DELIVER 0x10 61 61 + #define NCT6694_CANFD_DELIVER_SEL(buf_cnt) \ 62 62 + ((buf_cnt) & 0xFF) 63 63 + 64 64 + /* Command 11h - CAN Receive */ 65 65 + #define NCT6694_CANFD_RECEIVE 0x11 66 66 + #define NCT6694_CANFD_RECEIVE_SEL(idx, buf_cnt) \ 67 67 + ((idx ? 0x80 : 0x00) | ((buf_cnt) & 0x7F)) 68 68 + 69 69 + #define NCT6694_CANFD_FRAME_TAG(idx) (0xC0 | (idx)) 70 70 + #define NCT6694_CANFD_FRAME_FLAG_EFF BIT(0) 71 71 + #define NCT6694_CANFD_FRAME_FLAG_RTR BIT(1) 72 72 + #define NCT6694_CANFD_FRAME_FLAG_FD BIT(2) 73 73 + #define NCT6694_CANFD_FRAME_FLAG_BRS BIT(3) 74 74 + #define NCT6694_CANFD_FRAME_FLAG_ERR BIT(4) 75 75 + 76 76 + #define NCT6694_NAPI_WEIGHT 32 77 77 + 78 78 + enum nct6694_event_err { 79 79 + NCT6694_CANFD_EVT_ERR_NO_ERROR = 0, 80 80 + NCT6694_CANFD_EVT_ERR_CRC_ERROR, 81 81 + NCT6694_CANFD_EVT_ERR_STUFF_ERROR, 82 82 + NCT6694_CANFD_EVT_ERR_ACK_ERROR, 83 83 + NCT6694_CANFD_EVT_ERR_FORM_ERROR, 84 84 + NCT6694_CANFD_EVT_ERR_BIT_ERROR, 85 85 + NCT6694_CANFD_EVT_ERR_TIMEOUT_ERROR, 86 86 + NCT6694_CANFD_EVT_ERR_UNKNOWN_ERROR, 87 87 + }; 88 88 + 89 89 + enum nct6694_event_status { 90 90 + NCT6694_CANFD_EVT_STS_ERROR_ACTIVE = 0, 91 91 + NCT6694_CANFD_EVT_STS_ERROR_PASSIVE, 92 92 + NCT6694_CANFD_EVT_STS_BUS_OFF, 93 93 + NCT6694_CANFD_EVT_STS_WARNING, 94 94 + }; 95 95 + 96 96 + struct __packed nct6694_canfd_setting { 97 97 + __le32 nbr; 98 98 + __le32 dbr; 99 99 + u8 active; 100 100 + u8 reserved[3]; 101 101 + __le16 ctrl1; 102 102 + __le16 ctrl2; 103 103 + __le32 nbtp; 104 104 + __le32 dbtp; 105 105 + }; 106 106 + 107 107 + struct __packed nct6694_canfd_information { 108 108 + u8 tx_fifo_cnt; 109 109 + u8 rx_fifo_cnt; 110 110 + u8 reserved[2]; 111 111 + __le32 can_clk; 112 112 + }; 113 113 + 114 114 + struct __packed nct6694_canfd_event { 115 115 + u8 err; 116 116 + u8 status; 117 117 + u8 tx_evt; 118 118 + u8 rx_evt; 119 119 + u8 rec; 120 120 + u8 tec; 121 121 + u8 reserved[2]; 122 122 + }; 123 123 + 124 124 + struct __packed nct6694_canfd_frame { 125 125 + u8 tag; 126 126 + u8 flag; 127 127 + u8 reserved; 128 128 + u8 length; 129 129 + __le32 id; 130 130 + u8 data[CANFD_MAX_DLEN]; 131 131 + }; 132 132 + 133 133 + struct nct6694_canfd_priv { 134 134 + struct can_priv can; /* must be the first member */ 135 135 + struct can_rx_offload offload; 136 136 + struct net_device *ndev; 137 137 + struct nct6694 *nct6694; 138 138 + struct workqueue_struct *wq; 139 139 + struct work_struct tx_work; 140 140 + struct nct6694_canfd_frame tx; 141 141 + struct nct6694_canfd_frame rx; 142 142 + struct nct6694_canfd_event event[2]; 143 143 + struct can_berr_counter bec; 144 144 + }; 145 145 + 146 146 + static inline struct nct6694_canfd_priv *rx_offload_to_priv(struct can_rx_offload *offload) 147 147 + { 148 148 + return container_of(offload, struct nct6694_canfd_priv, offload); 149 149 + } 150 150 + 151 151 + static const struct can_bittiming_const nct6694_canfd_bittiming_nominal_const = { 152 152 + .name = DEVICE_NAME, 153 153 + .tseg1_min = 1, 154 154 + .tseg1_max = 256, 155 155 + .tseg2_min = 1, 156 156 + .tseg2_max = 128, 157 157 + .sjw_max = 128, 158 158 + .brp_min = 1, 159 159 + .brp_max = 512, 160 160 + .brp_inc = 1, 161 161 + }; 162 162 + 163 163 + static const struct can_bittiming_const nct6694_canfd_bittiming_data_const = { 164 164 + .name = DEVICE_NAME, 165 165 + .tseg1_min = 1, 166 166 + .tseg1_max = 32, 167 167 + .tseg2_min = 1, 168 168 + .tseg2_max = 16, 169 169 + .sjw_max = 16, 170 170 + .brp_min = 1, 171 171 + .brp_max = 32, 172 172 + .brp_inc = 1, 173 173 + }; 174 174 + 175 175 + static void nct6694_canfd_rx_offload(struct can_rx_offload *offload, 176 176 + struct sk_buff *skb) 177 177 + { 178 178 + struct nct6694_canfd_priv *priv = rx_offload_to_priv(offload); 179 179 + int ret; 180 180 + 181 181 + ret = can_rx_offload_queue_tail(offload, skb); 182 182 + if (ret) 183 183 + priv->ndev->stats.rx_fifo_errors++; 184 184 + } 185 185 + 186 186 + static void nct6694_canfd_handle_lost_msg(struct net_device *ndev) 187 187 + { 188 188 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 189 189 + struct net_device_stats *stats = &ndev->stats; 190 190 + struct can_frame *cf; 191 191 + struct sk_buff *skb; 192 192 + 193 193 + netdev_dbg(ndev, "RX FIFO overflow, message(s) lost.\n"); 194 194 + 195 195 + stats->rx_errors++; 196 196 + stats->rx_over_errors++; 197 197 + 198 198 + skb = alloc_can_err_skb(ndev, &cf); 199 199 + if (!skb) 200 200 + return; 201 201 + 202 202 + cf->can_id |= CAN_ERR_CRTL; 203 203 + cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 204 204 + 205 205 + nct6694_canfd_rx_offload(&priv->offload, skb); 206 206 + } 207 207 + 208 208 + static void nct6694_canfd_handle_rx(struct net_device *ndev, u8 rx_evt) 209 209 + { 210 210 + struct net_device_stats *stats = &ndev->stats; 211 211 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 212 212 + struct nct6694_canfd_frame *frame = &priv->rx; 213 213 + const struct nct6694_cmd_header cmd_hd = { 214 214 + .mod = NCT6694_CANFD_MOD, 215 215 + .cmd = NCT6694_CANFD_RECEIVE, 216 216 + .sel = NCT6694_CANFD_RECEIVE_SEL(ndev->dev_port, 1), 217 217 + .len = cpu_to_le16(sizeof(*frame)) 218 218 + }; 219 219 + struct sk_buff *skb; 220 220 + int ret; 221 221 + 222 222 + ret = nct6694_read_msg(priv->nct6694, &cmd_hd, frame); 223 223 + if (ret) 224 224 + return; 225 225 + 226 226 + if (frame->flag & NCT6694_CANFD_FRAME_FLAG_FD) { 227 227 + struct canfd_frame *cfd; 228 228 + 229 229 + skb = alloc_canfd_skb(priv->ndev, &cfd); 230 230 + if (!skb) { 231 231 + stats->rx_dropped++; 232 232 + return; 233 233 + } 234 234 + 235 235 + cfd->can_id = le32_to_cpu(frame->id); 236 236 + cfd->len = canfd_sanitize_len(frame->length); 237 237 + if (frame->flag & NCT6694_CANFD_FRAME_FLAG_EFF) 238 238 + cfd->can_id |= CAN_EFF_FLAG; 239 239 + if (frame->flag & NCT6694_CANFD_FRAME_FLAG_BRS) 240 240 + cfd->flags |= CANFD_BRS; 241 241 + if (frame->flag & NCT6694_CANFD_FRAME_FLAG_ERR) 242 242 + cfd->flags |= CANFD_ESI; 243 243 + 244 244 + memcpy(cfd->data, frame->data, cfd->len); 245 245 + } else { 246 246 + struct can_frame *cf; 247 247 + 248 248 + skb = alloc_can_skb(priv->ndev, &cf); 249 249 + if (!skb) { 250 250 + stats->rx_dropped++; 251 251 + return; 252 252 + } 253 253 + 254 254 + cf->can_id = le32_to_cpu(frame->id); 255 255 + cf->len = can_cc_dlc2len(frame->length); 256 256 + if (frame->flag & NCT6694_CANFD_FRAME_FLAG_EFF) 257 257 + cf->can_id |= CAN_EFF_FLAG; 258 258 + 259 259 + if (frame->flag & NCT6694_CANFD_FRAME_FLAG_RTR) 260 260 + cf->can_id |= CAN_RTR_FLAG; 261 261 + else 262 262 + memcpy(cf->data, frame->data, cf->len); 263 263 + } 264 264 + 265 265 + nct6694_canfd_rx_offload(&priv->offload, skb); 266 266 + } 267 267 + 268 268 + static int nct6694_canfd_get_berr_counter(const struct net_device *ndev, 269 269 + struct can_berr_counter *bec) 270 270 + { 271 271 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 272 272 + 273 273 + *bec = priv->bec; 274 274 + 275 275 + return 0; 276 276 + } 277 277 + 278 278 + static void nct6694_canfd_handle_state_change(struct net_device *ndev, u8 status) 279 279 + { 280 280 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 281 281 + enum can_state new_state, rx_state, tx_state; 282 282 + struct can_berr_counter bec; 283 283 + struct can_frame *cf; 284 284 + struct sk_buff *skb; 285 285 + 286 286 + nct6694_canfd_get_berr_counter(ndev, &bec); 287 287 + can_state_get_by_berr_counter(ndev, &bec, &tx_state, &rx_state); 288 288 + 289 289 + new_state = max(tx_state, rx_state); 290 290 + 291 291 + /* state hasn't changed */ 292 292 + if (new_state == priv->can.state) 293 293 + return; 294 294 + 295 295 + skb = alloc_can_err_skb(ndev, &cf); 296 296 + 297 297 + can_change_state(ndev, cf, tx_state, rx_state); 298 298 + 299 299 + if (new_state == CAN_STATE_BUS_OFF) { 300 300 + can_bus_off(ndev); 301 301 + } else if (cf) { 302 302 + cf->can_id |= CAN_ERR_CNT; 303 303 + cf->data[6] = bec.txerr; 304 304 + cf->data[7] = bec.rxerr; 305 305 + } 306 306 + 307 307 + if (skb) 308 308 + nct6694_canfd_rx_offload(&priv->offload, skb); 309 309 + } 310 310 + 311 311 + static void nct6694_canfd_handle_bus_err(struct net_device *ndev, u8 bus_err) 312 312 + { 313 313 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 314 314 + struct can_frame *cf; 315 315 + struct sk_buff *skb; 316 316 + 317 317 + priv->can.can_stats.bus_error++; 318 318 + 319 319 + skb = alloc_can_err_skb(ndev, &cf); 320 320 + if (cf) 321 321 + cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 322 322 + 323 323 + switch (bus_err) { 324 324 + case NCT6694_CANFD_EVT_ERR_CRC_ERROR: 325 325 + netdev_dbg(ndev, "CRC error\n"); 326 326 + ndev->stats.rx_errors++; 327 327 + if (cf) 328 328 + cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 329 329 + break; 330 330 + 331 331 + case NCT6694_CANFD_EVT_ERR_STUFF_ERROR: 332 332 + netdev_dbg(ndev, "Stuff error\n"); 333 333 + ndev->stats.rx_errors++; 334 334 + if (cf) 335 335 + cf->data[2] |= CAN_ERR_PROT_STUFF; 336 336 + break; 337 337 + 338 338 + case NCT6694_CANFD_EVT_ERR_ACK_ERROR: 339 339 + netdev_dbg(ndev, "Ack error\n"); 340 340 + ndev->stats.tx_errors++; 341 341 + if (cf) { 342 342 + cf->can_id |= CAN_ERR_ACK; 343 343 + cf->data[2] |= CAN_ERR_PROT_TX; 344 344 + } 345 345 + break; 346 346 + 347 347 + case NCT6694_CANFD_EVT_ERR_FORM_ERROR: 348 348 + netdev_dbg(ndev, "Form error\n"); 349 349 + ndev->stats.rx_errors++; 350 350 + if (cf) 351 351 + cf->data[2] |= CAN_ERR_PROT_FORM; 352 352 + break; 353 353 + 354 354 + case NCT6694_CANFD_EVT_ERR_BIT_ERROR: 355 355 + netdev_dbg(ndev, "Bit error\n"); 356 356 + ndev->stats.tx_errors++; 357 357 + if (cf) 358 358 + cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT; 359 359 + break; 360 360 + 361 361 + default: 362 362 + break; 363 363 + } 364 364 + 365 365 + if (skb) 366 366 + nct6694_canfd_rx_offload(&priv->offload, skb); 367 367 + } 368 368 + 369 369 + static void nct6694_canfd_handle_tx(struct net_device *ndev) 370 370 + { 371 371 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 372 372 + struct net_device_stats *stats = &ndev->stats; 373 373 + 374 374 + stats->tx_bytes += can_rx_offload_get_echo_skb_queue_tail(&priv->offload, 375 375 + 0, NULL); 376 376 + stats->tx_packets++; 377 377 + netif_wake_queue(ndev); 378 378 + } 379 379 + 380 380 + static irqreturn_t nct6694_canfd_irq(int irq, void *data) 381 381 + { 382 382 + struct net_device *ndev = data; 383 383 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 384 384 + struct nct6694_canfd_event *event = &priv->event[ndev->dev_port]; 385 385 + const struct nct6694_cmd_header cmd_hd = { 386 386 + .mod = NCT6694_CANFD_MOD, 387 387 + .cmd = NCT6694_CANFD_EVENT, 388 388 + .sel = NCT6694_CANFD_EVENT_SEL(ndev->dev_port, NCT6694_CANFD_EVENT_MASK), 389 389 + .len = cpu_to_le16(sizeof(priv->event)) 390 390 + }; 391 391 + irqreturn_t handled = IRQ_NONE; 392 392 + int ret; 393 393 + 394 394 + ret = nct6694_read_msg(priv->nct6694, &cmd_hd, priv->event); 395 395 + if (ret < 0) 396 396 + return handled; 397 397 + 398 398 + if (event->rx_evt & NCT6694_CANFD_EVT_RX_DATA_IN) { 399 399 + nct6694_canfd_handle_rx(ndev, event->rx_evt); 400 400 + handled = IRQ_HANDLED; 401 401 + } 402 402 + 403 403 + if (event->rx_evt & NCT6694_CANFD_EVT_RX_DATA_LOST) { 404 404 + nct6694_canfd_handle_lost_msg(ndev); 405 405 + handled = IRQ_HANDLED; 406 406 + } 407 407 + 408 408 + if (event->status) { 409 409 + nct6694_canfd_handle_state_change(ndev, event->status); 410 410 + handled = IRQ_HANDLED; 411 411 + } 412 412 + 413 413 + if (event->err != NCT6694_CANFD_EVT_ERR_NO_ERROR) { 414 414 + if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 415 415 + nct6694_canfd_handle_bus_err(ndev, event->err); 416 416 + handled = IRQ_HANDLED; 417 417 + } 418 418 + 419 419 + if (event->tx_evt & NCT6694_CANFD_EVT_TX_FIFO_EMPTY) { 420 420 + nct6694_canfd_handle_tx(ndev); 421 421 + handled = IRQ_HANDLED; 422 422 + } 423 423 + 424 424 + if (handled) 425 425 + can_rx_offload_threaded_irq_finish(&priv->offload); 426 426 + 427 427 + priv->bec.rxerr = event->rec; 428 428 + priv->bec.txerr = event->tec; 429 429 + 430 430 + return handled; 431 431 + } 432 432 + 433 433 + static void nct6694_canfd_tx_work(struct work_struct *work) 434 434 + { 435 435 + struct nct6694_canfd_priv *priv = container_of(work, 436 436 + struct nct6694_canfd_priv, 437 437 + tx_work); 438 438 + struct nct6694_canfd_frame *frame = &priv->tx; 439 439 + struct net_device *ndev = priv->ndev; 440 440 + struct net_device_stats *stats = &ndev->stats; 441 441 + struct sk_buff *skb = priv->can.echo_skb[0]; 442 442 + static const struct nct6694_cmd_header cmd_hd = { 443 443 + .mod = NCT6694_CANFD_MOD, 444 444 + .cmd = NCT6694_CANFD_DELIVER, 445 445 + .sel = NCT6694_CANFD_DELIVER_SEL(1), 446 446 + .len = cpu_to_le16(sizeof(*frame)) 447 447 + }; 448 448 + u32 txid; 449 449 + int err; 450 450 + 451 451 + memset(frame, 0, sizeof(*frame)); 452 452 + 453 453 + frame->tag = NCT6694_CANFD_FRAME_TAG(ndev->dev_port); 454 454 + 455 455 + if (can_is_canfd_skb(skb)) { 456 456 + struct canfd_frame *cfd = (struct canfd_frame *)skb->data; 457 457 + 458 458 + if (cfd->flags & CANFD_BRS) 459 459 + frame->flag |= NCT6694_CANFD_FRAME_FLAG_BRS; 460 460 + 461 461 + if (cfd->can_id & CAN_EFF_FLAG) { 462 462 + txid = cfd->can_id & CAN_EFF_MASK; 463 463 + frame->flag |= NCT6694_CANFD_FRAME_FLAG_EFF; 464 464 + } else { 465 465 + txid = cfd->can_id & CAN_SFF_MASK; 466 466 + } 467 467 + frame->flag |= NCT6694_CANFD_FRAME_FLAG_FD; 468 468 + frame->id = cpu_to_le32(txid); 469 469 + frame->length = canfd_sanitize_len(cfd->len); 470 470 + 471 471 + memcpy(frame->data, cfd->data, frame->length); 472 472 + } else { 473 473 + struct can_frame *cf = (struct can_frame *)skb->data; 474 474 + 475 475 + if (cf->can_id & CAN_EFF_FLAG) { 476 476 + txid = cf->can_id & CAN_EFF_MASK; 477 477 + frame->flag |= NCT6694_CANFD_FRAME_FLAG_EFF; 478 478 + } else { 479 479 + txid = cf->can_id & CAN_SFF_MASK; 480 480 + } 481 481 + 482 482 + if (cf->can_id & CAN_RTR_FLAG) 483 483 + frame->flag |= NCT6694_CANFD_FRAME_FLAG_RTR; 484 484 + else 485 485 + memcpy(frame->data, cf->data, cf->len); 486 486 + 487 487 + frame->id = cpu_to_le32(txid); 488 488 + frame->length = cf->len; 489 489 + } 490 490 + 491 491 + err = nct6694_write_msg(priv->nct6694, &cmd_hd, frame); 492 492 + if (err) { 493 493 + can_free_echo_skb(ndev, 0, NULL); 494 494 + stats->tx_dropped++; 495 495 + stats->tx_errors++; 496 496 + netif_wake_queue(ndev); 497 497 + } 498 498 + } 499 499 + 500 500 + static netdev_tx_t nct6694_canfd_start_xmit(struct sk_buff *skb, 501 501 + struct net_device *ndev) 502 502 + { 503 503 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 504 504 + 505 505 + if (can_dev_dropped_skb(ndev, skb)) 506 506 + return NETDEV_TX_OK; 507 507 + 508 508 + netif_stop_queue(ndev); 509 509 + can_put_echo_skb(skb, ndev, 0, 0); 510 510 + queue_work(priv->wq, &priv->tx_work); 511 511 + 512 512 + return NETDEV_TX_OK; 513 513 + } 514 514 + 515 515 + static int nct6694_canfd_start(struct net_device *ndev) 516 516 + { 517 517 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 518 518 + const struct can_bittiming *n_bt = &priv->can.bittiming; 519 519 + const struct can_bittiming *d_bt = &priv->can.fd.data_bittiming; 520 520 + struct nct6694_canfd_setting *setting __free(kfree) = NULL; 521 521 + const struct nct6694_cmd_header cmd_hd = { 522 522 + .mod = NCT6694_CANFD_MOD, 523 523 + .cmd = NCT6694_CANFD_SETTING, 524 524 + .sel = ndev->dev_port, 525 525 + .len = cpu_to_le16(sizeof(*setting)) 526 526 + }; 527 527 + u32 en_tdc; 528 528 + int ret; 529 529 + 530 530 + setting = kzalloc(sizeof(*setting), GFP_KERNEL); 531 531 + if (!setting) 532 532 + return -ENOMEM; 533 533 + 534 534 + if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 535 535 + setting->ctrl1 |= cpu_to_le16(NCT6694_CANFD_SETTING_CTRL1_MON); 536 536 + 537 537 + if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 538 538 + setting->ctrl1 |= cpu_to_le16(NCT6694_CANFD_SETTING_CTRL1_NISO); 539 539 + 540 540 + if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 541 541 + setting->ctrl1 |= cpu_to_le16(NCT6694_CANFD_SETTING_CTRL1_LBCK); 542 542 + 543 543 + /* Disable clock divider */ 544 544 + setting->ctrl2 = 0; 545 545 + 546 546 + setting->nbtp = cpu_to_le32(FIELD_PREP(NCT6694_CANFD_SETTING_NBTP_NSJW, 547 547 + n_bt->sjw - 1) | 548 548 + FIELD_PREP(NCT6694_CANFD_SETTING_NBTP_NBRP, 549 549 + n_bt->brp - 1) | 550 550 + FIELD_PREP(NCT6694_CANFD_SETTING_NBTP_NTSEG2, 551 551 + n_bt->phase_seg2 - 1) | 552 552 + FIELD_PREP(NCT6694_CANFD_SETTING_NBTP_NTSEG1, 553 553 + n_bt->prop_seg + n_bt->phase_seg1 - 1)); 554 554 + 555 555 + if (d_bt->brp <= 2) 556 556 + en_tdc = NCT6694_CANFD_SETTING_DBTP_TDC; 557 557 + else 558 558 + en_tdc = 0; 559 559 + 560 560 + setting->dbtp = cpu_to_le32(FIELD_PREP(NCT6694_CANFD_SETTING_DBTP_DSJW, 561 561 + d_bt->sjw - 1) | 562 562 + FIELD_PREP(NCT6694_CANFD_SETTING_DBTP_DBRP, 563 563 + d_bt->brp - 1) | 564 564 + FIELD_PREP(NCT6694_CANFD_SETTING_DBTP_DTSEG2, 565 565 + d_bt->phase_seg2 - 1) | 566 566 + FIELD_PREP(NCT6694_CANFD_SETTING_DBTP_DTSEG1, 567 567 + d_bt->prop_seg + d_bt->phase_seg1 - 1) | 568 568 + en_tdc); 569 569 + 570 570 + setting->active = NCT6694_CANFD_SETTING_ACTIVE_CTRL1 | 571 571 + NCT6694_CANFD_SETTING_ACTIVE_CTRL2 | 572 572 + NCT6694_CANFD_SETTING_ACTIVE_NBTP_DBTP; 573 573 + 574 574 + ret = nct6694_write_msg(priv->nct6694, &cmd_hd, setting); 575 575 + if (ret) 576 576 + return ret; 577 577 + 578 578 + priv->can.state = CAN_STATE_ERROR_ACTIVE; 579 579 + 580 580 + return 0; 581 581 + } 582 582 + 583 583 + static void nct6694_canfd_stop(struct net_device *ndev) 584 584 + { 585 585 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 586 586 + struct nct6694_canfd_setting *setting __free(kfree) = NULL; 587 587 + const struct nct6694_cmd_header cmd_hd = { 588 588 + .mod = NCT6694_CANFD_MOD, 589 589 + .cmd = NCT6694_CANFD_SETTING, 590 590 + .sel = ndev->dev_port, 591 591 + .len = cpu_to_le16(sizeof(*setting)) 592 592 + }; 593 593 + 594 594 + /* The NCT6694 cannot be stopped. To ensure safe operation and avoid 595 595 + * interference, the control mode is set to Listen-Only mode. This 596 596 + * mode allows the device to monitor bus activity without actively 597 597 + * participating in communication. 598 598 + */ 599 599 + setting = kzalloc(sizeof(*setting), GFP_KERNEL); 600 600 + if (!setting) 601 601 + return; 602 602 + 603 603 + nct6694_read_msg(priv->nct6694, &cmd_hd, setting); 604 604 + setting->ctrl1 = cpu_to_le16(NCT6694_CANFD_SETTING_CTRL1_MON); 605 605 + setting->active = NCT6694_CANFD_SETTING_ACTIVE_CTRL1; 606 606 + nct6694_write_msg(priv->nct6694, &cmd_hd, setting); 607 607 + 608 608 + priv->can.state = CAN_STATE_STOPPED; 609 609 + } 610 610 + 611 611 + static int nct6694_canfd_close(struct net_device *ndev) 612 612 + { 613 613 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 614 614 + 615 615 + netif_stop_queue(ndev); 616 616 + nct6694_canfd_stop(ndev); 617 617 + destroy_workqueue(priv->wq); 618 618 + free_irq(ndev->irq, ndev); 619 619 + can_rx_offload_disable(&priv->offload); 620 620 + close_candev(ndev); 621 621 + return 0; 622 622 + } 623 623 + 624 624 + static int nct6694_canfd_set_mode(struct net_device *ndev, enum can_mode mode) 625 625 + { 626 626 + int ret; 627 627 + 628 628 + switch (mode) { 629 629 + case CAN_MODE_START: 630 630 + ret = nct6694_canfd_start(ndev); 631 631 + if (ret) 632 632 + return ret; 633 633 + 634 634 + netif_wake_queue(ndev); 635 635 + break; 636 636 + 637 637 + default: 638 638 + return -EOPNOTSUPP; 639 639 + } 640 640 + 641 641 + return ret; 642 642 + } 643 643 + 644 644 + static int nct6694_canfd_open(struct net_device *ndev) 645 645 + { 646 646 + struct nct6694_canfd_priv *priv = netdev_priv(ndev); 647 647 + int ret; 648 648 + 649 649 + ret = open_candev(ndev); 650 650 + if (ret) 651 651 + return ret; 652 652 + 653 653 + can_rx_offload_enable(&priv->offload); 654 654 + 655 655 + ret = request_threaded_irq(ndev->irq, NULL, 656 656 + nct6694_canfd_irq, IRQF_ONESHOT, 657 657 + "nct6694_canfd", ndev); 658 658 + if (ret) { 659 659 + netdev_err(ndev, "Failed to request IRQ\n"); 660 660 + goto can_rx_offload_disable; 661 661 + } 662 662 + 663 663 + priv->wq = alloc_ordered_workqueue("%s-nct6694_wq", 664 664 + WQ_FREEZABLE | WQ_MEM_RECLAIM, 665 665 + ndev->name); 666 666 + if (!priv->wq) { 667 667 + ret = -ENOMEM; 668 668 + goto free_irq; 669 669 + } 670 670 + 671 671 + ret = nct6694_canfd_start(ndev); 672 672 + if (ret) 673 673 + goto destroy_wq; 674 674 + 675 675 + netif_start_queue(ndev); 676 676 + 677 677 + return 0; 678 678 + 679 679 + destroy_wq: 680 680 + destroy_workqueue(priv->wq); 681 681 + free_irq: 682 682 + free_irq(ndev->irq, ndev); 683 683 + can_rx_offload_disable: 684 684 + can_rx_offload_disable(&priv->offload); 685 685 + close_candev(ndev); 686 686 + return ret; 687 687 + } 688 688 + 689 689 + static const struct net_device_ops nct6694_canfd_netdev_ops = { 690 690 + .ndo_open = nct6694_canfd_open, 691 691 + .ndo_stop = nct6694_canfd_close, 692 692 + .ndo_start_xmit = nct6694_canfd_start_xmit, 693 693 + .ndo_change_mtu = can_change_mtu, 694 694 + }; 695 695 + 696 696 + static const struct ethtool_ops nct6694_canfd_ethtool_ops = { 697 697 + .get_ts_info = ethtool_op_get_ts_info, 698 698 + }; 699 699 + 700 700 + static int nct6694_canfd_get_clock(struct nct6694_canfd_priv *priv) 701 701 + { 702 702 + struct nct6694_canfd_information *info __free(kfree) = NULL; 703 703 + static const struct nct6694_cmd_header cmd_hd = { 704 704 + .mod = NCT6694_CANFD_MOD, 705 705 + .cmd = NCT6694_CANFD_INFORMATION, 706 706 + .sel = NCT6694_CANFD_INFORMATION_SEL, 707 707 + .len = cpu_to_le16(sizeof(*info)) 708 708 + }; 709 709 + int ret; 710 710 + 711 711 + info = kzalloc(sizeof(*info), GFP_KERNEL); 712 712 + if (!info) 713 713 + return -ENOMEM; 714 714 + 715 715 + ret = nct6694_read_msg(priv->nct6694, &cmd_hd, info); 716 716 + if (ret) 717 717 + return ret; 718 718 + 719 719 + return le32_to_cpu(info->can_clk); 720 720 + } 721 721 + 722 722 + static int nct6694_canfd_probe(struct platform_device *pdev) 723 723 + { 724 724 + struct nct6694 *nct6694 = dev_get_drvdata(pdev->dev.parent); 725 725 + struct nct6694_canfd_priv *priv; 726 726 + struct net_device *ndev; 727 727 + int port, irq, ret, can_clk; 728 728 + 729 729 + port = ida_alloc(&nct6694->canfd_ida, GFP_KERNEL); 730 730 + if (port < 0) 731 731 + return port; 732 732 + 733 733 + irq = irq_create_mapping(nct6694->domain, 734 734 + NCT6694_IRQ_CAN0 + port); 735 735 + if (!irq) { 736 736 + ret = -EINVAL; 737 737 + goto free_ida; 738 738 + } 739 739 + 740 740 + ndev = alloc_candev(sizeof(struct nct6694_canfd_priv), 1); 741 741 + if (!ndev) { 742 742 + ret = -ENOMEM; 743 743 + goto dispose_irq; 744 744 + } 745 745 + 746 746 + ndev->irq = irq; 747 747 + ndev->flags |= IFF_ECHO; 748 748 + ndev->dev_port = port; 749 749 + ndev->netdev_ops = &nct6694_canfd_netdev_ops; 750 750 + ndev->ethtool_ops = &nct6694_canfd_ethtool_ops; 751 751 + 752 752 + priv = netdev_priv(ndev); 753 753 + priv->nct6694 = nct6694; 754 754 + priv->ndev = ndev; 755 755 + 756 756 + can_clk = nct6694_canfd_get_clock(priv); 757 757 + if (can_clk < 0) { 758 758 + ret = dev_err_probe(&pdev->dev, can_clk, 759 759 + "Failed to get clock\n"); 760 760 + goto free_candev; 761 761 + } 762 762 + 763 763 + INIT_WORK(&priv->tx_work, nct6694_canfd_tx_work); 764 764 + 765 765 + priv->can.clock.freq = can_clk; 766 766 + priv->can.bittiming_const = &nct6694_canfd_bittiming_nominal_const; 767 767 + priv->can.fd.data_bittiming_const = &nct6694_canfd_bittiming_data_const; 768 768 + priv->can.do_set_mode = nct6694_canfd_set_mode; 769 769 + priv->can.do_get_berr_counter = nct6694_canfd_get_berr_counter; 770 770 + priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 771 771 + CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING | 772 772 + CAN_CTRLMODE_FD_NON_ISO; 773 773 + 774 774 + ret = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD); 775 775 + if (ret) 776 776 + goto free_candev; 777 777 + 778 778 + ret = can_rx_offload_add_manual(ndev, &priv->offload, 779 779 + NCT6694_NAPI_WEIGHT); 780 780 + if (ret) { 781 781 + dev_err_probe(&pdev->dev, ret, "Failed to add rx_offload\n"); 782 782 + goto free_candev; 783 783 + } 784 784 + 785 785 + platform_set_drvdata(pdev, priv); 786 786 + SET_NETDEV_DEV(priv->ndev, &pdev->dev); 787 787 + 788 788 + ret = register_candev(priv->ndev); 789 789 + if (ret) 790 790 + goto rx_offload_del; 791 791 + 792 792 + return 0; 793 793 + 794 794 + rx_offload_del: 795 795 + can_rx_offload_del(&priv->offload); 796 796 + free_candev: 797 797 + free_candev(ndev); 798 798 + dispose_irq: 799 799 + irq_dispose_mapping(irq); 800 800 + free_ida: 801 801 + ida_free(&nct6694->canfd_ida, port); 802 802 + return ret; 803 803 + } 804 804 + 805 805 + static void nct6694_canfd_remove(struct platform_device *pdev) 806 806 + { 807 807 + struct nct6694_canfd_priv *priv = platform_get_drvdata(pdev); 808 808 + struct nct6694 *nct6694 = priv->nct6694; 809 809 + struct net_device *ndev = priv->ndev; 810 810 + int port = ndev->dev_port; 811 811 + int irq = ndev->irq; 812 812 + 813 813 + unregister_candev(ndev); 814 814 + can_rx_offload_del(&priv->offload); 815 815 + free_candev(ndev); 816 816 + irq_dispose_mapping(irq); 817 817 + ida_free(&nct6694->canfd_ida, port); 818 818 + } 819 819 + 820 820 + static struct platform_driver nct6694_canfd_driver = { 821 821 + .driver = { 822 822 + .name = DEVICE_NAME, 823 823 + }, 824 824 + .probe = nct6694_canfd_probe, 825 825 + .remove = nct6694_canfd_remove, 826 826 + }; 827 827 + 828 828 + module_platform_driver(nct6694_canfd_driver); 829 829 + 830 830 + MODULE_DESCRIPTION("USB-CAN FD driver for NCT6694"); 831 831 + MODULE_AUTHOR("Ming Yu <tmyu0@nuvoton.com>"); 832 832 + MODULE_LICENSE("GPL");

+11

drivers/pinctrl/Kconfig

reviewed

··· 358 358 help 359 359 Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU). 360 360 361 361 + config PINCTRL_MAX7360 362 362 + tristate "MAX7360 Pincontrol support" 363 363 + depends on MFD_MAX7360 364 364 + select PINMUX 365 365 + select GENERIC_PINCONF 366 366 + help 367 367 + Say Y here to enable pin control support for Maxim MAX7360 keypad 368 368 + controller. 369 369 + This keypad controller has 8 GPIO pins that may work as GPIO, or PWM, 370 370 + or rotary encoder alternate modes. 371 371 + 361 372 config PINCTRL_MAX77620 362 373 tristate "MAX77620/MAX20024 Pincontrol support" 363 374 depends on MFD_MAX77620 && OF

+1

drivers/pinctrl/Makefile

reviewed

··· 37 37 obj-$(CONFIG_PINCTRL_LOONGSON2) += pinctrl-loongson2.o 38 38 obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o 39 39 obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o 40 40 + obj-$(CONFIG_PINCTRL_MAX7360) += pinctrl-max7360.o 40 41 obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o 41 42 obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o 42 43 obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o

+1 -1

drivers/pinctrl/nomadik/pinctrl-nomadik.c

reviewed

··· 584 584 seq_printf(s, "invalid pin offset"); 585 585 return; 586 586 } 587 587 - nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 587 587 + nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base); 588 588 } 589 589 590 590 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,

+90 -91

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

reviewed

··· 4 4 5 5 #include <linux/device.h> 6 6 #include <linux/gpio/driver.h> 7 7 + #include <linux/gpio/generic.h> 7 8 #include <linux/interrupt.h> 8 9 #include <linux/irq.h> 9 10 #include <linux/mfd/syscon.h> ··· 78 77 /* Structure for register banks */ 79 78 struct npcm7xx_gpio { 80 79 void __iomem *base; 81 81 - struct gpio_chip gc; 80 80 + struct gpio_generic_chip chip; 82 81 int irqbase; 83 82 int irq; 84 83 u32 pinctrl_id; ··· 100 99 }; 101 100 102 101 /* GPIO handling in the pinctrl driver */ 103 103 - static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, 102 102 + static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg, 104 103 unsigned int pinmask) 105 104 { 106 106 - unsigned long flags; 107 105 unsigned long val; 108 106 109 109 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 107 107 + guard(gpio_generic_lock_irqsave)(chip); 110 108 111 109 val = ioread32(reg) | pinmask; 112 110 iowrite32(val, reg); 113 113 - 114 114 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 115 111 } 116 112 117 117 - static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, 113 113 + static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg, 118 114 unsigned int pinmask) 119 115 { 120 120 - unsigned long flags; 121 116 unsigned long val; 122 117 123 123 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 118 118 + guard(gpio_generic_lock_irqsave)(chip); 124 119 125 120 val = ioread32(reg) & ~pinmask; 126 121 iowrite32(val, reg); 127 127 - 128 128 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 129 122 } 130 123 131 124 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) ··· 127 132 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 128 133 129 134 seq_printf(s, "-- module %d [gpio%d - %d]\n", 130 130 - bank->gc.base / bank->gc.ngpio, 131 131 - bank->gc.base, 132 132 - bank->gc.base + bank->gc.ngpio); 135 135 + bank->chip.gc.base / bank->chip.gc.ngpio, 136 136 + bank->chip.gc.base, 137 137 + bank->chip.gc.base + bank->chip.gc.ngpio); 133 138 seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n", 134 139 ioread32(bank->base + NPCM7XX_GP_N_DIN), 135 140 ioread32(bank->base + NPCM7XX_GP_N_DOUT), ··· 215 220 chained_irq_enter(chip, desc); 216 221 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); 217 222 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); 218 218 - dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, 223 223 + dev_dbg(bank->chip.gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, 219 224 en); 220 225 221 226 sts &= en; ··· 230 235 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); 231 236 unsigned int gpio = BIT(irqd_to_hwirq(d)); 232 237 233 233 - dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio, 238 238 + dev_dbg(bank->chip.gc.parent, "setirqtype: %u.%u = %u\n", gpio, 234 239 d->irq, type); 235 240 switch (type) { 236 241 case IRQ_TYPE_EDGE_RISING: 237 237 - dev_dbg(bank->gc.parent, "edge.rising\n"); 238 238 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 239 239 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 242 242 + dev_dbg(bank->chip.gc.parent, "edge.rising\n"); 243 243 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 244 244 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 240 245 break; 241 246 case IRQ_TYPE_EDGE_FALLING: 242 242 - dev_dbg(bank->gc.parent, "edge.falling\n"); 243 243 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 244 244 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 247 247 + dev_dbg(bank->chip.gc.parent, "edge.falling\n"); 248 248 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 249 249 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 245 250 break; 246 251 case IRQ_TYPE_EDGE_BOTH: 247 247 - dev_dbg(bank->gc.parent, "edge.both\n"); 248 248 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 252 252 + dev_dbg(bank->chip.gc.parent, "edge.both\n"); 253 253 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 249 254 break; 250 255 case IRQ_TYPE_LEVEL_LOW: 251 251 - dev_dbg(bank->gc.parent, "level.low\n"); 252 252 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 256 256 + dev_dbg(bank->chip.gc.parent, "level.low\n"); 257 257 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 253 258 break; 254 259 case IRQ_TYPE_LEVEL_HIGH: 255 255 - dev_dbg(bank->gc.parent, "level.high\n"); 256 256 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 260 260 + dev_dbg(bank->chip.gc.parent, "level.high\n"); 261 261 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 257 262 break; 258 263 default: 259 259 - dev_dbg(bank->gc.parent, "invalid irq type\n"); 264 264 + dev_dbg(bank->chip.gc.parent, "invalid irq type\n"); 260 265 return -EINVAL; 261 266 } 262 267 263 268 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 264 264 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 269 269 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 265 270 irq_set_handler_locked(d, handle_level_irq); 266 271 } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING 267 272 | IRQ_TYPE_EDGE_FALLING)) { 268 268 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 273 273 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 269 274 irq_set_handler_locked(d, handle_edge_irq); 270 275 } 271 276 ··· 278 283 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); 279 284 unsigned int gpio = irqd_to_hwirq(d); 280 285 281 281 - dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); 286 286 + dev_dbg(bank->chip.gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); 282 287 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); 283 288 } 284 289 ··· 290 295 unsigned int gpio = irqd_to_hwirq(d); 291 296 292 297 /* Clear events */ 293 293 - dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); 298 298 + dev_dbg(bank->chip.gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); 294 299 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); 295 300 gpiochip_disable_irq(gc, gpio); 296 301 } ··· 304 309 305 310 /* Enable events */ 306 311 gpiochip_enable_irq(gc, gpio); 307 307 - dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); 312 312 + dev_dbg(bank->chip.gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); 308 313 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); 309 314 } 310 315 ··· 1418 1423 struct regmap *gcr_regmap, unsigned int pin) 1419 1424 { 1420 1425 u32 val; 1421 1421 - int gpio = (pin % bank->gc.ngpio); 1426 1426 + int gpio = (pin % bank->chip.gc.ngpio); 1422 1427 unsigned long pinmask = BIT(gpio); 1423 1428 1424 1429 if (pincfg[pin].flag & SLEW) ··· 1438 1443 struct regmap *gcr_regmap, unsigned int pin, 1439 1444 int arg) 1440 1445 { 1441 1441 - int gpio = BIT(pin % bank->gc.ngpio); 1446 1446 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1442 1447 1443 1448 if (pincfg[pin].flag & SLEW) { 1444 1449 switch (arg) { 1445 1450 case 0: 1446 1446 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, 1451 1451 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC, 1447 1452 gpio); 1448 1453 return 0; 1449 1454 case 1: 1450 1450 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, 1455 1455 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC, 1451 1456 gpio); 1452 1457 return 0; 1453 1458 default: ··· 1480 1485 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1481 1486 struct npcm7xx_gpio *bank = 1482 1487 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1483 1483 - int gpio = (pin % bank->gc.ngpio); 1488 1488 + int gpio = (pin % bank->chip.gc.ngpio); 1484 1489 unsigned long pinmask = BIT(gpio); 1485 1490 u32 ds = 0; 1486 1491 int flg, val; ··· 1491 1496 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) 1492 1497 & pinmask; 1493 1498 ds = val ? DSHI(flg) : DSLO(flg); 1494 1494 - dev_dbg(bank->gc.parent, 1499 1499 + dev_dbg(bank->chip.gc.parent, 1495 1500 "pin %d strength %d = %d\n", pin, val, ds); 1496 1501 return ds; 1497 1502 } ··· 1506 1511 int v; 1507 1512 struct npcm7xx_gpio *bank = 1508 1513 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1509 1509 - int gpio = BIT(pin % bank->gc.ngpio); 1514 1514 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1510 1515 1511 1516 v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK); 1512 1517 if (!nval || !v) 1513 1518 return -ENOTSUPP; 1514 1519 if (DSLO(v) == nval) { 1515 1515 - dev_dbg(bank->gc.parent, 1520 1520 + dev_dbg(bank->chip.gc.parent, 1516 1521 "setting pin %d to low strength [%d]\n", pin, nval); 1517 1517 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1522 1522 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1518 1523 return 0; 1519 1524 } else if (DSHI(v) == nval) { 1520 1520 - dev_dbg(bank->gc.parent, 1525 1525 + dev_dbg(bank->chip.gc.parent, 1521 1526 "setting pin %d to high strength [%d]\n", pin, nval); 1522 1522 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1527 1527 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1523 1528 return 0; 1524 1529 } 1525 1530 ··· 1652 1657 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1653 1658 struct npcm7xx_gpio *bank = 1654 1659 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK]; 1655 1655 - int gpio = BIT(offset % bank->gc.ngpio); 1660 1660 + int gpio = BIT(offset % bank->chip.gc.ngpio); 1656 1661 1657 1657 - dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset, 1662 1662 + dev_dbg(bank->chip.gc.parent, "GPIO Set Direction: %d = %d\n", offset, 1658 1663 input); 1659 1664 if (input) 1660 1665 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); ··· 1682 1687 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1683 1688 struct npcm7xx_gpio *bank = 1684 1689 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1685 1685 - int gpio = (pin % bank->gc.ngpio); 1690 1690 + int gpio = (pin % bank->chip.gc.ngpio); 1686 1691 unsigned long pinmask = BIT(gpio); 1687 1692 u32 ie, oe, pu, pd; 1688 1693 int rc = 0; ··· 1745 1750 u16 arg = pinconf_to_config_argument(config); 1746 1751 struct npcm7xx_gpio *bank = 1747 1752 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1748 1748 - int gpio = BIT(pin % bank->gc.ngpio); 1753 1753 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1749 1754 1750 1750 - dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin); 1755 1755 + dev_dbg(bank->chip.gc.parent, "param=%d %d[GPIO]\n", param, pin); 1751 1756 switch (param) { 1752 1757 case PIN_CONFIG_BIAS_DISABLE: 1753 1753 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1754 1754 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1758 1758 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1759 1759 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1755 1760 break; 1756 1761 case PIN_CONFIG_BIAS_PULL_DOWN: 1757 1757 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1758 1758 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1762 1762 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1763 1763 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1759 1764 break; 1760 1765 case PIN_CONFIG_BIAS_PULL_UP: 1761 1761 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1762 1762 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1766 1766 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1767 1767 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1763 1768 break; 1764 1769 case PIN_CONFIG_INPUT_ENABLE: 1765 1770 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); 1766 1766 - bank->direction_input(&bank->gc, pin % bank->gc.ngpio); 1771 1771 + bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio); 1767 1772 break; 1768 1773 case PIN_CONFIG_OUTPUT: 1769 1769 - bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); 1774 1774 + bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg); 1770 1775 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); 1771 1776 break; 1772 1777 case PIN_CONFIG_DRIVE_PUSH_PULL: 1773 1773 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1778 1778 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1774 1779 break; 1775 1780 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1776 1776 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1781 1781 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1777 1782 break; 1778 1783 case PIN_CONFIG_INPUT_DEBOUNCE: 1779 1779 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); 1784 1784 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_DBNC, gpio); 1780 1785 break; 1781 1786 case PIN_CONFIG_SLEW_RATE: 1782 1787 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); ··· 1824 1829 1825 1830 static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) 1826 1831 { 1832 1832 + struct gpio_generic_chip_config config; 1827 1833 int ret = -ENXIO; 1828 1834 struct device *dev = pctrl->dev; 1829 1835 struct fwnode_reference_args args; ··· 1836 1840 if (!pctrl->gpio_bank[id].base) 1837 1841 return -EINVAL; 1838 1842 1839 1839 - ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, 1840 1840 - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN, 1841 1841 - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT, 1842 1842 - NULL, 1843 1843 - NULL, 1844 1844 - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM, 1845 1845 - BGPIOF_READ_OUTPUT_REG_SET); 1843 1843 + config = (typeof(config)){ 1844 1844 + .dev = dev, 1845 1845 + .sz = 4, 1846 1846 + .dat = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN, 1847 1847 + .set = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT, 1848 1848 + .dirin = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM, 1849 1849 + .flags = GPIO_GENERIC_READ_OUTPUT_REG_SET, 1850 1850 + }; 1851 1851 + 1852 1852 + ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config); 1846 1853 if (ret) { 1847 1847 - dev_err(dev, "bgpio_init() failed\n"); 1854 1854 + dev_err(dev, "failed to initialize the generic GPIO chip\n"); 1848 1855 return ret; 1849 1856 } 1850 1857 ··· 1865 1866 pctrl->gpio_bank[id].irq = ret; 1866 1867 pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK; 1867 1868 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; 1868 1868 - pctrl->gpio_bank[id].gc.base = args.args[1]; 1869 1869 - pctrl->gpio_bank[id].gc.ngpio = args.args[2]; 1870 1870 - pctrl->gpio_bank[id].gc.owner = THIS_MODULE; 1871 1871 - pctrl->gpio_bank[id].gc.parent = dev; 1872 1872 - pctrl->gpio_bank[id].gc.fwnode = child; 1873 1873 - pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 1874 1874 - if (pctrl->gpio_bank[id].gc.label == NULL) 1869 1869 + pctrl->gpio_bank[id].chip.gc.base = args.args[1]; 1870 1870 + pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2]; 1871 1871 + pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE; 1872 1872 + pctrl->gpio_bank[id].chip.gc.parent = dev; 1873 1873 + pctrl->gpio_bank[id].chip.gc.fwnode = child; 1874 1874 + pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 1875 1875 + if (pctrl->gpio_bank[id].chip.gc.label == NULL) 1875 1876 return -ENOMEM; 1876 1877 1877 1877 - pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; 1878 1878 - pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; 1879 1879 - pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; 1880 1880 - pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; 1881 1881 - pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; 1882 1882 - pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; 1883 1883 - pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; 1884 1884 - pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free; 1878 1878 + pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show; 1879 1879 + pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input; 1880 1880 + pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input; 1881 1881 + pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output; 1882 1882 + pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output; 1883 1883 + pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request; 1884 1884 + pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request; 1885 1885 + pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free; 1885 1886 id++; 1886 1887 } 1887 1888 ··· 1896 1897 for (id = 0 ; id < pctrl->bank_num ; id++) { 1897 1898 struct gpio_irq_chip *girq; 1898 1899 1899 1899 - girq = &pctrl->gpio_bank[id].gc.irq; 1900 1900 + girq = &pctrl->gpio_bank[id].chip.gc.irq; 1900 1901 gpio_irq_chip_set_chip(girq, &npcmgpio_irqchip); 1901 1902 girq->parent_handler = npcmgpio_irq_handler; 1902 1903 girq->num_parents = 1; ··· 1911 1912 girq->default_type = IRQ_TYPE_NONE; 1912 1913 girq->handler = handle_level_irq; 1913 1914 ret = devm_gpiochip_add_data(pctrl->dev, 1914 1914 - &pctrl->gpio_bank[id].gc, 1915 1915 + &pctrl->gpio_bank[id].chip.gc, 1915 1916 &pctrl->gpio_bank[id]); 1916 1917 if (ret) { 1917 1918 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id); 1918 1919 goto err_register; 1919 1920 } 1920 1921 1921 1921 - ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc, 1922 1922 + ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].chip.gc, 1922 1923 dev_name(pctrl->dev), 1923 1924 pctrl->gpio_bank[id].pinctrl_id, 1924 1924 - pctrl->gpio_bank[id].gc.base, 1925 1925 - pctrl->gpio_bank[id].gc.ngpio); 1925 1925 + pctrl->gpio_bank[id].chip.gc.base, 1926 1926 + pctrl->gpio_bank[id].chip.gc.ngpio); 1926 1927 if (ret < 0) { 1927 1928 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id); 1928 1928 - gpiochip_remove(&pctrl->gpio_bank[id].gc); 1929 1929 + gpiochip_remove(&pctrl->gpio_bank[id].chip.gc); 1929 1930 goto err_register; 1930 1931 } 1931 1932 } ··· 1934 1935 1935 1936 err_register: 1936 1937 for (; id > 0; id--) 1937 1937 - gpiochip_remove(&pctrl->gpio_bank[id - 1].gc); 1938 1938 + gpiochip_remove(&pctrl->gpio_bank[id - 1].chip.gc); 1938 1939 1939 1940 return ret; 1940 1941 }

+78 -76

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

reviewed

··· 4 4 #include <linux/bits.h> 5 5 #include <linux/device.h> 6 6 #include <linux/gpio/driver.h> 7 7 + #include <linux/gpio/generic.h> 7 8 #include <linux/interrupt.h> 8 9 #include <linux/irq.h> 9 10 #include <linux/mfd/syscon.h> ··· 91 90 }; 92 91 93 92 struct npcm8xx_gpio { 94 94 - struct gpio_chip gc; 93 93 + struct gpio_generic_chip chip; 95 94 void __iomem *base; 96 95 struct debounce_time debounce; 97 96 int irqbase; ··· 116 115 }; 117 116 118 117 /* GPIO handling in the pinctrl driver */ 119 119 - static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, 118 118 + static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg, 120 119 unsigned int pinmask) 121 120 { 122 122 - unsigned long flags; 121 121 + guard(gpio_generic_lock_irqsave)(chip); 123 122 124 124 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 125 123 iowrite32(ioread32(reg) | pinmask, reg); 126 126 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 127 124 } 128 125 129 129 - static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, 126 126 + static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg, 130 127 unsigned int pinmask) 131 128 { 132 132 - unsigned long flags; 129 129 + guard(gpio_generic_lock_irqsave)(chip); 133 130 134 134 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 135 131 iowrite32(ioread32(reg) & ~pinmask, reg); 136 136 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 137 132 } 138 133 139 134 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) ··· 230 233 231 234 switch (type) { 232 235 case IRQ_TYPE_EDGE_RISING: 233 233 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 234 234 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 236 236 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); 237 237 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 235 238 break; 236 239 case IRQ_TYPE_EDGE_FALLING: 237 237 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 238 238 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 240 240 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); 241 241 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 239 242 break; 240 243 case IRQ_TYPE_EDGE_BOTH: 241 241 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 242 242 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 244 244 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 245 245 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); 243 246 break; 244 247 case IRQ_TYPE_LEVEL_LOW: 245 245 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 248 248 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 246 249 break; 247 250 case IRQ_TYPE_LEVEL_HIGH: 248 248 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 251 251 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 249 252 break; 250 253 default: 251 254 return -EINVAL; 252 255 } 253 256 254 257 if (type & IRQ_TYPE_LEVEL_MASK) { 255 255 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 258 258 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 256 259 irq_set_handler_locked(d, handle_level_irq); 257 260 } else if (type & IRQ_TYPE_EDGE_BOTH) { 258 258 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 261 261 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 259 262 irq_set_handler_locked(d, handle_edge_irq); 260 263 } 261 264 ··· 1839 1842 static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, 1840 1843 struct regmap *gcr_regmap, unsigned int pin) 1841 1844 { 1842 1842 - int gpio = pin % bank->gc.ngpio; 1845 1845 + int gpio = pin % bank->chip.gc.ngpio; 1843 1846 unsigned long pinmask = BIT(gpio); 1844 1847 u32 val; 1845 1848 ··· 1859 1862 int arg) 1860 1863 { 1861 1864 void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC; 1862 1862 - int gpio = BIT(pin % bank->gc.ngpio); 1865 1865 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1863 1866 1864 1867 if (pincfg[pin].flag & SLEW) { 1865 1868 switch (arg) { 1866 1869 case 0: 1867 1867 - npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio); 1870 1870 + npcm_gpio_clr(&bank->chip, OSRC_Offset, gpio); 1868 1871 return 0; 1869 1872 case 1: 1870 1870 - npcm_gpio_set(&bank->gc, OSRC_Offset, gpio); 1873 1873 + npcm_gpio_set(&bank->chip, OSRC_Offset, gpio); 1871 1874 return 0; 1872 1875 default: 1873 1876 return -EINVAL; ··· 1899 1902 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1900 1903 struct npcm8xx_gpio *bank = 1901 1904 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 1902 1902 - int gpio = pin % bank->gc.ngpio; 1905 1905 + int gpio = pin % bank->chip.gc.ngpio; 1903 1906 unsigned long pinmask = BIT(gpio); 1904 1907 int flg, val; 1905 1908 u32 ds = 0; ··· 1910 1913 1911 1914 val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask; 1912 1915 ds = val ? DSHI(flg) : DSLO(flg); 1913 1913 - dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds); 1916 1916 + dev_dbg(bank->chip.gc.parent, "pin %d strength %d = %d\n", pin, val, ds); 1914 1917 1915 1918 return ds; 1916 1919 } ··· 1920 1923 { 1921 1924 struct npcm8xx_gpio *bank = 1922 1925 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 1923 1923 - int gpio = BIT(pin % bank->gc.ngpio); 1926 1926 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1924 1927 int v; 1925 1928 1926 1929 v = pincfg[pin].flag & DRIVE_STRENGTH_MASK; 1927 1930 1928 1931 if (DSLO(v) == nval) 1929 1929 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1932 1932 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1930 1933 else if (DSHI(v) == nval) 1931 1931 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1934 1934 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1932 1935 else 1933 1936 return -ENOTSUPP; 1934 1937 ··· 2051 2054 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2052 2055 struct npcm8xx_gpio *bank = 2053 2056 &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK]; 2054 2054 - int gpio = BIT(offset % bank->gc.ngpio); 2057 2057 + int gpio = BIT(offset % bank->chip.gc.ngpio); 2055 2058 2056 2059 if (input) 2057 2060 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); ··· 2082 2085 if (bank->debounce.set_val[i]) { 2083 2086 if (bank->debounce.nanosec_val[i] == nanosecs) { 2084 2087 debounce_select = i << gpio_debounce; 2085 2085 - npcm_gpio_set(&bank->gc, DBNCS_offset, 2088 2088 + npcm_gpio_set(&bank->chip, DBNCS_offset, 2086 2089 debounce_select); 2087 2090 break; 2088 2091 } ··· 2090 2093 bank->debounce.set_val[i] = true; 2091 2094 bank->debounce.nanosec_val[i] = nanosecs; 2092 2095 debounce_select = i << gpio_debounce; 2093 2093 - npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select); 2096 2096 + npcm_gpio_set(&bank->chip, DBNCS_offset, debounce_select); 2094 2097 switch (nanosecs) { 2095 2098 case 1 ... 1040: 2096 2099 iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); ··· 2142 2145 { 2143 2146 struct npcm8xx_gpio *bank = 2144 2147 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2145 2145 - int gpio = BIT(pin % bank->gc.ngpio); 2148 2148 + int gpio = BIT(pin % bank->chip.gc.ngpio); 2146 2149 int ret; 2147 2150 2148 2151 if (nanosecs) { 2149 2149 - ret = debounce_timing_setting(bank, pin % bank->gc.ngpio, 2152 2152 + ret = debounce_timing_setting(bank, pin % bank->chip.gc.ngpio, 2150 2153 nanosecs); 2151 2154 if (ret) 2152 2155 dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin); 2153 2156 else 2154 2154 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, 2157 2157 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, 2155 2158 gpio); 2156 2159 return ret; 2157 2160 } 2158 2161 2159 2159 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio); 2162 2162 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, gpio); 2160 2163 2161 2164 return 0; 2162 2165 } ··· 2169 2172 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2170 2173 struct npcm8xx_gpio *bank = 2171 2174 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2172 2172 - int gpio = pin % bank->gc.ngpio; 2175 2175 + int gpio = pin % bank->chip.gc.ngpio; 2173 2176 unsigned long pinmask = BIT(gpio); 2174 2177 u32 ie, oe, pu, pd; 2175 2178 int rc = 0; ··· 2232 2235 struct npcm8xx_gpio *bank = 2233 2236 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2234 2237 u32 arg = pinconf_to_config_argument(config); 2235 2235 - int gpio = BIT(pin % bank->gc.ngpio); 2238 2238 + int gpio = BIT(pin % bank->chip.gc.ngpio); 2236 2239 2237 2240 switch (param) { 2238 2241 case PIN_CONFIG_BIAS_DISABLE: 2239 2239 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2240 2240 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2242 2242 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); 2243 2243 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); 2241 2244 break; 2242 2245 case PIN_CONFIG_BIAS_PULL_DOWN: 2243 2243 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2244 2244 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2246 2246 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); 2247 2247 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); 2245 2248 break; 2246 2249 case PIN_CONFIG_BIAS_PULL_UP: 2247 2247 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2248 2248 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2250 2250 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); 2251 2251 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); 2249 2252 break; 2250 2253 case PIN_CONFIG_INPUT_ENABLE: 2251 2254 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); 2252 2252 - bank->direction_input(&bank->gc, pin % bank->gc.ngpio); 2255 2255 + bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio); 2253 2256 break; 2254 2257 case PIN_CONFIG_OUTPUT: 2255 2255 - bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); 2258 2258 + bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg); 2256 2259 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); 2257 2260 break; 2258 2261 case PIN_CONFIG_DRIVE_PUSH_PULL: 2259 2259 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2262 2262 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2260 2263 break; 2261 2264 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 2262 2262 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2265 2265 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2263 2266 break; 2264 2267 case PIN_CONFIG_INPUT_DEBOUNCE: 2265 2268 return npcm_set_debounce(npcm, pin, arg * 1000); ··· 2310 2313 { 2311 2314 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); 2312 2315 2313 2313 - return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent), 2314 2314 - bank->pinctrl_id, bank->gc.base, 2315 2315 - bank->gc.ngpio); 2316 2316 + return gpiochip_add_pin_range(&bank->chip.gc, dev_name(chip->parent), 2317 2317 + bank->pinctrl_id, bank->chip.gc.base, 2318 2318 + bank->chip.gc.ngpio); 2316 2319 } 2317 2320 2318 2321 static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) 2319 2322 { 2323 2323 + struct gpio_generic_chip_config config; 2320 2324 struct fwnode_reference_args args; 2321 2325 struct device *dev = pctrl->dev; 2322 2326 struct fwnode_handle *child; ··· 2329 2331 if (!pctrl->gpio_bank[id].base) 2330 2332 return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id); 2331 2333 2332 2332 - ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, 2333 2333 - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, 2334 2334 - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, 2335 2335 - NULL, 2336 2336 - NULL, 2337 2337 - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, 2338 2338 - BGPIOF_READ_OUTPUT_REG_SET); 2334 2334 + config = (typeof(config)){ 2335 2335 + .dev = dev, 2336 2336 + .sz = 4, 2337 2337 + .dat = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, 2338 2338 + .set = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, 2339 2339 + .dirin = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, 2340 2340 + .flags = GPIO_GENERIC_READ_OUTPUT_REG_SET, 2341 2341 + }; 2342 2342 + 2343 2343 + ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config); 2339 2344 if (ret) 2340 2340 - return dev_err_probe(dev, ret, "bgpio_init() failed\n"); 2345 2345 + return dev_err_probe(dev, ret, 2346 2346 + "failed to initialize the generic GPIO chip\n"); 2341 2347 2342 2348 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args); 2343 2349 if (ret < 0) ··· 2355 2353 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; 2356 2354 pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; 2357 2355 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; 2358 2358 - pctrl->gpio_bank[id].gc.base = -1; 2359 2359 - pctrl->gpio_bank[id].gc.ngpio = args.args[2]; 2360 2360 - pctrl->gpio_bank[id].gc.owner = THIS_MODULE; 2361 2361 - pctrl->gpio_bank[id].gc.parent = dev; 2362 2362 - pctrl->gpio_bank[id].gc.fwnode = child; 2363 2363 - pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 2364 2364 - if (pctrl->gpio_bank[id].gc.label == NULL) 2356 2356 + pctrl->gpio_bank[id].chip.gc.base = -1; 2357 2357 + pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2]; 2358 2358 + pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE; 2359 2359 + pctrl->gpio_bank[id].chip.gc.parent = dev; 2360 2360 + pctrl->gpio_bank[id].chip.gc.fwnode = child; 2361 2361 + pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 2362 2362 + if (pctrl->gpio_bank[id].chip.gc.label == NULL) 2365 2363 return -ENOMEM; 2366 2364 2367 2367 - pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; 2368 2368 - pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; 2369 2369 - pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; 2370 2370 - pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; 2371 2371 - pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; 2372 2372 - pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; 2373 2373 - pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; 2374 2374 - pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free; 2365 2365 + pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show; 2366 2366 + pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input; 2367 2367 + pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input; 2368 2368 + pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output; 2369 2369 + pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output; 2370 2370 + pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request; 2371 2371 + pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request; 2372 2372 + pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free; 2375 2373 for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) 2376 2374 pctrl->gpio_bank[id].debounce.set_val[i] = false; 2377 2377 - pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges; 2375 2375 + pctrl->gpio_bank[id].chip.gc.add_pin_ranges = npcmgpio_add_pin_ranges; 2378 2376 id++; 2379 2377 } 2380 2378 ··· 2389 2387 for (id = 0 ; id < pctrl->bank_num ; id++) { 2390 2388 struct gpio_irq_chip *girq; 2391 2389 2392 2392 - girq = &pctrl->gpio_bank[id].gc.irq; 2390 2390 + girq = &pctrl->gpio_bank[id].chip.gc.irq; 2393 2391 girq->chip = &pctrl->gpio_bank[id].irq_chip; 2394 2392 girq->parent_handler = npcmgpio_irq_handler; 2395 2393 girq->num_parents = 1; ··· 2403 2401 girq->default_type = IRQ_TYPE_NONE; 2404 2402 girq->handler = handle_level_irq; 2405 2403 ret = devm_gpiochip_add_data(pctrl->dev, 2406 2406 - &pctrl->gpio_bank[id].gc, 2404 2404 + &pctrl->gpio_bank[id].chip.gc, 2407 2405 &pctrl->gpio_bank[id]); 2408 2406 if (ret) 2409 2407 return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id);

+29 -17

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

reviewed

··· 11 11 12 12 #include <linux/device.h> 13 13 #include <linux/gpio/driver.h> 14 14 + #include <linux/gpio/generic.h> 14 15 #include <linux/interrupt.h> 15 16 #include <linux/irq.h> 16 17 #include <linux/mfd/syscon.h> ··· 48 47 struct wpcm450_bank; 49 48 50 49 struct wpcm450_gpio { 51 51 - struct gpio_chip gc; 50 50 + struct gpio_generic_chip chip; 52 51 struct wpcm450_pinctrl *pctrl; 53 52 const struct wpcm450_bank *bank; 54 53 }; ··· 185 184 } 186 185 187 186 /* 188 188 - * This is an implementation of the gpio_chip->get() function, for use in 189 189 - * wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided 190 190 - * implementation there, because it would require taking gpio_chip->bgpio_lock, 191 191 - * which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where 192 192 - * a raw spin lock is held. 187 187 + * FIXME: This is an implementation of the gpio_chip->get() function, for use 188 188 + * in wpcm450_gpio_fix_evpol(). It was implemented back when gpio-mmio used a 189 189 + * regular spinlock internally, while wpcm450_gpio_fix_evpol() needed to work 190 190 + * in contexts with a raw spinlock held. Since then, the gpio generic chip has 191 191 + * been switched to using a raw spinlock so this should be converted to using 192 192 + * the locking interfaces provided in linux/gpio/gneneric.h. 193 193 */ 194 194 static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset) 195 195 { ··· 331 329 for_each_set_bit(bit, &pending, 32) { 332 330 int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); 333 331 334 334 - generic_handle_domain_irq(gpio->gc.irq.domain, offset); 332 332 + generic_handle_domain_irq(gpio->chip.gc.irq.domain, offset); 335 333 } 336 334 chained_irq_exit(chip, desc); 337 335 } ··· 1014 1012 struct wpcm450_gpio *gpio = gpiochip_get_data(chip); 1015 1013 const struct wpcm450_bank *bank = gpio->bank; 1016 1014 1017 1017 - return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev), 1015 1015 + return gpiochip_add_pin_range(&gpio->chip.gc, dev_name(gpio->pctrl->dev), 1018 1016 0, bank->base, bank->length); 1019 1017 } 1020 1018 ··· 1031 1029 "Resource fail for GPIO controller\n"); 1032 1030 1033 1031 for_each_gpiochip_node(dev, child) { 1032 1032 + struct gpio_generic_chip_config config; 1034 1033 void __iomem *dat = NULL; 1035 1034 void __iomem *set = NULL; 1036 1035 void __iomem *dirout = NULL; ··· 1061 1058 set = pctrl->gpio_base + bank->dataout; 1062 1059 dirout = pctrl->gpio_base + bank->cfg0; 1063 1060 } else { 1064 1064 - flags = BGPIOF_NO_OUTPUT; 1061 1061 + flags = GPIO_GENERIC_NO_OUTPUT; 1065 1062 } 1066 1066 - ret = bgpio_init(&gpio->gc, dev, 4, 1067 1067 - dat, set, NULL, dirout, NULL, flags); 1063 1063 + 1064 1064 + config = (typeof(config)){ 1065 1065 + .dev = dev, 1066 1066 + .sz = 4, 1067 1067 + .dat = dat, 1068 1068 + .set = set, 1069 1069 + .dirout = dirout, 1070 1070 + .flags = flags, 1071 1071 + }; 1072 1072 + 1073 1073 + ret = gpio_generic_chip_init(&gpio->chip, &config); 1068 1074 if (ret < 0) 1069 1075 return dev_err_probe(dev, ret, "GPIO initialization failed\n"); 1070 1076 1071 1071 - gpio->gc.ngpio = bank->length; 1072 1072 - gpio->gc.set_config = wpcm450_gpio_set_config; 1073 1073 - gpio->gc.fwnode = child; 1074 1074 - gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; 1077 1077 + gpio->chip.gc.ngpio = bank->length; 1078 1078 + gpio->chip.gc.set_config = wpcm450_gpio_set_config; 1079 1079 + gpio->chip.gc.fwnode = child; 1080 1080 + gpio->chip.gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; 1075 1081 1076 1076 - girq = &gpio->gc.irq; 1082 1082 + girq = &gpio->chip.gc.irq; 1077 1083 gpio_irq_chip_set_chip(girq, &wpcm450_gpio_irqchip); 1078 1084 girq->parent_handler = wpcm450_gpio_irqhandler; 1079 1085 girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS, ··· 1106 1094 girq->num_parents++; 1107 1095 } 1108 1096 1109 1109 - ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio); 1097 1097 + ret = devm_gpiochip_add_data(dev, &gpio->chip.gc, gpio); 1110 1098 if (ret) 1111 1099 return dev_err_probe(dev, ret, "Failed to add GPIO chip\n"); 1112 1100 }

+16 -10

drivers/pinctrl/pinctrl-equilibrium.c

reviewed

··· 2 2 /* Copyright (C) 2019 Intel Corporation */ 3 3 4 4 #include <linux/gpio/driver.h> 5 5 + #include <linux/gpio/generic.h> 5 6 #include <linux/module.h> 6 7 #include <linux/of.h> 7 8 #include <linux/of_address.h> ··· 180 179 struct gpio_irq_chip *girq; 181 180 struct gpio_chip *gc; 182 181 183 183 - gc = &gctrl->chip; 182 182 + gc = &gctrl->chip.gc; 184 183 gc->label = gctrl->name; 185 184 gc->fwnode = gctrl->fwnode; 186 185 gc->request = gpiochip_generic_request; ··· 192 191 return 0; 193 192 } 194 193 195 195 - girq = &gctrl->chip.irq; 194 194 + girq = &gctrl->chip.gc.irq; 196 195 gpio_irq_chip_set_chip(girq, &eqbr_irq_chip); 197 196 girq->parent_handler = eqbr_irq_handler; 198 197 girq->num_parents = 1; ··· 209 208 210 209 static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata) 211 210 { 211 211 + struct gpio_generic_chip_config config; 212 212 struct device *dev = drvdata->dev; 213 213 struct eqbr_gpio_ctrl *gctrl; 214 214 struct device_node *np; ··· 241 239 } 242 240 raw_spin_lock_init(&gctrl->lock); 243 241 244 244 - ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8, 245 245 - gctrl->membase + GPIO_IN, 246 246 - gctrl->membase + GPIO_OUTSET, 247 247 - gctrl->membase + GPIO_OUTCLR, 248 248 - gctrl->membase + GPIO_DIR, 249 249 - NULL, 0); 242 242 + config = (typeof(config)){ 243 243 + .dev = dev, 244 244 + .sz = gctrl->bank->nr_pins / 8, 245 245 + .dat = gctrl->membase + GPIO_IN, 246 246 + .set = gctrl->membase + GPIO_OUTSET, 247 247 + .clr = gctrl->membase + GPIO_OUTCLR, 248 248 + .dirout = gctrl->membase + GPIO_DIR, 249 249 + }; 250 250 + 251 251 + ret = gpio_generic_chip_init(&gctrl->chip, &config); 250 252 if (ret) { 251 253 dev_err(dev, "unable to init generic GPIO\n"); 252 254 return ret; ··· 260 254 if (ret) 261 255 return ret; 262 256 263 263 - ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl); 257 257 + ret = devm_gpiochip_add_data(dev, &gctrl->chip.gc, gctrl); 264 258 if (ret) 265 259 return ret; 266 260 } ··· 505 499 bank->pin_base, pin); 506 500 return -ENODEV; 507 501 } 508 508 - gc = &gctrl->chip; 502 502 + gc = &gctrl->chip.gc; 509 503 gc->direction_output(gc, offset, 0); 510 504 continue; 511 505 default:

+1 -1

drivers/pinctrl/pinctrl-equilibrium.h

reviewed

··· 96 96 * @lock: spin lock to protect gpio register write. 97 97 */ 98 98 struct eqbr_gpio_ctrl { 99 99 - struct gpio_chip chip; 99 99 + struct gpio_generic_chip chip; 100 100 struct fwnode_handle *fwnode; 101 101 struct eqbr_pin_bank *bank; 102 102 void __iomem *membase;

+215

drivers/pinctrl/pinctrl-max7360.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright 2025 Bootlin 4 4 + * 5 5 + * Author: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 6 6 + */ 7 7 + 8 8 + #include <linux/array_size.h> 9 9 + #include <linux/dev_printk.h> 10 10 + #include <linux/device.h> 11 11 + #include <linux/device/devres.h> 12 12 + #include <linux/err.h> 13 13 + #include <linux/init.h> 14 14 + #include <linux/mfd/max7360.h> 15 15 + #include <linux/module.h> 16 16 + #include <linux/platform_device.h> 17 17 + #include <linux/regmap.h> 18 18 + #include <linux/stddef.h> 19 19 + 20 20 + #include <linux/pinctrl/pinctrl.h> 21 21 + #include <linux/pinctrl/pinconf-generic.h> 22 22 + #include <linux/pinctrl/pinmux.h> 23 23 + 24 24 + #include "core.h" 25 25 + #include "pinmux.h" 26 26 + 27 27 + struct max7360_pinctrl { 28 28 + struct pinctrl_dev *pctldev; 29 29 + struct pinctrl_desc pinctrl_desc; 30 30 + }; 31 31 + 32 32 + static const struct pinctrl_pin_desc max7360_pins[] = { 33 33 + PINCTRL_PIN(0, "PORT0"), 34 34 + PINCTRL_PIN(1, "PORT1"), 35 35 + PINCTRL_PIN(2, "PORT2"), 36 36 + PINCTRL_PIN(3, "PORT3"), 37 37 + PINCTRL_PIN(4, "PORT4"), 38 38 + PINCTRL_PIN(5, "PORT5"), 39 39 + PINCTRL_PIN(6, "PORT6"), 40 40 + PINCTRL_PIN(7, "PORT7"), 41 41 + }; 42 42 + 43 43 + static const unsigned int port0_pins[] = {0}; 44 44 + static const unsigned int port1_pins[] = {1}; 45 45 + static const unsigned int port2_pins[] = {2}; 46 46 + static const unsigned int port3_pins[] = {3}; 47 47 + static const unsigned int port4_pins[] = {4}; 48 48 + static const unsigned int port5_pins[] = {5}; 49 49 + static const unsigned int port6_pins[] = {6}; 50 50 + static const unsigned int port7_pins[] = {7}; 51 51 + static const unsigned int rotary_pins[] = {6, 7}; 52 52 + 53 53 + static const struct pingroup max7360_groups[] = { 54 54 + PINCTRL_PINGROUP("PORT0", port0_pins, ARRAY_SIZE(port0_pins)), 55 55 + PINCTRL_PINGROUP("PORT1", port1_pins, ARRAY_SIZE(port1_pins)), 56 56 + PINCTRL_PINGROUP("PORT2", port2_pins, ARRAY_SIZE(port2_pins)), 57 57 + PINCTRL_PINGROUP("PORT3", port3_pins, ARRAY_SIZE(port3_pins)), 58 58 + PINCTRL_PINGROUP("PORT4", port4_pins, ARRAY_SIZE(port4_pins)), 59 59 + PINCTRL_PINGROUP("PORT5", port5_pins, ARRAY_SIZE(port5_pins)), 60 60 + PINCTRL_PINGROUP("PORT6", port6_pins, ARRAY_SIZE(port6_pins)), 61 61 + PINCTRL_PINGROUP("PORT7", port7_pins, ARRAY_SIZE(port7_pins)), 62 62 + PINCTRL_PINGROUP("ROTARY", rotary_pins, ARRAY_SIZE(rotary_pins)), 63 63 + }; 64 64 + 65 65 + static int max7360_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 66 66 + { 67 67 + return ARRAY_SIZE(max7360_groups); 68 68 + } 69 69 + 70 70 + static const char *max7360_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 71 71 + unsigned int group) 72 72 + { 73 73 + return max7360_groups[group].name; 74 74 + } 75 75 + 76 76 + static int max7360_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 77 77 + unsigned int group, 78 78 + const unsigned int **pins, 79 79 + unsigned int *num_pins) 80 80 + { 81 81 + *pins = max7360_groups[group].pins; 82 82 + *num_pins = max7360_groups[group].npins; 83 83 + return 0; 84 84 + } 85 85 + 86 86 + static const struct pinctrl_ops max7360_pinctrl_ops = { 87 87 + .get_groups_count = max7360_pinctrl_get_groups_count, 88 88 + .get_group_name = max7360_pinctrl_get_group_name, 89 89 + .get_group_pins = max7360_pinctrl_get_group_pins, 90 90 + #ifdef CONFIG_OF 91 91 + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 92 92 + .dt_free_map = pinconf_generic_dt_free_map, 93 93 + #endif 94 94 + }; 95 95 + 96 96 + static const char * const simple_groups[] = { 97 97 + "PORT0", "PORT1", "PORT2", "PORT3", 98 98 + "PORT4", "PORT5", "PORT6", "PORT7", 99 99 + }; 100 100 + 101 101 + static const char * const rotary_groups[] = { "ROTARY" }; 102 102 + 103 103 + #define MAX7360_PINCTRL_FN_GPIO 0 104 104 + #define MAX7360_PINCTRL_FN_PWM 1 105 105 + #define MAX7360_PINCTRL_FN_ROTARY 2 106 106 + static const struct pinfunction max7360_functions[] = { 107 107 + [MAX7360_PINCTRL_FN_GPIO] = PINCTRL_PINFUNCTION("gpio", simple_groups, 108 108 + ARRAY_SIZE(simple_groups)), 109 109 + [MAX7360_PINCTRL_FN_PWM] = PINCTRL_PINFUNCTION("pwm", simple_groups, 110 110 + ARRAY_SIZE(simple_groups)), 111 111 + [MAX7360_PINCTRL_FN_ROTARY] = PINCTRL_PINFUNCTION("rotary", rotary_groups, 112 112 + ARRAY_SIZE(rotary_groups)), 113 113 + }; 114 114 + 115 115 + static int max7360_get_functions_count(struct pinctrl_dev *pctldev) 116 116 + { 117 117 + return ARRAY_SIZE(max7360_functions); 118 118 + } 119 119 + 120 120 + static const char *max7360_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) 121 121 + { 122 122 + return max7360_functions[selector].name; 123 123 + } 124 124 + 125 125 + static int max7360_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 126 126 + const char * const **groups, 127 127 + unsigned int * const num_groups) 128 128 + { 129 129 + *groups = max7360_functions[selector].groups; 130 130 + *num_groups = max7360_functions[selector].ngroups; 131 131 + 132 132 + return 0; 133 133 + } 134 134 + 135 135 + static int max7360_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 136 136 + unsigned int group) 137 137 + { 138 138 + struct regmap *regmap = dev_get_regmap(pctldev->dev->parent, NULL); 139 139 + int val; 140 140 + 141 141 + /* 142 142 + * GPIO and PWM functions are the same: we only need to handle the 143 143 + * rotary encoder function, on pins 6 and 7. 144 144 + */ 145 145 + if (max7360_groups[group].pins[0] >= 6) { 146 146 + if (selector == MAX7360_PINCTRL_FN_ROTARY) 147 147 + val = MAX7360_GPIO_CFG_RTR_EN; 148 148 + else 149 149 + val = 0; 150 150 + 151 151 + return regmap_write_bits(regmap, MAX7360_REG_GPIOCFG, MAX7360_GPIO_CFG_RTR_EN, val); 152 152 + } 153 153 + 154 154 + return 0; 155 155 + } 156 156 + 157 157 + static const struct pinmux_ops max7360_pmxops = { 158 158 + .get_functions_count = max7360_get_functions_count, 159 159 + .get_function_name = max7360_get_function_name, 160 160 + .get_function_groups = max7360_get_function_groups, 161 161 + .set_mux = max7360_set_mux, 162 162 + .strict = true, 163 163 + }; 164 164 + 165 165 + static int max7360_pinctrl_probe(struct platform_device *pdev) 166 166 + { 167 167 + struct regmap *regmap; 168 168 + struct pinctrl_desc *pd; 169 169 + struct max7360_pinctrl *chip; 170 170 + struct device *dev = &pdev->dev; 171 171 + 172 172 + regmap = dev_get_regmap(dev->parent, NULL); 173 173 + if (!regmap) 174 174 + return dev_err_probe(dev, -ENODEV, "Could not get parent regmap\n"); 175 175 + 176 176 + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 177 177 + if (!chip) 178 178 + return -ENOMEM; 179 179 + 180 180 + pd = &chip->pinctrl_desc; 181 181 + 182 182 + pd->pctlops = &max7360_pinctrl_ops; 183 183 + pd->pmxops = &max7360_pmxops; 184 184 + pd->name = dev_name(dev); 185 185 + pd->pins = max7360_pins; 186 186 + pd->npins = MAX7360_MAX_GPIO; 187 187 + pd->owner = THIS_MODULE; 188 188 + 189 189 + /* 190 190 + * This MFD sub-device does not have any associated device tree node: 191 191 + * properties are stored in the device node of the parent (MFD) device 192 192 + * and this same node is used in phandles of client devices. 193 193 + * Reuse this device tree node here, as otherwise the pinctrl subsystem 194 194 + * would be confused by this topology. 195 195 + */ 196 196 + device_set_of_node_from_dev(dev, dev->parent); 197 197 + 198 198 + chip->pctldev = devm_pinctrl_register(dev, pd, chip); 199 199 + if (IS_ERR(chip->pctldev)) 200 200 + return dev_err_probe(dev, PTR_ERR(chip->pctldev), "can't register controller\n"); 201 201 + 202 202 + return 0; 203 203 + } 204 204 + 205 205 + static struct platform_driver max7360_pinctrl_driver = { 206 206 + .driver = { 207 207 + .name = "max7360-pinctrl", 208 208 + }, 209 209 + .probe = max7360_pinctrl_probe, 210 210 + }; 211 211 + module_platform_driver(max7360_pinctrl_driver); 212 212 + 213 213 + MODULE_DESCRIPTION("MAX7360 pinctrl driver"); 214 214 + MODULE_AUTHOR("Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>"); 215 215 + MODULE_LICENSE("GPL");

+19 -13

drivers/pinctrl/stm32/pinctrl-stm32-hdp.c

reviewed

··· 6 6 #include <linux/bits.h> 7 7 #include <linux/clk.h> 8 8 #include <linux/gpio/driver.h> 9 9 + #include <linux/gpio/generic.h> 9 10 #include <linux/io.h> 10 11 #include <linux/of.h> 11 12 #include <linux/of_device.h> ··· 46 45 void __iomem *base; 47 46 struct clk *clk; 48 47 struct pinctrl_dev *pctl_dev; 49 49 - struct gpio_chip gpio_chip; 48 48 + struct gpio_generic_chip gpio_chip; 50 49 u32 mux_conf; 51 50 u32 gposet_conf; 52 51 const char * const *func_name; ··· 604 603 605 604 static int stm32_hdp_probe(struct platform_device *pdev) 606 605 { 606 606 + struct gpio_generic_chip_config config; 607 607 struct device *dev = &pdev->dev; 608 608 struct stm32_hdp *hdp; 609 609 u8 version; ··· 637 635 if (err) 638 636 return dev_err_probe(dev, err, "Failed to enable pinctrl\n"); 639 637 640 640 - hdp->gpio_chip.get_direction = stm32_hdp_gpio_get_direction; 641 641 - hdp->gpio_chip.ngpio = ARRAY_SIZE(stm32_hdp_pins); 642 642 - hdp->gpio_chip.can_sleep = true; 643 643 - hdp->gpio_chip.names = stm32_hdp_pins_group; 638 638 + hdp->gpio_chip.gc.get_direction = stm32_hdp_gpio_get_direction; 639 639 + hdp->gpio_chip.gc.ngpio = ARRAY_SIZE(stm32_hdp_pins); 640 640 + hdp->gpio_chip.gc.can_sleep = true; 641 641 + hdp->gpio_chip.gc.names = stm32_hdp_pins_group; 644 642 645 645 - err = bgpio_init(&hdp->gpio_chip, dev, 4, 646 646 - hdp->base + HDP_GPOVAL, 647 647 - hdp->base + HDP_GPOSET, 648 648 - hdp->base + HDP_GPOCLR, 649 649 - NULL, NULL, BGPIOF_NO_INPUT); 643 643 + config = (typeof(config)){ 644 644 + .dev = dev, 645 645 + .sz = 4, 646 646 + .dat = hdp->base + HDP_GPOVAL, 647 647 + .set = hdp->base + HDP_GPOSET, 648 648 + .clr = hdp->base + HDP_GPOCLR, 649 649 + .flags = GPIO_GENERIC_NO_INPUT, 650 650 + }; 651 651 + 652 652 + err = gpio_generic_chip_init(&hdp->gpio_chip, &config); 650 653 if (err) 651 651 - return dev_err_probe(dev, err, "Failed to init bgpio\n"); 654 654 + return dev_err_probe(dev, err, "Failed to init the generic GPIO chip\n"); 652 655 653 653 - 654 654 - err = devm_gpiochip_add_data(dev, &hdp->gpio_chip, hdp); 656 656 + err = devm_gpiochip_add_data(dev, &hdp->gpio_chip.gc, hdp); 655 657 if (err) 656 658 return dev_err_probe(dev, err, "Failed to add gpiochip\n"); 657 659

+10

drivers/pwm/Kconfig

reviewed

··· 441 441 To compile this driver as a module, choose M here: the module 442 442 will be called pwm-lpss-platform. 443 443 444 444 + config PWM_MAX7360 445 445 + tristate "MAX7360 PWMs" 446 446 + depends on MFD_MAX7360 447 447 + help 448 448 + PWM driver for Maxim Integrated MAX7360 multifunction device, with 449 449 + support for up to 8 PWM outputs. 450 450 + 451 451 + To compile this driver as a module, choose M here: the module 452 452 + will be called pwm-max7360. 453 453 + 444 454 config PWM_MC33XS2410 445 455 tristate "MC33XS2410 PWM support" 446 456 depends on OF

+1

drivers/pwm/Makefile

reviewed

··· 38 38 obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o 39 39 obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o 40 40 obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o 41 41 + obj-$(CONFIG_PWM_MAX7360) += pwm-max7360.o 41 42 obj-$(CONFIG_PWM_MC33XS2410) += pwm-mc33xs2410.o 42 43 obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o 43 44 obj-$(CONFIG_PWM_MESON) += pwm-meson.o

+209

drivers/pwm/pwm-max7360.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright 2025 Bootlin 4 4 + * 5 5 + * Author: Kamel BOUHARA <kamel.bouhara@bootlin.com> 6 6 + * Author: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> 7 7 + * 8 8 + * PWM functionality of the MAX7360 multi-function device. 9 9 + * https://www.analog.com/media/en/technical-documentation/data-sheets/MAX7360.pdf 10 10 + * 11 11 + * Limitations: 12 12 + * - Only supports normal polarity. 13 13 + * - The period is fixed to 2 ms. 14 14 + * - Only the duty cycle can be changed, new values are applied at the beginning 15 15 + * of the next cycle. 16 16 + * - When disabled, the output is put in Hi-Z immediately. 17 17 + */ 18 18 + #include <linux/bits.h> 19 19 + #include <linux/dev_printk.h> 20 20 + #include <linux/err.h> 21 21 + #include <linux/math64.h> 22 22 + #include <linux/mfd/max7360.h> 23 23 + #include <linux/minmax.h> 24 24 + #include <linux/mod_devicetable.h> 25 25 + #include <linux/module.h> 26 26 + #include <linux/platform_device.h> 27 27 + #include <linux/pwm.h> 28 28 + #include <linux/regmap.h> 29 29 + #include <linux/time.h> 30 30 + #include <linux/types.h> 31 31 + 32 32 + #define MAX7360_NUM_PWMS 8 33 33 + #define MAX7360_PWM_MAX 255 34 34 + #define MAX7360_PWM_STEPS 256 35 35 + #define MAX7360_PWM_PERIOD_NS (2 * NSEC_PER_MSEC) 36 36 + 37 37 + struct max7360_pwm_waveform { 38 38 + u8 duty_steps; 39 39 + bool enabled; 40 40 + }; 41 41 + 42 42 + static int max7360_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 43 43 + { 44 44 + struct regmap *regmap = pwmchip_get_drvdata(chip); 45 45 + 46 46 + /* 47 47 + * Make sure we use the individual PWM configuration register and not 48 48 + * the global one. 49 49 + * We never need to use the global one, so there is no need to revert 50 50 + * that in the .free() callback. 51 51 + */ 52 52 + return regmap_write_bits(regmap, MAX7360_REG_PWMCFG(pwm->hwpwm), 53 53 + MAX7360_PORT_CFG_COMMON_PWM, 0); 54 54 + } 55 55 + 56 56 + static int max7360_pwm_round_waveform_tohw(struct pwm_chip *chip, 57 57 + struct pwm_device *pwm, 58 58 + const struct pwm_waveform *wf, 59 59 + void *_wfhw) 60 60 + { 61 61 + struct max7360_pwm_waveform *wfhw = _wfhw; 62 62 + u64 duty_steps; 63 63 + 64 64 + /* 65 65 + * Ignore user provided values for period_length_ns and duty_offset_ns: 66 66 + * we only support fixed period of MAX7360_PWM_PERIOD_NS and offset of 0. 67 67 + * Values from 0 to 254 as duty_steps will provide duty cycles of 0/256 68 68 + * to 254/256, while value 255 will provide a duty cycle of 100%. 69 69 + */ 70 70 + if (wf->duty_length_ns >= MAX7360_PWM_PERIOD_NS) { 71 71 + duty_steps = MAX7360_PWM_MAX; 72 72 + } else { 73 73 + duty_steps = (u32)wf->duty_length_ns * MAX7360_PWM_STEPS / MAX7360_PWM_PERIOD_NS; 74 74 + if (duty_steps == MAX7360_PWM_MAX) 75 75 + duty_steps = MAX7360_PWM_MAX - 1; 76 76 + } 77 77 + 78 78 + wfhw->duty_steps = min(MAX7360_PWM_MAX, duty_steps); 79 79 + wfhw->enabled = !!wf->period_length_ns; 80 80 + 81 81 + if (wf->period_length_ns && wf->period_length_ns < MAX7360_PWM_PERIOD_NS) 82 82 + return 1; 83 83 + else 84 84 + return 0; 85 85 + } 86 86 + 87 87 + static int max7360_pwm_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm, 88 88 + const void *_wfhw, struct pwm_waveform *wf) 89 89 + { 90 90 + const struct max7360_pwm_waveform *wfhw = _wfhw; 91 91 + 92 92 + wf->period_length_ns = wfhw->enabled ? MAX7360_PWM_PERIOD_NS : 0; 93 93 + wf->duty_offset_ns = 0; 94 94 + 95 95 + if (wfhw->enabled) { 96 96 + if (wfhw->duty_steps == MAX7360_PWM_MAX) 97 97 + wf->duty_length_ns = MAX7360_PWM_PERIOD_NS; 98 98 + else 99 99 + wf->duty_length_ns = DIV_ROUND_UP(wfhw->duty_steps * MAX7360_PWM_PERIOD_NS, 100 100 + MAX7360_PWM_STEPS); 101 101 + } else { 102 102 + wf->duty_length_ns = 0; 103 103 + } 104 104 + 105 105 + return 0; 106 106 + } 107 107 + 108 108 + static int max7360_pwm_write_waveform(struct pwm_chip *chip, 109 109 + struct pwm_device *pwm, 110 110 + const void *_wfhw) 111 111 + { 112 112 + struct regmap *regmap = pwmchip_get_drvdata(chip); 113 113 + const struct max7360_pwm_waveform *wfhw = _wfhw; 114 114 + unsigned int val; 115 115 + int ret; 116 116 + 117 117 + if (wfhw->enabled) { 118 118 + ret = regmap_write(regmap, MAX7360_REG_PWM(pwm->hwpwm), wfhw->duty_steps); 119 119 + if (ret) 120 120 + return ret; 121 121 + } 122 122 + 123 123 + val = wfhw->enabled ? BIT(pwm->hwpwm) : 0; 124 124 + return regmap_write_bits(regmap, MAX7360_REG_GPIOCTRL, BIT(pwm->hwpwm), val); 125 125 + } 126 126 + 127 127 + static int max7360_pwm_read_waveform(struct pwm_chip *chip, 128 128 + struct pwm_device *pwm, 129 129 + void *_wfhw) 130 130 + { 131 131 + struct regmap *regmap = pwmchip_get_drvdata(chip); 132 132 + struct max7360_pwm_waveform *wfhw = _wfhw; 133 133 + unsigned int val; 134 134 + int ret; 135 135 + 136 136 + ret = regmap_read(regmap, MAX7360_REG_GPIOCTRL, &val); 137 137 + if (ret) 138 138 + return ret; 139 139 + 140 140 + if (val & BIT(pwm->hwpwm)) { 141 141 + wfhw->enabled = true; 142 142 + ret = regmap_read(regmap, MAX7360_REG_PWM(pwm->hwpwm), &val); 143 143 + if (ret) 144 144 + return ret; 145 145 + 146 146 + wfhw->duty_steps = val; 147 147 + } else { 148 148 + wfhw->enabled = false; 149 149 + wfhw->duty_steps = 0; 150 150 + } 151 151 + 152 152 + return 0; 153 153 + } 154 154 + 155 155 + static const struct pwm_ops max7360_pwm_ops = { 156 156 + .request = max7360_pwm_request, 157 157 + .round_waveform_tohw = max7360_pwm_round_waveform_tohw, 158 158 + .round_waveform_fromhw = max7360_pwm_round_waveform_fromhw, 159 159 + .read_waveform = max7360_pwm_read_waveform, 160 160 + .write_waveform = max7360_pwm_write_waveform, 161 161 + }; 162 162 + 163 163 + static int max7360_pwm_probe(struct platform_device *pdev) 164 164 + { 165 165 + struct device *dev = &pdev->dev; 166 166 + struct pwm_chip *chip; 167 167 + struct regmap *regmap; 168 168 + int ret; 169 169 + 170 170 + regmap = dev_get_regmap(dev->parent, NULL); 171 171 + if (!regmap) 172 172 + return dev_err_probe(dev, -ENODEV, "Could not get parent regmap\n"); 173 173 + 174 174 + /* 175 175 + * This MFD sub-device does not have any associated device tree node: 176 176 + * properties are stored in the device node of the parent (MFD) device 177 177 + * and this same node is used in phandles of client devices. 178 178 + * Reuse this device tree node here, as otherwise the PWM subsystem 179 179 + * would be confused by this topology. 180 180 + */ 181 181 + device_set_of_node_from_dev(dev, dev->parent); 182 182 + 183 183 + chip = devm_pwmchip_alloc(dev, MAX7360_NUM_PWMS, 0); 184 184 + if (IS_ERR(chip)) 185 185 + return PTR_ERR(chip); 186 186 + chip->ops = &max7360_pwm_ops; 187 187 + 188 188 + pwmchip_set_drvdata(chip, regmap); 189 189 + 190 190 + ret = devm_pwmchip_add(dev, chip); 191 191 + if (ret) 192 192 + return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); 193 193 + 194 194 + return 0; 195 195 + } 196 196 + 197 197 + static struct platform_driver max7360_pwm_driver = { 198 198 + .driver = { 199 199 + .name = "max7360-pwm", 200 200 + .probe_type = PROBE_PREFER_ASYNCHRONOUS, 201 201 + }, 202 202 + .probe = max7360_pwm_probe, 203 203 + }; 204 204 + module_platform_driver(max7360_pwm_driver); 205 205 + 206 206 + MODULE_DESCRIPTION("MAX7360 PWM driver"); 207 207 + MODULE_AUTHOR("Kamel BOUHARA <kamel.bouhara@bootlin.com>"); 208 208 + MODULE_AUTHOR("Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>"); 209 209 + MODULE_LICENSE("GPL");

+10

drivers/rtc/Kconfig

reviewed

··· 416 416 This driver can also be built as a module, if so, the module will be 417 417 called "rtc-nct3018y". 418 418 419 419 + config RTC_DRV_NCT6694 420 420 + tristate "Nuvoton NCT6694 RTC support" 421 421 + depends on MFD_NCT6694 422 422 + help 423 423 + If you say yes to this option, support will be included for Nuvoton 424 424 + NCT6694, a USB device to RTC. 425 425 + 426 426 + This driver can also be built as a module. If so, the module will 427 427 + be called rtc-nct6694. 428 428 + 419 429 config RTC_DRV_RK808 420 430 tristate "Rockchip RK805/RK808/RK809/RK817/RK818 RTC" 421 431 depends on MFD_RK8XX

+1

drivers/rtc/Makefile

reviewed

··· 119 119 obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o 120 120 obj-$(CONFIG_RTC_DRV_GAMECUBE) += rtc-gamecube.o 121 121 obj-$(CONFIG_RTC_DRV_NCT3018Y) += rtc-nct3018y.o 122 122 + obj-$(CONFIG_RTC_DRV_NCT6694) += rtc-nct6694.o 122 123 obj-$(CONFIG_RTC_DRV_NTXEC) += rtc-ntxec.o 123 124 obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o 124 125 obj-$(CONFIG_RTC_DRV_OPAL) += rtc-opal.o

+297

drivers/rtc/rtc-nct6694.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Nuvoton NCT6694 RTC driver based on USB interface. 4 4 + * 5 5 + * Copyright (C) 2025 Nuvoton Technology Corp. 6 6 + */ 7 7 + 8 8 + #include <linux/bcd.h> 9 9 + #include <linux/irqdomain.h> 10 10 + #include <linux/kernel.h> 11 11 + #include <linux/mfd/nct6694.h> 12 12 + #include <linux/module.h> 13 13 + #include <linux/platform_device.h> 14 14 + #include <linux/rtc.h> 15 15 + #include <linux/slab.h> 16 16 + 17 17 + /* 18 18 + * USB command module type for NCT6694 RTC controller. 19 19 + * This defines the module type used for communication with the NCT6694 20 20 + * RTC controller over the USB interface. 21 21 + */ 22 22 + #define NCT6694_RTC_MOD 0x08 23 23 + 24 24 + /* Command 00h - RTC Time */ 25 25 + #define NCT6694_RTC_TIME 0x0000 26 26 + #define NCT6694_RTC_TIME_SEL 0x00 27 27 + 28 28 + /* Command 01h - RTC Alarm */ 29 29 + #define NCT6694_RTC_ALARM 0x01 30 30 + #define NCT6694_RTC_ALARM_SEL 0x00 31 31 + 32 32 + /* Command 02h - RTC Status */ 33 33 + #define NCT6694_RTC_STATUS 0x02 34 34 + #define NCT6694_RTC_STATUS_SEL 0x00 35 35 + 36 36 + #define NCT6694_RTC_IRQ_INT_EN BIT(0) /* Transmit a USB INT-in when RTC alarm */ 37 37 + #define NCT6694_RTC_IRQ_GPO_EN BIT(5) /* Trigger a GPO Low Pulse when RTC alarm */ 38 38 + 39 39 + #define NCT6694_RTC_IRQ_EN (NCT6694_RTC_IRQ_INT_EN | NCT6694_RTC_IRQ_GPO_EN) 40 40 + #define NCT6694_RTC_IRQ_STS BIT(0) /* Write 1 clear IRQ status */ 41 41 + 42 42 + struct __packed nct6694_rtc_time { 43 43 + u8 sec; 44 44 + u8 min; 45 45 + u8 hour; 46 46 + u8 week; 47 47 + u8 day; 48 48 + u8 month; 49 49 + u8 year; 50 50 + }; 51 51 + 52 52 + struct __packed nct6694_rtc_alarm { 53 53 + u8 sec; 54 54 + u8 min; 55 55 + u8 hour; 56 56 + u8 alarm_en; 57 57 + u8 alarm_pend; 58 58 + }; 59 59 + 60 60 + struct __packed nct6694_rtc_status { 61 61 + u8 irq_en; 62 62 + u8 irq_pend; 63 63 + }; 64 64 + 65 65 + union __packed nct6694_rtc_msg { 66 66 + struct nct6694_rtc_time time; 67 67 + struct nct6694_rtc_alarm alarm; 68 68 + struct nct6694_rtc_status sts; 69 69 + }; 70 70 + 71 71 + struct nct6694_rtc_data { 72 72 + struct nct6694 *nct6694; 73 73 + struct rtc_device *rtc; 74 74 + union nct6694_rtc_msg *msg; 75 75 + int irq; 76 76 + }; 77 77 + 78 78 + static int nct6694_rtc_read_time(struct device *dev, struct rtc_time *tm) 79 79 + { 80 80 + struct nct6694_rtc_data *data = dev_get_drvdata(dev); 81 81 + struct nct6694_rtc_time *time = &data->msg->time; 82 82 + static const struct nct6694_cmd_header cmd_hd = { 83 83 + .mod = NCT6694_RTC_MOD, 84 84 + .cmd = NCT6694_RTC_TIME, 85 85 + .sel = NCT6694_RTC_TIME_SEL, 86 86 + .len = cpu_to_le16(sizeof(*time)) 87 87 + }; 88 88 + int ret; 89 89 + 90 90 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, time); 91 91 + if (ret) 92 92 + return ret; 93 93 + 94 94 + tm->tm_sec = bcd2bin(time->sec); /* tm_sec expect 0 ~ 59 */ 95 95 + tm->tm_min = bcd2bin(time->min); /* tm_min expect 0 ~ 59 */ 96 96 + tm->tm_hour = bcd2bin(time->hour); /* tm_hour expect 0 ~ 23 */ 97 97 + tm->tm_wday = bcd2bin(time->week) - 1; /* tm_wday expect 0 ~ 6 */ 98 98 + tm->tm_mday = bcd2bin(time->day); /* tm_mday expect 1 ~ 31 */ 99 99 + tm->tm_mon = bcd2bin(time->month) - 1; /* tm_month expect 0 ~ 11 */ 100 100 + tm->tm_year = bcd2bin(time->year) + 100; /* tm_year expect since 1900 */ 101 101 + 102 102 + return ret; 103 103 + } 104 104 + 105 105 + static int nct6694_rtc_set_time(struct device *dev, struct rtc_time *tm) 106 106 + { 107 107 + struct nct6694_rtc_data *data = dev_get_drvdata(dev); 108 108 + struct nct6694_rtc_time *time = &data->msg->time; 109 109 + static const struct nct6694_cmd_header cmd_hd = { 110 110 + .mod = NCT6694_RTC_MOD, 111 111 + .cmd = NCT6694_RTC_TIME, 112 112 + .sel = NCT6694_RTC_TIME_SEL, 113 113 + .len = cpu_to_le16(sizeof(*time)) 114 114 + }; 115 115 + 116 116 + time->sec = bin2bcd(tm->tm_sec); 117 117 + time->min = bin2bcd(tm->tm_min); 118 118 + time->hour = bin2bcd(tm->tm_hour); 119 119 + time->week = bin2bcd(tm->tm_wday + 1); 120 120 + time->day = bin2bcd(tm->tm_mday); 121 121 + time->month = bin2bcd(tm->tm_mon + 1); 122 122 + time->year = bin2bcd(tm->tm_year - 100); 123 123 + 124 124 + return nct6694_write_msg(data->nct6694, &cmd_hd, time); 125 125 + } 126 126 + 127 127 + static int nct6694_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 128 128 + { 129 129 + struct nct6694_rtc_data *data = dev_get_drvdata(dev); 130 130 + struct nct6694_rtc_alarm *alarm = &data->msg->alarm; 131 131 + static const struct nct6694_cmd_header cmd_hd = { 132 132 + .mod = NCT6694_RTC_MOD, 133 133 + .cmd = NCT6694_RTC_ALARM, 134 134 + .sel = NCT6694_RTC_ALARM_SEL, 135 135 + .len = cpu_to_le16(sizeof(*alarm)) 136 136 + }; 137 137 + int ret; 138 138 + 139 139 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, alarm); 140 140 + if (ret) 141 141 + return ret; 142 142 + 143 143 + alrm->time.tm_sec = bcd2bin(alarm->sec); 144 144 + alrm->time.tm_min = bcd2bin(alarm->min); 145 145 + alrm->time.tm_hour = bcd2bin(alarm->hour); 146 146 + alrm->enabled = alarm->alarm_en; 147 147 + alrm->pending = alarm->alarm_pend; 148 148 + 149 149 + return ret; 150 150 + } 151 151 + 152 152 + static int nct6694_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 153 153 + { 154 154 + struct nct6694_rtc_data *data = dev_get_drvdata(dev); 155 155 + struct nct6694_rtc_alarm *alarm = &data->msg->alarm; 156 156 + static const struct nct6694_cmd_header cmd_hd = { 157 157 + .mod = NCT6694_RTC_MOD, 158 158 + .cmd = NCT6694_RTC_ALARM, 159 159 + .sel = NCT6694_RTC_ALARM_SEL, 160 160 + .len = cpu_to_le16(sizeof(*alarm)) 161 161 + }; 162 162 + 163 163 + alarm->sec = bin2bcd(alrm->time.tm_sec); 164 164 + alarm->min = bin2bcd(alrm->time.tm_min); 165 165 + alarm->hour = bin2bcd(alrm->time.tm_hour); 166 166 + alarm->alarm_en = alrm->enabled ? NCT6694_RTC_IRQ_EN : 0; 167 167 + alarm->alarm_pend = 0; 168 168 + 169 169 + return nct6694_write_msg(data->nct6694, &cmd_hd, alarm); 170 170 + } 171 171 + 172 172 + static int nct6694_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 173 173 + { 174 174 + struct nct6694_rtc_data *data = dev_get_drvdata(dev); 175 175 + struct nct6694_rtc_status *sts = &data->msg->sts; 176 176 + static const struct nct6694_cmd_header cmd_hd = { 177 177 + .mod = NCT6694_RTC_MOD, 178 178 + .cmd = NCT6694_RTC_STATUS, 179 179 + .sel = NCT6694_RTC_STATUS_SEL, 180 180 + .len = cpu_to_le16(sizeof(*sts)) 181 181 + }; 182 182 + 183 183 + if (enabled) 184 184 + sts->irq_en |= NCT6694_RTC_IRQ_EN; 185 185 + else 186 186 + sts->irq_en &= ~NCT6694_RTC_IRQ_EN; 187 187 + 188 188 + sts->irq_pend = 0; 189 189 + 190 190 + return nct6694_write_msg(data->nct6694, &cmd_hd, sts); 191 191 + } 192 192 + 193 193 + static const struct rtc_class_ops nct6694_rtc_ops = { 194 194 + .read_time = nct6694_rtc_read_time, 195 195 + .set_time = nct6694_rtc_set_time, 196 196 + .read_alarm = nct6694_rtc_read_alarm, 197 197 + .set_alarm = nct6694_rtc_set_alarm, 198 198 + .alarm_irq_enable = nct6694_rtc_alarm_irq_enable, 199 199 + }; 200 200 + 201 201 + static irqreturn_t nct6694_irq(int irq, void *dev_id) 202 202 + { 203 203 + struct nct6694_rtc_data *data = dev_id; 204 204 + struct nct6694_rtc_status *sts = &data->msg->sts; 205 205 + static const struct nct6694_cmd_header cmd_hd = { 206 206 + .mod = NCT6694_RTC_MOD, 207 207 + .cmd = NCT6694_RTC_STATUS, 208 208 + .sel = NCT6694_RTC_STATUS_SEL, 209 209 + .len = cpu_to_le16(sizeof(*sts)) 210 210 + }; 211 211 + int ret; 212 212 + 213 213 + rtc_lock(data->rtc); 214 214 + 215 215 + sts->irq_en = NCT6694_RTC_IRQ_EN; 216 216 + sts->irq_pend = NCT6694_RTC_IRQ_STS; 217 217 + ret = nct6694_write_msg(data->nct6694, &cmd_hd, sts); 218 218 + if (ret) { 219 219 + rtc_unlock(data->rtc); 220 220 + return IRQ_NONE; 221 221 + } 222 222 + 223 223 + rtc_update_irq(data->rtc, 1, RTC_IRQF | RTC_AF); 224 224 + 225 225 + rtc_unlock(data->rtc); 226 226 + 227 227 + return IRQ_HANDLED; 228 228 + } 229 229 + 230 230 + static void nct6694_irq_dispose_mapping(void *d) 231 231 + { 232 232 + struct nct6694_rtc_data *data = d; 233 233 + 234 234 + irq_dispose_mapping(data->irq); 235 235 + } 236 236 + 237 237 + static int nct6694_rtc_probe(struct platform_device *pdev) 238 238 + { 239 239 + struct nct6694_rtc_data *data; 240 240 + struct nct6694 *nct6694 = dev_get_drvdata(pdev->dev.parent); 241 241 + int ret; 242 242 + 243 243 + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 244 244 + if (!data) 245 245 + return -ENOMEM; 246 246 + 247 247 + data->msg = devm_kzalloc(&pdev->dev, sizeof(union nct6694_rtc_msg), 248 248 + GFP_KERNEL); 249 249 + if (!data->msg) 250 250 + return -ENOMEM; 251 251 + 252 252 + data->irq = irq_create_mapping(nct6694->domain, NCT6694_IRQ_RTC); 253 253 + if (!data->irq) 254 254 + return -EINVAL; 255 255 + 256 256 + ret = devm_add_action_or_reset(&pdev->dev, nct6694_irq_dispose_mapping, 257 257 + data); 258 258 + if (ret) 259 259 + return ret; 260 260 + 261 261 + ret = devm_device_init_wakeup(&pdev->dev); 262 262 + if (ret) 263 263 + return dev_err_probe(&pdev->dev, ret, "Failed to init wakeup\n"); 264 264 + 265 265 + data->rtc = devm_rtc_allocate_device(&pdev->dev); 266 266 + if (IS_ERR(data->rtc)) 267 267 + return PTR_ERR(data->rtc); 268 268 + 269 269 + data->nct6694 = nct6694; 270 270 + data->rtc->ops = &nct6694_rtc_ops; 271 271 + data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 272 272 + data->rtc->range_max = RTC_TIMESTAMP_END_2099; 273 273 + 274 274 + platform_set_drvdata(pdev, data); 275 275 + 276 276 + ret = devm_request_threaded_irq(&pdev->dev, data->irq, NULL, 277 277 + nct6694_irq, IRQF_ONESHOT, 278 278 + "rtc-nct6694", data); 279 279 + if (ret < 0) 280 280 + return dev_err_probe(&pdev->dev, ret, "Failed to request irq\n"); 281 281 + 282 282 + return devm_rtc_register_device(data->rtc); 283 283 + } 284 284 + 285 285 + static struct platform_driver nct6694_rtc_driver = { 286 286 + .driver = { 287 287 + .name = "nct6694-rtc", 288 288 + }, 289 289 + .probe = nct6694_rtc_probe, 290 290 + }; 291 291 + 292 292 + module_platform_driver(nct6694_rtc_driver); 293 293 + 294 294 + MODULE_DESCRIPTION("USB-RTC driver for NCT6694"); 295 295 + MODULE_AUTHOR("Ming Yu <tmyu0@nuvoton.com>"); 296 296 + MODULE_LICENSE("GPL"); 297 297 + MODULE_ALIAS("platform:nct6694-rtc");

+11

drivers/watchdog/Kconfig

reviewed

··· 760 760 MAX77620 chips. To compile this driver as a module, 761 761 choose M here: the module will be called max77620_wdt. 762 762 763 763 + config NCT6694_WATCHDOG 764 764 + tristate "Nuvoton NCT6694 watchdog support" 765 765 + depends on MFD_NCT6694 766 766 + select WATCHDOG_CORE 767 767 + help 768 768 + Say Y here to support Nuvoton NCT6694 watchdog timer 769 769 + functionality. 770 770 + 771 771 + This driver can also be built as a module. If so, the module 772 772 + will be called nct6694_wdt. 773 773 + 763 774 config IMX2_WDT 764 775 tristate "IMX2+ Watchdog" 765 776 depends on ARCH_MXC || ARCH_LAYERSCAPE || COMPILE_TEST

+1

drivers/watchdog/Makefile

reviewed

··· 235 235 obj-$(CONFIG_WM8350_WATCHDOG) += wm8350_wdt.o 236 236 obj-$(CONFIG_MAX63XX_WATCHDOG) += max63xx_wdt.o 237 237 obj-$(CONFIG_MAX77620_WATCHDOG) += max77620_wdt.o 238 238 + obj-$(CONFIG_NCT6694_WATCHDOG) += nct6694_wdt.o 238 239 obj-$(CONFIG_ZIIRAVE_WATCHDOG) += ziirave_wdt.o 239 240 obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o 240 241 obj-$(CONFIG_MENF21BMC_WATCHDOG) += menf21bmc_wdt.o

+307

drivers/watchdog/nct6694_wdt.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Nuvoton NCT6694 WDT driver based on USB interface. 4 4 + * 5 5 + * Copyright (C) 2025 Nuvoton Technology Corp. 6 6 + */ 7 7 + 8 8 + #include <linux/idr.h> 9 9 + #include <linux/kernel.h> 10 10 + #include <linux/mfd/nct6694.h> 11 11 + #include <linux/module.h> 12 12 + #include <linux/platform_device.h> 13 13 + #include <linux/slab.h> 14 14 + #include <linux/watchdog.h> 15 15 + 16 16 + #define DEVICE_NAME "nct6694-wdt" 17 17 + 18 18 + #define NCT6694_DEFAULT_TIMEOUT 10 19 19 + #define NCT6694_DEFAULT_PRETIMEOUT 0 20 20 + 21 21 + #define NCT6694_WDT_MAX_DEVS 2 22 22 + 23 23 + /* 24 24 + * USB command module type for NCT6694 WDT controller. 25 25 + * This defines the module type used for communication with the NCT6694 26 26 + * WDT controller over the USB interface. 27 27 + */ 28 28 + #define NCT6694_WDT_MOD 0x07 29 29 + 30 30 + /* Command 00h - WDT Setup */ 31 31 + #define NCT6694_WDT_SETUP 0x00 32 32 + #define NCT6694_WDT_SETUP_SEL(idx) (idx ? 0x01 : 0x00) 33 33 + 34 34 + /* Command 01h - WDT Command */ 35 35 + #define NCT6694_WDT_COMMAND 0x01 36 36 + #define NCT6694_WDT_COMMAND_SEL(idx) (idx ? 0x01 : 0x00) 37 37 + 38 38 + static unsigned int timeout[NCT6694_WDT_MAX_DEVS] = { 39 39 + [0 ... (NCT6694_WDT_MAX_DEVS - 1)] = NCT6694_DEFAULT_TIMEOUT 40 40 + }; 41 41 + module_param_array(timeout, int, NULL, 0644); 42 42 + MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds"); 43 43 + 44 44 + static unsigned int pretimeout[NCT6694_WDT_MAX_DEVS] = { 45 45 + [0 ... (NCT6694_WDT_MAX_DEVS - 1)] = NCT6694_DEFAULT_PRETIMEOUT 46 46 + }; 47 47 + module_param_array(pretimeout, int, NULL, 0644); 48 48 + MODULE_PARM_DESC(pretimeout, "Watchdog pre-timeout in seconds"); 49 49 + 50 50 + static bool nowayout = WATCHDOG_NOWAYOUT; 51 51 + module_param(nowayout, bool, 0); 52 52 + MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 53 53 + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 54 54 + 55 55 + enum { 56 56 + NCT6694_ACTION_NONE = 0, 57 57 + NCT6694_ACTION_SIRQ, 58 58 + NCT6694_ACTION_GPO, 59 59 + }; 60 60 + 61 61 + struct __packed nct6694_wdt_setup { 62 62 + __le32 pretimeout; 63 63 + __le32 timeout; 64 64 + u8 owner; 65 65 + u8 scratch; 66 66 + u8 control; 67 67 + u8 status; 68 68 + __le32 countdown; 69 69 + }; 70 70 + 71 71 + struct __packed nct6694_wdt_cmd { 72 72 + __le32 wdt_cmd; 73 73 + __le32 reserved; 74 74 + }; 75 75 + 76 76 + union __packed nct6694_wdt_msg { 77 77 + struct nct6694_wdt_setup setup; 78 78 + struct nct6694_wdt_cmd cmd; 79 79 + }; 80 80 + 81 81 + struct nct6694_wdt_data { 82 82 + struct watchdog_device wdev; 83 83 + struct device *dev; 84 84 + struct nct6694 *nct6694; 85 85 + union nct6694_wdt_msg *msg; 86 86 + unsigned char wdev_idx; 87 87 + }; 88 88 + 89 89 + static int nct6694_wdt_setting(struct watchdog_device *wdev, 90 90 + u32 timeout_val, u8 timeout_act, 91 91 + u32 pretimeout_val, u8 pretimeout_act) 92 92 + { 93 93 + struct nct6694_wdt_data *data = watchdog_get_drvdata(wdev); 94 94 + struct nct6694_wdt_setup *setup = &data->msg->setup; 95 95 + const struct nct6694_cmd_header cmd_hd = { 96 96 + .mod = NCT6694_WDT_MOD, 97 97 + .cmd = NCT6694_WDT_SETUP, 98 98 + .sel = NCT6694_WDT_SETUP_SEL(data->wdev_idx), 99 99 + .len = cpu_to_le16(sizeof(*setup)) 100 100 + }; 101 101 + unsigned int timeout_fmt, pretimeout_fmt; 102 102 + 103 103 + if (pretimeout_val == 0) 104 104 + pretimeout_act = NCT6694_ACTION_NONE; 105 105 + 106 106 + timeout_fmt = (timeout_val * 1000) | (timeout_act << 24); 107 107 + pretimeout_fmt = (pretimeout_val * 1000) | (pretimeout_act << 24); 108 108 + 109 109 + memset(setup, 0, sizeof(*setup)); 110 110 + setup->timeout = cpu_to_le32(timeout_fmt); 111 111 + setup->pretimeout = cpu_to_le32(pretimeout_fmt); 112 112 + 113 113 + return nct6694_write_msg(data->nct6694, &cmd_hd, setup); 114 114 + } 115 115 + 116 116 + static int nct6694_wdt_start(struct watchdog_device *wdev) 117 117 + { 118 118 + struct nct6694_wdt_data *data = watchdog_get_drvdata(wdev); 119 119 + int ret; 120 120 + 121 121 + ret = nct6694_wdt_setting(wdev, wdev->timeout, NCT6694_ACTION_GPO, 122 122 + wdev->pretimeout, NCT6694_ACTION_GPO); 123 123 + if (ret) 124 124 + return ret; 125 125 + 126 126 + dev_dbg(data->dev, "Setting WDT(%d): timeout = %d, pretimeout = %d\n", 127 127 + data->wdev_idx, wdev->timeout, wdev->pretimeout); 128 128 + 129 129 + return ret; 130 130 + } 131 131 + 132 132 + static int nct6694_wdt_stop(struct watchdog_device *wdev) 133 133 + { 134 134 + struct nct6694_wdt_data *data = watchdog_get_drvdata(wdev); 135 135 + struct nct6694_wdt_cmd *cmd = &data->msg->cmd; 136 136 + const struct nct6694_cmd_header cmd_hd = { 137 137 + .mod = NCT6694_WDT_MOD, 138 138 + .cmd = NCT6694_WDT_COMMAND, 139 139 + .sel = NCT6694_WDT_COMMAND_SEL(data->wdev_idx), 140 140 + .len = cpu_to_le16(sizeof(*cmd)) 141 141 + }; 142 142 + 143 143 + memcpy(&cmd->wdt_cmd, "WDTC", 4); 144 144 + cmd->reserved = 0; 145 145 + 146 146 + return nct6694_write_msg(data->nct6694, &cmd_hd, cmd); 147 147 + } 148 148 + 149 149 + static int nct6694_wdt_ping(struct watchdog_device *wdev) 150 150 + { 151 151 + struct nct6694_wdt_data *data = watchdog_get_drvdata(wdev); 152 152 + struct nct6694_wdt_cmd *cmd = &data->msg->cmd; 153 153 + const struct nct6694_cmd_header cmd_hd = { 154 154 + .mod = NCT6694_WDT_MOD, 155 155 + .cmd = NCT6694_WDT_COMMAND, 156 156 + .sel = NCT6694_WDT_COMMAND_SEL(data->wdev_idx), 157 157 + .len = cpu_to_le16(sizeof(*cmd)) 158 158 + }; 159 159 + 160 160 + memcpy(&cmd->wdt_cmd, "WDTS", 4); 161 161 + cmd->reserved = 0; 162 162 + 163 163 + return nct6694_write_msg(data->nct6694, &cmd_hd, cmd); 164 164 + } 165 165 + 166 166 + static int nct6694_wdt_set_timeout(struct watchdog_device *wdev, 167 167 + unsigned int new_timeout) 168 168 + { 169 169 + int ret; 170 170 + 171 171 + ret = nct6694_wdt_setting(wdev, new_timeout, NCT6694_ACTION_GPO, 172 172 + wdev->pretimeout, NCT6694_ACTION_GPO); 173 173 + if (ret) 174 174 + return ret; 175 175 + 176 176 + wdev->timeout = new_timeout; 177 177 + 178 178 + return 0; 179 179 + } 180 180 + 181 181 + static int nct6694_wdt_set_pretimeout(struct watchdog_device *wdev, 182 182 + unsigned int new_pretimeout) 183 183 + { 184 184 + int ret; 185 185 + 186 186 + ret = nct6694_wdt_setting(wdev, wdev->timeout, NCT6694_ACTION_GPO, 187 187 + new_pretimeout, NCT6694_ACTION_GPO); 188 188 + if (ret) 189 189 + return ret; 190 190 + 191 191 + wdev->pretimeout = new_pretimeout; 192 192 + 193 193 + return 0; 194 194 + } 195 195 + 196 196 + static unsigned int nct6694_wdt_get_time(struct watchdog_device *wdev) 197 197 + { 198 198 + struct nct6694_wdt_data *data = watchdog_get_drvdata(wdev); 199 199 + struct nct6694_wdt_setup *setup = &data->msg->setup; 200 200 + const struct nct6694_cmd_header cmd_hd = { 201 201 + .mod = NCT6694_WDT_MOD, 202 202 + .cmd = NCT6694_WDT_SETUP, 203 203 + .sel = NCT6694_WDT_SETUP_SEL(data->wdev_idx), 204 204 + .len = cpu_to_le16(sizeof(*setup)) 205 205 + }; 206 206 + unsigned int timeleft_ms; 207 207 + int ret; 208 208 + 209 209 + ret = nct6694_read_msg(data->nct6694, &cmd_hd, setup); 210 210 + if (ret) 211 211 + return 0; 212 212 + 213 213 + timeleft_ms = le32_to_cpu(setup->countdown); 214 214 + 215 215 + return timeleft_ms / 1000; 216 216 + } 217 217 + 218 218 + static const struct watchdog_info nct6694_wdt_info = { 219 219 + .options = WDIOF_SETTIMEOUT | 220 220 + WDIOF_KEEPALIVEPING | 221 221 + WDIOF_MAGICCLOSE | 222 222 + WDIOF_PRETIMEOUT, 223 223 + .identity = DEVICE_NAME, 224 224 + }; 225 225 + 226 226 + static const struct watchdog_ops nct6694_wdt_ops = { 227 227 + .owner = THIS_MODULE, 228 228 + .start = nct6694_wdt_start, 229 229 + .stop = nct6694_wdt_stop, 230 230 + .set_timeout = nct6694_wdt_set_timeout, 231 231 + .set_pretimeout = nct6694_wdt_set_pretimeout, 232 232 + .get_timeleft = nct6694_wdt_get_time, 233 233 + .ping = nct6694_wdt_ping, 234 234 + }; 235 235 + 236 236 + static void nct6694_wdt_ida_free(void *d) 237 237 + { 238 238 + struct nct6694_wdt_data *data = d; 239 239 + struct nct6694 *nct6694 = data->nct6694; 240 240 + 241 241 + ida_free(&nct6694->wdt_ida, data->wdev_idx); 242 242 + } 243 243 + 244 244 + static int nct6694_wdt_probe(struct platform_device *pdev) 245 245 + { 246 246 + struct device *dev = &pdev->dev; 247 247 + struct nct6694 *nct6694 = dev_get_drvdata(dev->parent); 248 248 + struct nct6694_wdt_data *data; 249 249 + struct watchdog_device *wdev; 250 250 + int ret; 251 251 + 252 252 + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 253 253 + if (!data) 254 254 + return -ENOMEM; 255 255 + 256 256 + data->msg = devm_kzalloc(dev, sizeof(union nct6694_wdt_msg), 257 257 + GFP_KERNEL); 258 258 + if (!data->msg) 259 259 + return -ENOMEM; 260 260 + 261 261 + data->dev = dev; 262 262 + data->nct6694 = nct6694; 263 263 + 264 264 + ret = ida_alloc(&nct6694->wdt_ida, GFP_KERNEL); 265 265 + if (ret < 0) 266 266 + return ret; 267 267 + data->wdev_idx = ret; 268 268 + 269 269 + ret = devm_add_action_or_reset(dev, nct6694_wdt_ida_free, data); 270 270 + if (ret) 271 271 + return ret; 272 272 + 273 273 + wdev = &data->wdev; 274 274 + wdev->info = &nct6694_wdt_info; 275 275 + wdev->ops = &nct6694_wdt_ops; 276 276 + wdev->timeout = timeout[data->wdev_idx]; 277 277 + wdev->pretimeout = pretimeout[data->wdev_idx]; 278 278 + if (timeout[data->wdev_idx] < pretimeout[data->wdev_idx]) { 279 279 + dev_warn(data->dev, "pretimeout < timeout. Setting to zero\n"); 280 280 + wdev->pretimeout = 0; 281 281 + } 282 282 + 283 283 + wdev->min_timeout = 1; 284 284 + wdev->max_timeout = 255; 285 285 + 286 286 + platform_set_drvdata(pdev, data); 287 287 + 288 288 + watchdog_set_drvdata(&data->wdev, data); 289 289 + watchdog_set_nowayout(&data->wdev, nowayout); 290 290 + watchdog_stop_on_reboot(&data->wdev); 291 291 + 292 292 + return devm_watchdog_register_device(dev, &data->wdev); 293 293 + } 294 294 + 295 295 + static struct platform_driver nct6694_wdt_driver = { 296 296 + .driver = { 297 297 + .name = DEVICE_NAME, 298 298 + }, 299 299 + .probe = nct6694_wdt_probe, 300 300 + }; 301 301 + 302 302 + module_platform_driver(nct6694_wdt_driver); 303 303 + 304 304 + MODULE_DESCRIPTION("USB-WDT driver for NCT6694"); 305 305 + MODULE_AUTHOR("Ming Yu <tmyu0@nuvoton.com>"); 306 306 + MODULE_LICENSE("GPL"); 307 307 + MODULE_ALIAS("platform:nct6694-wdt");

+28

include/dt-bindings/gpio/tegra256-gpio.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 3 3 + 4 4 + /* 5 5 + * This header provides constants for the nvidia,tegra256-gpio DT binding. 6 6 + * 7 7 + * The first cell in Tegra's GPIO specifier is the GPIO ID. 8 8 + * The macros below provide names for this. 9 9 + * 10 10 + * The second cell contains standard flag values specified in gpio.h. 11 11 + */ 12 12 + 13 13 + #ifndef _DT_BINDINGS_GPIO_TEGRA256_GPIO_H 14 14 + #define _DT_BINDINGS_GPIO_TEGRA256_GPIO_H 15 15 + 16 16 + #include <dt-bindings/gpio/gpio.h> 17 17 + 18 18 + /* GPIOs implemented by main GPIO controller */ 19 19 + #define TEGRA256_MAIN_GPIO_PORT_A 0 20 20 + #define TEGRA256_MAIN_GPIO_PORT_B 1 21 21 + #define TEGRA256_MAIN_GPIO_PORT_C 2 22 22 + #define TEGRA256_MAIN_GPIO_PORT_D 3 23 23 + 24 24 + #define TEGRA256_MAIN_GPIO(port, offset) \ 25 25 + ((TEGRA256_MAIN_GPIO_PORT_##port * 8) + (offset)) 26 26 + 27 27 + #endif 28 28 +

+48 -57

include/linux/gpio/driver.h

reviewed

··· 388 388 * implies that if the chip supports IRQs, these IRQs need to be threaded 389 389 * as the chip access may sleep when e.g. reading out the IRQ status 390 390 * registers. 391 391 - * @read_reg: reader function for generic GPIO 392 392 - * @write_reg: writer function for generic GPIO 393 393 - * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 394 394 - * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 395 395 - * generic GPIO core. It is for internal housekeeping only. 396 396 - * @reg_dat: data (in) register for generic GPIO 397 397 - * @reg_set: output set register (out=high) for generic GPIO 398 398 - * @reg_clr: output clear register (out=low) for generic GPIO 399 399 - * @reg_dir_out: direction out setting register for generic GPIO 400 400 - * @reg_dir_in: direction in setting register for generic GPIO 401 401 - * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 402 402 - * be read and we need to rely on out internal state tracking. 403 403 - * @bgpio_pinctrl: the generic GPIO uses a pin control backend. 404 404 - * @bgpio_bits: number of register bits used for a generic GPIO i.e. 405 405 - * <register width> * 8 406 406 - * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 407 407 - * shadowed and real data registers writes together. 408 408 - * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 409 409 - * safely. 410 410 - * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 411 411 - * direction safely. A "1" in this word means the line is set as 412 412 - * output. 413 391 * 414 392 * A gpio_chip can help platforms abstract various sources of GPIOs so 415 393 * they can all be accessed through a common programming interface. ··· 452 474 u16 offset; 453 475 const char *const *names; 454 476 bool can_sleep; 455 455 - 456 456 - #if IS_ENABLED(CONFIG_GPIO_GENERIC) 457 457 - unsigned long (*read_reg)(void __iomem *reg); 458 458 - void (*write_reg)(void __iomem *reg, unsigned long data); 459 459 - bool be_bits; 460 460 - void __iomem *reg_dat; 461 461 - void __iomem *reg_set; 462 462 - void __iomem *reg_clr; 463 463 - void __iomem *reg_dir_out; 464 464 - void __iomem *reg_dir_in; 465 465 - bool bgpio_dir_unreadable; 466 466 - bool bgpio_pinctrl; 467 467 - int bgpio_bits; 468 468 - raw_spinlock_t bgpio_lock; 469 469 - unsigned long bgpio_data; 470 470 - unsigned long bgpio_dir; 471 471 - #endif /* CONFIG_GPIO_GENERIC */ 472 477 473 478 #ifdef CONFIG_GPIOLIB_IRQCHIP 474 479 /* ··· 684 723 685 724 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 686 725 687 687 - int bgpio_init(struct gpio_chip *gc, struct device *dev, 688 688 - unsigned long sz, void __iomem *dat, void __iomem *set, 689 689 - void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 690 690 - unsigned long flags); 691 691 - 692 692 - #define BGPIOF_BIG_ENDIAN BIT(0) 693 693 - #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 694 694 - #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 695 695 - #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 696 696 - #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 697 697 - #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 698 698 - #define BGPIOF_NO_SET_ON_INPUT BIT(6) 699 699 - #define BGPIOF_PINCTRL_BACKEND BIT(7) /* Call pinctrl direction setters */ 700 700 - #define BGPIOF_NO_INPUT BIT(8) /* only output */ 701 701 - 702 726 #ifdef CONFIG_GPIOLIB_IRQCHIP 703 727 int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 704 728 struct irq_domain *domain); ··· 718 772 719 773 #ifdef CONFIG_PINCTRL 720 774 721 721 - int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 722 722 - unsigned int gpio_offset, unsigned int pin_offset, 723 723 - unsigned int npins); 775 775 + int gpiochip_add_pin_range_with_pins(struct gpio_chip *gc, 776 776 + const char *pinctl_name, 777 777 + unsigned int gpio_offset, 778 778 + unsigned int pin_offset, 779 779 + unsigned int const *pins, 780 780 + unsigned int npins); 724 781 int gpiochip_add_pingroup_range(struct gpio_chip *gc, 725 782 struct pinctrl_dev *pctldev, 726 783 unsigned int gpio_offset, const char *pin_group); 727 784 void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 728 785 786 786 + static inline int 787 787 + gpiochip_add_pin_range(struct gpio_chip *gc, 788 788 + const char *pinctl_name, 789 789 + unsigned int gpio_offset, 790 790 + unsigned int pin_offset, 791 791 + unsigned int npins) 792 792 + { 793 793 + return gpiochip_add_pin_range_with_pins(gc, pinctl_name, gpio_offset, 794 794 + pin_offset, NULL, npins); 795 795 + } 796 796 + 797 797 + static inline int 798 798 + gpiochip_add_sparse_pin_range(struct gpio_chip *gc, 799 799 + const char *pinctl_name, 800 800 + unsigned int gpio_offset, 801 801 + unsigned int const *pins, 802 802 + unsigned int npins) 803 803 + { 804 804 + return gpiochip_add_pin_range_with_pins(gc, pinctl_name, gpio_offset, 0, 805 805 + pins, npins); 806 806 + } 729 807 #else /* ! CONFIG_PINCTRL */ 808 808 + 809 809 + static inline int 810 810 + gpiochip_add_pin_range_with_pins(struct gpio_chip *gc, 811 811 + const char *pinctl_name, 812 812 + unsigned int gpio_offset, 813 813 + unsigned int pin_offset, 814 814 + unsigned int npins) 815 815 + { 816 816 + return 0; 817 817 + } 730 818 731 819 static inline int 732 820 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, ··· 769 789 { 770 790 return 0; 771 791 } 792 792 + 793 793 + static inline int 794 794 + gpiochip_add_sparse_pin_range(struct gpio_chip *gc, 795 795 + const char *pinctl_name, 796 796 + unsigned int gpio_offset, 797 797 + unsigned int const *pins, 798 798 + unsigned int npins) 799 799 + { 800 800 + return 0; 801 801 + } 802 802 + 772 803 static inline int 773 804 gpiochip_add_pingroup_range(struct gpio_chip *gc, 774 805 struct pinctrl_dev *pctldev,

+41

include/linux/gpio/forwarder.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + #ifndef __LINUX_GPIO_FORWARDER_H 3 3 + #define __LINUX_GPIO_FORWARDER_H 4 4 + 5 5 + struct gpio_desc; 6 6 + struct gpio_chip; 7 7 + struct gpiochip_fwd; 8 8 + 9 9 + struct gpiochip_fwd *devm_gpiochip_fwd_alloc(struct device *dev, 10 10 + unsigned int ngpios); 11 11 + int gpiochip_fwd_desc_add(struct gpiochip_fwd *fwd, 12 12 + struct gpio_desc *desc, unsigned int offset); 13 13 + void gpiochip_fwd_desc_free(struct gpiochip_fwd *fwd, unsigned int offset); 14 14 + int gpiochip_fwd_register(struct gpiochip_fwd *fwd, void *data); 15 15 + 16 16 + struct gpio_chip *gpiochip_fwd_get_gpiochip(struct gpiochip_fwd *fwd); 17 17 + 18 18 + void *gpiochip_fwd_get_data(struct gpiochip_fwd *fwd); 19 19 + 20 20 + int gpiochip_fwd_gpio_request(struct gpiochip_fwd *fwd, unsigned int offset); 21 21 + int gpiochip_fwd_gpio_get_direction(struct gpiochip_fwd *fwd, 22 22 + unsigned int offset); 23 23 + int gpiochip_fwd_gpio_direction_input(struct gpiochip_fwd *fwd, 24 24 + unsigned int offset); 25 25 + int gpiochip_fwd_gpio_direction_output(struct gpiochip_fwd *fwd, 26 26 + unsigned int offset, 27 27 + int value); 28 28 + int gpiochip_fwd_gpio_get(struct gpiochip_fwd *fwd, unsigned int offset); 29 29 + int gpiochip_fwd_gpio_get_multiple(struct gpiochip_fwd *fwd, 30 30 + unsigned long *mask, 31 31 + unsigned long *bits); 32 32 + int gpiochip_fwd_gpio_set(struct gpiochip_fwd *fwd, unsigned int offset, 33 33 + int value); 34 34 + int gpiochip_fwd_gpio_set_multiple(struct gpiochip_fwd *fwd, 35 35 + unsigned long *mask, 36 36 + unsigned long *bits); 37 37 + int gpiochip_fwd_gpio_set_config(struct gpiochip_fwd *fwd, unsigned int offset, 38 38 + unsigned long config); 39 39 + int gpiochip_fwd_gpio_to_irq(struct gpiochip_fwd *fwd, unsigned int offset); 40 40 + 41 41 + #endif

+86 -16

include/linux/gpio/generic.h

reviewed

··· 9 9 10 10 struct device; 11 11 12 12 + #define GPIO_GENERIC_BIG_ENDIAN BIT(0) 13 13 + #define GPIO_GENERIC_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 14 14 + #define GPIO_GENERIC_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 15 15 + #define GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER BIT(3) 16 16 + #define GPIO_GENERIC_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 17 17 + #define GPIO_GENERIC_NO_OUTPUT BIT(5) /* only input */ 18 18 + #define GPIO_GENERIC_NO_SET_ON_INPUT BIT(6) 19 19 + #define GPIO_GENERIC_PINCTRL_BACKEND BIT(7) /* Call pinctrl direction setters */ 20 20 + #define GPIO_GENERIC_NO_INPUT BIT(8) /* only output */ 21 21 + 12 22 /** 13 23 * struct gpio_generic_chip_config - Generic GPIO chip configuration data 14 24 * @dev: Parent device of the new GPIO chip (compulsory). ··· 60 50 * struct gpio_generic_chip - Generic GPIO chip implementation. 61 51 * @gc: The underlying struct gpio_chip object, implementing low-level GPIO 62 52 * chip routines. 53 53 + * @read_reg: reader function for generic GPIO 54 54 + * @write_reg: writer function for generic GPIO 55 55 + * @be_bits: if the generic GPIO has big endian bit order (bit 31 is 56 56 + * representing line 0, bit 30 is line 1 ... bit 0 is line 31) this 57 57 + * is set to true by the generic GPIO core. It is for internal 58 58 + * housekeeping only. 59 59 + * @reg_dat: data (in) register for generic GPIO 60 60 + * @reg_set: output set register (out=high) for generic GPIO 61 61 + * @reg_clr: output clear register (out=low) for generic GPIO 62 62 + * @reg_dir_out: direction out setting register for generic GPIO 63 63 + * @reg_dir_in: direction in setting register for generic GPIO 64 64 + * @dir_unreadable: indicates that the direction register(s) cannot be read and 65 65 + * we need to rely on out internal state tracking. 66 66 + * @pinctrl: the generic GPIO uses a pin control backend. 67 67 + * @bits: number of register bits used for a generic GPIO 68 68 + * i.e. <register width> * 8 69 69 + * @lock: used to lock chip->sdata. Also, this is needed to keep 70 70 + * shadowed and real data registers writes together. 71 71 + * @sdata: shadowed data register for generic GPIO to clear/set bits safely. 72 72 + * @sdir: shadowed direction register for generic GPIO to clear/set direction 73 73 + * safely. A "1" in this word means the line is set as output. 63 74 */ 64 75 struct gpio_generic_chip { 65 76 struct gpio_chip gc; 77 77 + unsigned long (*read_reg)(void __iomem *reg); 78 78 + void (*write_reg)(void __iomem *reg, unsigned long data); 79 79 + bool be_bits; 80 80 + void __iomem *reg_dat; 81 81 + void __iomem *reg_set; 82 82 + void __iomem *reg_clr; 83 83 + void __iomem *reg_dir_out; 84 84 + void __iomem *reg_dir_in; 85 85 + bool dir_unreadable; 86 86 + bool pinctrl; 87 87 + int bits; 88 88 + raw_spinlock_t lock; 89 89 + unsigned long sdata; 90 90 + unsigned long sdir; 66 91 }; 67 92 68 68 - /** 69 69 - * gpio_generic_chip_init() - Initialize a generic GPIO chip. 70 70 - * @chip: Generic GPIO chip to set up. 71 71 - * @cfg: Generic GPIO chip configuration. 72 72 - * 73 73 - * Returns 0 on success, negative error number on failure. 74 74 - */ 75 75 - static inline int 76 76 - gpio_generic_chip_init(struct gpio_generic_chip *chip, 77 77 - const struct gpio_generic_chip_config *cfg) 93 93 + static inline struct gpio_generic_chip * 94 94 + to_gpio_generic_chip(struct gpio_chip *gc) 78 95 { 79 79 - return bgpio_init(&chip->gc, cfg->dev, cfg->sz, cfg->dat, cfg->set, 80 80 - cfg->clr, cfg->dirout, cfg->dirin, cfg->flags); 96 96 + return container_of(gc, struct gpio_generic_chip, gc); 81 97 } 98 98 + 99 99 + int gpio_generic_chip_init(struct gpio_generic_chip *chip, 100 100 + const struct gpio_generic_chip_config *cfg); 82 101 83 102 /** 84 103 * gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO chip. ··· 133 94 return chip->gc.set(&chip->gc, offset, value); 134 95 } 135 96 97 97 + /** 98 98 + * gpio_generic_read_reg() - Read a register using the underlying callback. 99 99 + * @chip: Generic GPIO chip to use. 100 100 + * @reg: Register to read. 101 101 + * 102 102 + * Returns: value read from register. 103 103 + */ 104 104 + static inline unsigned long 105 105 + gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg) 106 106 + { 107 107 + if (WARN_ON(!chip->read_reg)) 108 108 + return 0; 109 109 + 110 110 + return chip->read_reg(reg); 111 111 + } 112 112 + 113 113 + /** 114 114 + * gpio_generic_write_reg() - Write a register using the underlying callback. 115 115 + * @chip: Generic GPIO chip to use. 116 116 + * @reg: Register to write to. 117 117 + * @val: New value to write. 118 118 + */ 119 119 + static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip, 120 120 + void __iomem *reg, unsigned long val) 121 121 + { 122 122 + if (WARN_ON(!chip->write_reg)) 123 123 + return; 124 124 + 125 125 + chip->write_reg(reg, val); 126 126 + } 127 127 + 136 128 #define gpio_generic_chip_lock(gen_gc) \ 137 137 - raw_spin_lock(&(gen_gc)->gc.bgpio_lock) 129 129 + raw_spin_lock(&(gen_gc)->lock) 138 130 139 131 #define gpio_generic_chip_unlock(gen_gc) \ 140 140 - raw_spin_unlock(&(gen_gc)->gc.bgpio_lock) 132 132 + raw_spin_unlock(&(gen_gc)->lock) 141 133 142 134 #define gpio_generic_chip_lock_irqsave(gen_gc, flags) \ 143 143 - raw_spin_lock_irqsave(&(gen_gc)->gc.bgpio_lock, flags) 135 135 + raw_spin_lock_irqsave(&(gen_gc)->lock, flags) 144 136 145 137 #define gpio_generic_chip_unlock_irqrestore(gen_gc, flags) \ 146 146 - raw_spin_unlock_irqrestore(&(gen_gc)->gc.bgpio_lock, flags) 138 138 + raw_spin_unlock_irqrestore(&(gen_gc)->lock, flags) 147 139 148 140 DEFINE_LOCK_GUARD_1(gpio_generic_lock, 149 141 struct gpio_generic_chip,

+2 -4

include/linux/gpio/gpio-nomadik.h

reviewed

··· 261 261 * true. 262 262 */ 263 263 void nmk_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev, 264 264 - struct gpio_chip *chip, unsigned int offset, 265 265 - unsigned int gpio); 264 264 + struct gpio_chip *chip, unsigned int offset); 266 265 267 266 #else 268 267 269 268 static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 270 269 struct pinctrl_dev *pctldev, 271 270 struct gpio_chip *chip, 272 272 - unsigned int offset, 273 273 - unsigned int gpio) 271 271 + unsigned int offset) 274 272 { 275 273 } 276 274

+18

include/linux/gpio/regmap.h

reviewed

··· 6 6 struct device; 7 7 struct fwnode_handle; 8 8 struct gpio_regmap; 9 9 + struct gpio_chip; 9 10 struct irq_domain; 10 11 struct regmap; 11 12 ··· 41 40 * @drvdata: (Optional) Pointer to driver specific data which is 42 41 * not used by gpio-remap but is provided "as is" to the 43 42 * driver callback(s). 43 43 + * @init_valid_mask: (Optional) Routine to initialize @valid_mask, to be used 44 44 + * if not all GPIOs are valid. 45 45 + * @regmap_irq_chip: (Optional) Pointer on an regmap_irq_chip structure. If 46 46 + * set, a regmap-irq device will be created and the IRQ 47 47 + * domain will be set accordingly. 48 48 + * @regmap_irq_line (Optional) The IRQ the device uses to signal interrupts. 49 49 + * @regmap_irq_flags (Optional) The IRQF_ flags to use for the interrupt. 44 50 * 45 51 * The ->reg_mask_xlate translates a given base address and GPIO offset to 46 52 * register and mask pair. The base address is one of the given register ··· 86 78 int ngpio_per_reg; 87 79 struct irq_domain *irq_domain; 88 80 81 81 + #ifdef CONFIG_REGMAP_IRQ 82 82 + struct regmap_irq_chip *regmap_irq_chip; 83 83 + int regmap_irq_line; 84 84 + unsigned long regmap_irq_flags; 85 85 + #endif 86 86 + 89 87 int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, 90 88 unsigned int offset, unsigned int *reg, 91 89 unsigned int *mask); 90 90 + 91 91 + int (*init_valid_mask)(struct gpio_chip *gc, 92 92 + unsigned long *valid_mask, 93 93 + unsigned int ngpios); 92 94 93 95 void *drvdata; 94 96 };

+109

include/linux/mfd/max7360.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 + 3 3 + #ifndef __LINUX_MFD_MAX7360_H 4 4 + #define __LINUX_MFD_MAX7360_H 5 5 + 6 6 + #include <linux/bits.h> 7 7 + 8 8 + #define MAX7360_MAX_KEY_ROWS 8 9 9 + #define MAX7360_MAX_KEY_COLS 8 10 10 + #define MAX7360_MAX_KEY_NUM (MAX7360_MAX_KEY_ROWS * MAX7360_MAX_KEY_COLS) 11 11 + #define MAX7360_ROW_SHIFT 3 12 12 + 13 13 + #define MAX7360_MAX_GPIO 8 14 14 + #define MAX7360_MAX_GPO 6 15 15 + #define MAX7360_PORT_PWM_COUNT 8 16 16 + #define MAX7360_PORT_RTR_PIN (MAX7360_PORT_PWM_COUNT - 1) 17 17 + 18 18 + /* 19 19 + * MAX7360 registers 20 20 + */ 21 21 + #define MAX7360_REG_KEYFIFO 0x00 22 22 + #define MAX7360_REG_CONFIG 0x01 23 23 + #define MAX7360_REG_DEBOUNCE 0x02 24 24 + #define MAX7360_REG_INTERRUPT 0x03 25 25 + #define MAX7360_REG_PORTS 0x04 26 26 + #define MAX7360_REG_KEYREP 0x05 27 27 + #define MAX7360_REG_SLEEP 0x06 28 28 + 29 29 + /* 30 30 + * MAX7360 GPIO registers 31 31 + * 32 32 + * All these registers are reset together when writing bit 3 of 33 33 + * MAX7360_REG_GPIOCFG. 34 34 + */ 35 35 + #define MAX7360_REG_GPIOCFG 0x40 36 36 + #define MAX7360_REG_GPIOCTRL 0x41 37 37 + #define MAX7360_REG_GPIODEB 0x42 38 38 + #define MAX7360_REG_GPIOCURR 0x43 39 39 + #define MAX7360_REG_GPIOOUTM 0x44 40 40 + #define MAX7360_REG_PWMCOM 0x45 41 41 + #define MAX7360_REG_RTRCFG 0x46 42 42 + #define MAX7360_REG_I2C_TIMEOUT 0x48 43 43 + #define MAX7360_REG_GPIOIN 0x49 44 44 + #define MAX7360_REG_RTR_CNT 0x4A 45 45 + #define MAX7360_REG_PWMBASE 0x50 46 46 + #define MAX7360_REG_PWMCFGBASE 0x58 47 47 + 48 48 + #define MAX7360_REG_GPIO_LAST 0x5F 49 49 + 50 50 + #define MAX7360_REG_PWM(x) (MAX7360_REG_PWMBASE + (x)) 51 51 + #define MAX7360_REG_PWMCFG(x) (MAX7360_REG_PWMCFGBASE + (x)) 52 52 + 53 53 + /* 54 54 + * Configuration register bits 55 55 + */ 56 56 + #define MAX7360_FIFO_EMPTY 0x3F 57 57 + #define MAX7360_FIFO_OVERFLOW 0x7F 58 58 + #define MAX7360_FIFO_RELEASE BIT(6) 59 59 + #define MAX7360_FIFO_COL GENMASK(5, 3) 60 60 + #define MAX7360_FIFO_ROW GENMASK(2, 0) 61 61 + 62 62 + #define MAX7360_CFG_SLEEP BIT(7) 63 63 + #define MAX7360_CFG_INTERRUPT BIT(5) 64 64 + #define MAX7360_CFG_KEY_RELEASE BIT(3) 65 65 + #define MAX7360_CFG_WAKEUP BIT(1) 66 66 + #define MAX7360_CFG_TIMEOUT BIT(0) 67 67 + 68 68 + #define MAX7360_DEBOUNCE GENMASK(4, 0) 69 69 + #define MAX7360_DEBOUNCE_MIN 9 70 70 + #define MAX7360_DEBOUNCE_MAX 40 71 71 + #define MAX7360_PORTS GENMASK(8, 5) 72 72 + 73 73 + #define MAX7360_INTERRUPT_TIME_MASK GENMASK(4, 0) 74 74 + #define MAX7360_INTERRUPT_FIFO_MASK GENMASK(7, 5) 75 75 + 76 76 + #define MAX7360_PORT_CFG_INTERRUPT_MASK BIT(7) 77 77 + #define MAX7360_PORT_CFG_INTERRUPT_EDGES BIT(6) 78 78 + #define MAX7360_PORT_CFG_COMMON_PWM BIT(5) 79 79 + 80 80 + /* 81 81 + * Autosleep register values 82 82 + */ 83 83 + #define MAX7360_AUTOSLEEP_8192MS 0x01 84 84 + #define MAX7360_AUTOSLEEP_4096MS 0x02 85 85 + #define MAX7360_AUTOSLEEP_2048MS 0x03 86 86 + #define MAX7360_AUTOSLEEP_1024MS 0x04 87 87 + #define MAX7360_AUTOSLEEP_512MS 0x05 88 88 + #define MAX7360_AUTOSLEEP_256MS 0x06 89 89 + 90 90 + #define MAX7360_GPIO_CFG_RTR_EN BIT(7) 91 91 + #define MAX7360_GPIO_CFG_GPIO_EN BIT(4) 92 92 + #define MAX7360_GPIO_CFG_GPIO_RST BIT(3) 93 93 + 94 94 + #define MAX7360_ROT_DEBOUNCE GENMASK(3, 0) 95 95 + #define MAX7360_ROT_DEBOUNCE_MIN 0 96 96 + #define MAX7360_ROT_DEBOUNCE_MAX 15 97 97 + #define MAX7360_ROT_INTCNT GENMASK(6, 4) 98 98 + #define MAX7360_ROT_INTCNT_DLY BIT(7) 99 99 + 100 100 + #define MAX7360_INT_INTI 0 101 101 + #define MAX7360_INT_INTK 1 102 102 + 103 103 + #define MAX7360_INT_GPIO 0 104 104 + #define MAX7360_INT_KEYPAD 1 105 105 + #define MAX7360_INT_ROTARY 2 106 106 + 107 107 + #define MAX7360_NR_INTERNAL_IRQS 3 108 108 + 109 109 + #endif

+102

include/linux/mfd/nct6694.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Copyright (C) 2025 Nuvoton Technology Corp. 4 4 + * 5 5 + * Nuvoton NCT6694 USB transaction and data structure. 6 6 + */ 7 7 + 8 8 + #ifndef __MFD_NCT6694_H 9 9 + #define __MFD_NCT6694_H 10 10 + 11 11 + #define NCT6694_VENDOR_ID 0x0416 12 12 + #define NCT6694_PRODUCT_ID 0x200B 13 13 + #define NCT6694_INT_IN_EP 0x81 14 14 + #define NCT6694_BULK_IN_EP 0x02 15 15 + #define NCT6694_BULK_OUT_EP 0x03 16 16 + 17 17 + #define NCT6694_HCTRL_SET 0x40 18 18 + #define NCT6694_HCTRL_GET 0x80 19 19 + 20 20 + #define NCT6694_URB_TIMEOUT 1000 21 21 + 22 22 + enum nct6694_irq_id { 23 23 + NCT6694_IRQ_GPIO0 = 0, 24 24 + NCT6694_IRQ_GPIO1, 25 25 + NCT6694_IRQ_GPIO2, 26 26 + NCT6694_IRQ_GPIO3, 27 27 + NCT6694_IRQ_GPIO4, 28 28 + NCT6694_IRQ_GPIO5, 29 29 + NCT6694_IRQ_GPIO6, 30 30 + NCT6694_IRQ_GPIO7, 31 31 + NCT6694_IRQ_GPIO8, 32 32 + NCT6694_IRQ_GPIO9, 33 33 + NCT6694_IRQ_GPIOA, 34 34 + NCT6694_IRQ_GPIOB, 35 35 + NCT6694_IRQ_GPIOC, 36 36 + NCT6694_IRQ_GPIOD, 37 37 + NCT6694_IRQ_GPIOE, 38 38 + NCT6694_IRQ_GPIOF, 39 39 + NCT6694_IRQ_CAN0, 40 40 + NCT6694_IRQ_CAN1, 41 41 + NCT6694_IRQ_RTC, 42 42 + NCT6694_NR_IRQS, 43 43 + }; 44 44 + 45 45 + enum nct6694_response_err_status { 46 46 + NCT6694_NO_ERROR = 0, 47 47 + NCT6694_FORMAT_ERROR, 48 48 + NCT6694_RESERVED1, 49 49 + NCT6694_RESERVED2, 50 50 + NCT6694_NOT_SUPPORT_ERROR, 51 51 + NCT6694_NO_RESPONSE_ERROR, 52 52 + NCT6694_TIMEOUT_ERROR, 53 53 + NCT6694_PENDING, 54 54 + }; 55 55 + 56 56 + struct __packed nct6694_cmd_header { 57 57 + u8 rsv1; 58 58 + u8 mod; 59 59 + union __packed { 60 60 + __le16 offset; 61 61 + struct __packed { 62 62 + u8 cmd; 63 63 + u8 sel; 64 64 + }; 65 65 + }; 66 66 + u8 hctrl; 67 67 + u8 rsv2; 68 68 + __le16 len; 69 69 + }; 70 70 + 71 71 + struct __packed nct6694_response_header { 72 72 + u8 sequence_id; 73 73 + u8 sts; 74 74 + u8 reserved[4]; 75 75 + __le16 len; 76 76 + }; 77 77 + 78 78 + union __packed nct6694_usb_msg { 79 79 + struct nct6694_cmd_header cmd_header; 80 80 + struct nct6694_response_header response_header; 81 81 + }; 82 82 + 83 83 + struct nct6694 { 84 84 + struct device *dev; 85 85 + struct ida gpio_ida; 86 86 + struct ida i2c_ida; 87 87 + struct ida canfd_ida; 88 88 + struct ida wdt_ida; 89 89 + struct irq_domain *domain; 90 90 + struct mutex access_lock; 91 91 + spinlock_t irq_lock; 92 92 + struct urb *int_in_urb; 93 93 + struct usb_device *udev; 94 94 + union nct6694_usb_msg *usb_msg; 95 95 + __le32 *int_buffer; 96 96 + unsigned int irq_enable; 97 97 + }; 98 98 + 99 99 + int nct6694_read_msg(struct nct6694 *nct6694, const struct nct6694_cmd_header *cmd_hd, void *buf); 100 100 + int nct6694_write_msg(struct nct6694 *nct6694, const struct nct6694_cmd_header *cmd_hd, void *buf); 101 101 + 102 102 + #endif

+6

include/linux/string_choices.h

reviewed

··· 47 47 } 48 48 #define str_low_high(v) str_high_low(!(v)) 49 49 50 50 + static inline const char *str_input_output(bool v) 51 51 + { 52 52 + return v ? "input" : "output"; 53 53 + } 54 54 + #define str_output_input(v) str_input_output(!(v)) 55 55 + 50 56 static inline const char *str_on_off(bool v) 51 57 { 52 58 return v ? "on" : "off";