Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A smaller set of fixes this week, and all regression fixes:
- a handful of issues fixed on at91 with common clock conversion
- a set of fixes for Marvell mvebu (SMP, coherency, PM)
- a clock fix for i.MX6Q.
- ... and a SMP/hotplug fix for Exynos"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: EXYNOS: Fix core ID used by platsmp and hotplug code
ARM: at91/dt: add missing clocks property to pwm node in sam9x5.dtsi
ARM: at91/dt: fix usb0 clocks definition in sam9n12 dtsi
ARM: at91: at91sam9x5: correct typo error for ohci clock
ARM: clk-imx6q: parent lvds_sel input from upstream clock gates
ARM: mvebu: Fix coherency bus notifiers by using separate notifiers
ARM: mvebu: Fix the operand list in the inline asm of armada_370_xp_pmsu_idle_enter
ARM: mvebu: fix SMP boot for Armada 38x and Armada 375 Z1 in big endian
+48
-31
+1
-1
arch/arm/boot/dts/at91sam9n12.dtsi
+1
-1
arch/arm/boot/dts/at91sam9n12.dtsi
···
925
925
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
926
926
reg = <0x00500000 0x00100000>;
927
927
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
928
-
clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
928
+
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
929
929
<&uhpck>;
930
930
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
931
931
status = "disabled";
+2
-2
arch/arm/boot/dts/at91sam9x5.dtsi
+2
-2
arch/arm/boot/dts/at91sam9x5.dtsi
···
1124
1124
compatible = "atmel,at91sam9rl-pwm";
1125
1125
reg = <0xf8034000 0x300>;
1126
1126
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1127
+
clocks = <&pwm_clk>;
1127
1128
#pwm-cells = <3>;
1128
1129
status = "disabled";
1129
1130
};
···
1156
1155
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1157
1156
reg = <0x00600000 0x100000>;
1158
1157
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1159
-
clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
1160
-
<&uhpck>;
1158
+
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1161
1159
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
1162
1160
status = "disabled";
1163
1161
};
+6
-4
arch/arm/mach-exynos/hotplug.c
+6
-4
arch/arm/mach-exynos/hotplug.c
···
40
40
41
41
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
42
42
{
43
+
u32 mpidr = cpu_logical_map(cpu);
44
+
u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
45
+
43
46
for (;;) {
44
47
45
-
/* make cpu1 to be turned off at next WFI command */
46
-
if (cpu == 1)
47
-
exynos_cpu_power_down(cpu);
48
+
/* Turn the CPU off on next WFI instruction. */
49
+
exynos_cpu_power_down(core_id);
48
50
49
51
wfi();
50
52
51
-
if (pen_release == cpu_logical_map(cpu)) {
53
+
if (pen_release == core_id) {
52
54
/*
53
55
* OK, proper wakeup, we're done
54
56
*/
+19
-15
arch/arm/mach-exynos/platsmp.c
+19
-15
arch/arm/mach-exynos/platsmp.c
···
90
90
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
91
91
{
92
92
unsigned long timeout;
93
-
unsigned long phys_cpu = cpu_logical_map(cpu);
93
+
u32 mpidr = cpu_logical_map(cpu);
94
+
u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
94
95
int ret = -ENOSYS;
95
96
96
97
/*
···
105
104
* the holding pen - release it, then wait for it to flag
106
105
* that it has been released by resetting pen_release.
107
106
*
108
-
* Note that "pen_release" is the hardware CPU ID, whereas
107
+
* Note that "pen_release" is the hardware CPU core ID, whereas
109
108
* "cpu" is Linux's internal ID.
110
109
*/
111
-
write_pen_release(phys_cpu);
110
+
write_pen_release(core_id);
112
111
113
-
if (!exynos_cpu_power_state(cpu)) {
114
-
exynos_cpu_power_up(cpu);
112
+
if (!exynos_cpu_power_state(core_id)) {
113
+
exynos_cpu_power_up(core_id);
115
114
timeout = 10;
116
115
117
116
/* wait max 10 ms until cpu1 is on */
118
-
while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
117
+
while (exynos_cpu_power_state(core_id)
118
+
!= S5P_CORE_LOCAL_PWR_EN) {
119
119
if (timeout-- == 0)
120
120
break;
121
121
···
147
145
* Try to set boot address using firmware first
148
146
* and fall back to boot register if it fails.
149
147
*/
150
-
ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
148
+
ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
151
149
if (ret && ret != -ENOSYS)
152
150
goto fail;
153
151
if (ret == -ENOSYS) {
154
-
void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
152
+
void __iomem *boot_reg = cpu_boot_reg(core_id);
155
153
156
154
if (IS_ERR(boot_reg)) {
157
155
ret = PTR_ERR(boot_reg);
158
156
goto fail;
159
157
}
160
-
__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
158
+
__raw_writel(boot_addr, cpu_boot_reg(core_id));
161
159
}
162
160
163
-
call_firmware_op(cpu_boot, phys_cpu);
161
+
call_firmware_op(cpu_boot, core_id);
164
162
165
163
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
166
164
···
229
227
* boot register if it fails.
230
228
*/
231
229
for (i = 1; i < max_cpus; ++i) {
232
-
unsigned long phys_cpu;
233
230
unsigned long boot_addr;
231
+
u32 mpidr;
232
+
u32 core_id;
234
233
int ret;
235
234
236
-
phys_cpu = cpu_logical_map(i);
235
+
mpidr = cpu_logical_map(i);
236
+
core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
237
237
boot_addr = virt_to_phys(exynos4_secondary_startup);
238
238
239
-
ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
239
+
ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
240
240
if (ret && ret != -ENOSYS)
241
241
break;
242
242
if (ret == -ENOSYS) {
243
-
void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
243
+
void __iomem *boot_reg = cpu_boot_reg(core_id);
244
244
245
245
if (IS_ERR(boot_reg))
246
246
break;
247
-
__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
247
+
__raw_writel(boot_addr, cpu_boot_reg(core_id));
248
248
}
249
249
}
250
250
}
+2
-2
arch/arm/mach-imx/clk-imx6q.c
+2
-2
arch/arm/mach-imx/clk-imx6q.c
···
70
70
static const char *lvds_sels[] = {
71
71
"dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
72
72
"pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
73
-
"pcie_ref", "sata_ref",
73
+
"pcie_ref_125m", "sata_ref_100m",
74
74
};
75
75
76
76
enum mx6q_clks {
···
491
491
492
492
/* All existing boards with PCIe use LVDS1 */
493
493
if (IS_ENABLED(CONFIG_PCI_IMX6))
494
-
clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
494
+
clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]);
495
495
496
496
/* Set initial power mode */
497
497
imx6q_set_lpm(WAIT_CLOCKED);
+5
-1
arch/arm/mach-mvebu/coherency.c
+5
-1
arch/arm/mach-mvebu/coherency.c
···
292
292
.notifier_call = mvebu_hwcc_notifier,
293
293
};
294
294
295
+
static struct notifier_block mvebu_hwcc_pci_nb = {
296
+
.notifier_call = mvebu_hwcc_notifier,
297
+
};
298
+
295
299
static void __init armada_370_coherency_init(struct device_node *np)
296
300
{
297
301
struct resource res;
···
431
427
{
432
428
if (coherency_available())
433
429
bus_register_notifier(&pci_bus_type,
434
-
&mvebu_hwcc_nb);
430
+
&mvebu_hwcc_pci_nb);
435
431
return 0;
436
432
}
437
433
+8
-1
arch/arm/mach-mvebu/headsmp-a9.S
+8
-1
arch/arm/mach-mvebu/headsmp-a9.S
···
15
15
#include <linux/linkage.h>
16
16
#include <linux/init.h>
17
17
18
+
#include <asm/assembler.h>
19
+
18
20
__CPUINIT
19
21
#define CPU_RESUME_ADDR_REG 0xf10182d4
20
22
···
24
22
.global armada_375_smp_cpu1_enable_code_end
25
23
26
24
armada_375_smp_cpu1_enable_code_start:
27
-
ldr r0, [pc, #4]
25
+
ARM_BE8(setend be)
26
+
adr r0, 1f
27
+
ldr r0, [r0]
28
28
ldr r1, [r0]
29
+
ARM_BE8(rev r1, r1)
29
30
mov pc, r1
31
+
1:
30
32
.word CPU_RESUME_ADDR_REG
31
33
armada_375_smp_cpu1_enable_code_end:
32
34
33
35
ENTRY(mvebu_cortex_a9_secondary_startup)
36
+
ARM_BE8(setend be)
34
37
bl v7_invalidate_l1
35
38
b secondary_startup
36
39
ENDPROC(mvebu_cortex_a9_secondary_startup)
+5
-5
arch/arm/mach-mvebu/pmsu.c
+5
-5
arch/arm/mach-mvebu/pmsu.c
···
201
201
202
202
/* Test the CR_C bit and set it if it was cleared */
203
203
asm volatile(
204
-
"mrc p15, 0, %0, c1, c0, 0 \n\t"
205
-
"tst %0, #(1 << 2) \n\t"
206
-
"orreq %0, %0, #(1 << 2) \n\t"
207
-
"mcreq p15, 0, %0, c1, c0, 0 \n\t"
204
+
"mrc p15, 0, r0, c1, c0, 0 \n\t"
205
+
"tst r0, #(1 << 2) \n\t"
206
+
"orreq r0, r0, #(1 << 2) \n\t"
207
+
"mcreq p15, 0, r0, c1, c0, 0 \n\t"
208
208
"isb "
209
-
: : "r" (0));
209
+
: : : "r0");
210
210
211
211
pr_warn("Failed to suspend the system\n");
212
212