tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"i915, nouveau and amdgpu/radeon fixes in this:

nouveau:
Two fixes, one for a regression with dithering and one for a bug
hit by the userspace drivers.

i915:
A few fixes, mostly things heading for stable, two important
skylake GT3/4 hangs.

radeon/amdgpu:
Some audio, suspend/resume and some runtime PM fixes, along with
two patches to harden the userptr ABI a bit"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (24 commits)
drm: Loongson-3 doesn't fully support wc memory
drm/nouveau/gr/gf100: select a stream master to fixup tfb offset queries
amdgpu/uvd: add uvd fw version for amdgpu
drm/amdgpu: forbid mapping of userptr bo through radeon device file
drm/radeon: forbid mapping of userptr bo through radeon device file
drm/amdgpu: bump the afmt limit for CZ, ST, Polaris
drm/amdgpu: use defines for CRTCs and AMFT blocks
drm/dp/mst: Validate port in drm_dp_payload_send_msg()
drm/nouveau/kms: fix setting of default values for dithering properties
drm/radeon: print a message if ATPX dGPU power control is missing
Revert "drm/radeon: disable runtime pm on PX laptops without dGPU power control"
drm/amdgpu/acp: fix resume on CZ systems with AZ audio
drm/radeon: add a quirk for a XFX R9 270X
drm/radeon: print pci revision as well as pci ids on driver load
drm/i915: Use fw_domains_put_with_fifo() on HSW
drm/i915: Force ringbuffers to not be at offset 0
drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
drm/i915/skl: Fix spurious gpu hang with gt3/gt4 revs
drm/i915/skl: Fix rc6 based gpu/system hang
drm/i915/userptr: Hold mmref whilst calling get-user-pages
...

Linus Torvalds d61fb48b d4b05288

+125 -62
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 1591 1591 struct amdgpu_bo *vcpu_bo; 1592 1592 void *cpu_addr; 1593 1593 uint64_t gpu_addr; 1594 + unsigned fw_version; 1594 1595 void *saved_bo; 1595 1596 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1596 1597 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
··· 425 425 struct acp_pm_domain *apd; 426 426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 427 427 428 + /* return early if no ACP */ 429 + if (!adev->acp.acp_genpd) 430 + return 0; 431 + 428 432 /* SMU block will power on ACP irrespective of ACP runtime status. 429 433 * Power off explicitly based on genpd ACP runtime status so that ACP 430 434 * hw and ACP-genpd status are in sync.
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
··· 303 303 fw_info.feature = adev->vce.fb_version; 304 304 break; 305 305 case AMDGPU_INFO_FW_UVD: 306 - fw_info.ver = 0; 306 + fw_info.ver = adev->uvd.fw_version; 307 307 fw_info.feature = 0; 308 308 break; 309 309 case AMDGPU_INFO_FW_GMC:
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
··· 53 53 54 54 #define AMDGPU_MAX_HPD_PINS 6 55 55 #define AMDGPU_MAX_CRTCS 6 56 - #define AMDGPU_MAX_AFMT_BLOCKS 7 56 + #define AMDGPU_MAX_AFMT_BLOCKS 9 57 57 58 58 enum amdgpu_rmx_type { 59 59 RMX_OFF, ··· 309 309 struct atom_context *atom_context; 310 310 struct card_info *atom_card_info; 311 311 bool mode_config_initialized; 312 - struct amdgpu_crtc *crtcs[6]; 313 - struct amdgpu_afmt *afmt[7]; 312 + struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 313 + struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 314 314 /* DVI-I properties */ 315 315 struct drm_property *coherent_mode_property; 316 316 /* DAC enable load detect */
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 223 223 { 224 224 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo); 225 225 226 + if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 227 + return -EPERM; 226 228 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); 227 229 } 228 230
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
··· 158 158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 159 159 version_major, version_minor, family_id); 160 160 161 + adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 162 + (family_id << 8)); 163 + 161 164 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) 162 165 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; 163 166 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, ··· 257 254 258 255 if (i == AMDGPU_MAX_UVD_HANDLES) 259 256 return 0; 257 + 258 + cancel_delayed_work_sync(&adev->uvd.idle_work); 260 259 261 260 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 262 261 ptr = adev->uvd.cpu_addr;
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
··· 234 234 if (i == AMDGPU_MAX_VCE_HANDLES) 235 235 return 0; 236 236 237 + cancel_delayed_work_sync(&adev->vce.idle_work); 237 238 /* TODO: suspending running encoding sessions isn't supported */ 238 239 return -EINVAL; 239 240 }
+8 -1
drivers/gpu/drm/drm_dp_mst_topology.c
··· 1672 1672 u8 sinks[DRM_DP_MAX_SDP_STREAMS]; 1673 1673 int i; 1674 1674 1675 + port = drm_dp_get_validated_port_ref(mgr, port); 1676 + if (!port) 1677 + return -EINVAL; 1678 + 1675 1679 port_num = port->port_num; 1676 1680 mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent); 1677 1681 if (!mstb) { 1678 1682 mstb = drm_dp_get_last_connected_port_and_mstb(mgr, port->parent, &port_num); 1679 1683 1680 - if (!mstb) 1684 + if (!mstb) { 1685 + drm_dp_put_port(port); 1681 1686 return -EINVAL; 1687 + } 1682 1688 } 1683 1689 1684 1690 txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); ··· 1713 1707 kfree(txmsg); 1714 1708 fail_put: 1715 1709 drm_dp_put_mst_branch_device(mstb); 1710 + drm_dp_put_port(port); 1716 1711 return ret; 1717 1712 } 1718 1713
+3 -2
drivers/gpu/drm/i915/i915_drv.h
··· 2634 2634 2635 2635 /* WaRsDisableCoarsePowerGating:skl,bxt */ 2636 2636 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \ 2637 - ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \ 2638 - IS_SKL_REVID(dev, 0, SKL_REVID_F0))) 2637 + IS_SKL_GT3(dev) || \ 2638 + IS_SKL_GT4(dev)) 2639 + 2639 2640 /* 2640 2641 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2641 2642 * even when in MSI mode. This results in spurious interrupt warnings if the
+16 -11
drivers/gpu/drm/i915/i915_gem_userptr.c
··· 501 501 if (pvec != NULL) { 502 502 struct mm_struct *mm = obj->userptr.mm->mm; 503 503 504 - down_read(&mm->mmap_sem); 505 - while (pinned < npages) { 506 - ret = get_user_pages_remote(work->task, mm, 507 - obj->userptr.ptr + pinned * PAGE_SIZE, 508 - npages - pinned, 509 - !obj->userptr.read_only, 0, 510 - pvec + pinned, NULL); 511 - if (ret < 0) 512 - break; 504 + ret = -EFAULT; 505 + if (atomic_inc_not_zero(&mm->mm_users)) { 506 + down_read(&mm->mmap_sem); 507 + while (pinned < npages) { 508 + ret = get_user_pages_remote 509 + (work->task, mm, 510 + obj->userptr.ptr + pinned * PAGE_SIZE, 511 + npages - pinned, 512 + !obj->userptr.read_only, 0, 513 + pvec + pinned, NULL); 514 + if (ret < 0) 515 + break; 513 516 514 - pinned += ret; 517 + pinned += ret; 518 + } 519 + up_read(&mm->mmap_sem); 520 + mmput(mm); 515 521 } 516 - up_read(&mm->mmap_sem); 517 522 } 518 523 519 524 mutex_lock(&dev->struct_mutex);
+11 -5
drivers/gpu/drm/i915/intel_lrc.c
··· 841 841 if (unlikely(total_bytes > remain_usable)) { 842 842 /* 843 843 * The base request will fit but the reserved space 844 - * falls off the end. So only need to to wait for the 845 - * reserved size after flushing out the remainder. 844 + * falls off the end. So don't need an immediate wrap 845 + * and only need to effectively wait for the reserved 846 + * size space from the start of ringbuffer. 846 847 */ 847 848 wait_bytes = remain_actual + ringbuf->reserved_size; 848 - need_wrap = true; 849 849 } else if (total_bytes > ringbuf->space) { 850 850 /* No wrapping required, just waiting. */ 851 851 wait_bytes = total_bytes; ··· 1913 1913 struct intel_ringbuffer *ringbuf = request->ringbuf; 1914 1914 int ret; 1915 1915 1916 - ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS); 1916 + ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS); 1917 1917 if (ret) 1918 1918 return ret; 1919 + 1920 + /* We're using qword write, seqno should be aligned to 8 bytes. */ 1921 + BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); 1919 1922 1920 1923 /* w/a for post sync ops following a GPGPU operation we 1921 1924 * need a prior CS_STALL, which is emitted by the flush 1922 1925 * following the batch. 1923 1926 */ 1924 - intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5)); 1927 + intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); 1925 1928 intel_logical_ring_emit(ringbuf, 1926 1929 (PIPE_CONTROL_GLOBAL_GTT_IVB | 1927 1930 PIPE_CONTROL_CS_STALL | ··· 1932 1929 intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring)); 1933 1930 intel_logical_ring_emit(ringbuf, 0); 1934 1931 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); 1932 + /* We're thrashing one dword of HWS. */ 1933 + intel_logical_ring_emit(ringbuf, 0); 1935 1934 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); 1935 + intel_logical_ring_emit(ringbuf, MI_NOOP); 1936 1936 return intel_logical_ring_advance_and_submit(request); 1937 1937 } 1938 1938
+28 -14
drivers/gpu/drm/i915/intel_pm.c
··· 2876 2876 const struct drm_plane_state *pstate, 2877 2877 int y) 2878 2878 { 2879 - struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); 2879 + struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); 2880 2880 struct drm_framebuffer *fb = pstate->fb; 2881 + uint32_t width = 0, height = 0; 2882 + 2883 + width = drm_rect_width(&intel_pstate->src) >> 16; 2884 + height = drm_rect_height(&intel_pstate->src) >> 16; 2885 + 2886 + if (intel_rotation_90_or_270(pstate->rotation)) 2887 + swap(width, height); 2881 2888 2882 2889 /* for planar format */ 2883 2890 if (fb->pixel_format == DRM_FORMAT_NV12) { 2884 2891 if (y) /* y-plane data rate */ 2885 - return intel_crtc->config->pipe_src_w * 2886 - intel_crtc->config->pipe_src_h * 2892 + return width * height * 2887 2893 drm_format_plane_cpp(fb->pixel_format, 0); 2888 2894 else /* uv-plane data rate */ 2889 - return (intel_crtc->config->pipe_src_w/2) * 2890 - (intel_crtc->config->pipe_src_h/2) * 2895 + return (width / 2) * (height / 2) * 2891 2896 drm_format_plane_cpp(fb->pixel_format, 1); 2892 2897 } 2893 2898 2894 2899 /* for packed formats */ 2895 - return intel_crtc->config->pipe_src_w * 2896 - intel_crtc->config->pipe_src_h * 2897 - drm_format_plane_cpp(fb->pixel_format, 0); 2900 + return width * height * drm_format_plane_cpp(fb->pixel_format, 0); 2898 2901 } 2899 2902 2900 2903 /* ··· 2976 2973 struct drm_framebuffer *fb = plane->state->fb; 2977 2974 int id = skl_wm_plane_id(intel_plane); 2978 2975 2979 - if (fb == NULL) 2976 + if (!to_intel_plane_state(plane->state)->visible) 2980 2977 continue; 2978 + 2981 2979 if (plane->type == DRM_PLANE_TYPE_CURSOR) 2982 2980 continue; 2983 2981 ··· 3004 3000 uint16_t plane_blocks, y_plane_blocks = 0; 3005 3001 int id = skl_wm_plane_id(intel_plane); 3006 3002 3007 - if (pstate->fb == NULL) 3003 + if (!to_intel_plane_state(pstate)->visible) 3008 3004 continue; 3009 3005 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3010 3006 continue; ··· 3127 3123 { 3128 3124 struct drm_plane *plane = &intel_plane->base; 3129 3125 struct drm_framebuffer *fb = plane->state->fb; 3126 + struct intel_plane_state *intel_pstate = 3127 + to_intel_plane_state(plane->state); 3130 3128 uint32_t latency = dev_priv->wm.skl_latency[level]; 3131 3129 uint32_t method1, method2; 3132 3130 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3133 3131 uint32_t res_blocks, res_lines; 3134 3132 uint32_t selected_result; 3135 3133 uint8_t cpp; 3134 + uint32_t width = 0, height = 0; 3136 3135 3137 - if (latency == 0 || !cstate->base.active || !fb) 3136 + if (latency == 0 || !cstate->base.active || !intel_pstate->visible) 3138 3137 return false; 3138 + 3139 + width = drm_rect_width(&intel_pstate->src) >> 16; 3140 + height = drm_rect_height(&intel_pstate->src) >> 16; 3141 + 3142 + if (intel_rotation_90_or_270(plane->state->rotation)) 3143 + swap(width, height); 3139 3144 3140 3145 cpp = drm_format_plane_cpp(fb->pixel_format, 0); 3141 3146 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate), 3142 3147 cpp, latency); 3143 3148 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate), 3144 3149 cstate->base.adjusted_mode.crtc_htotal, 3145 - cstate->pipe_src_w, 3146 - cpp, fb->modifier[0], 3150 + width, 3151 + cpp, 3152 + fb->modifier[0], 3147 3153 latency); 3148 3154 3149 - plane_bytes_per_line = cstate->pipe_src_w * cpp; 3155 + plane_bytes_per_line = width * cpp; 3150 3156 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3151 3157 3152 3158 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
+11 -7
drivers/gpu/drm/i915/intel_ringbuffer.c
··· 968 968 969 969 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ 970 970 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; 971 - if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) || 971 + if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) || 972 972 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) 973 973 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; 974 974 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); ··· 1085 1085 WA_SET_BIT_MASKED(HIZ_CHICKEN, 1086 1086 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); 1087 1087 1088 - if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) { 1088 + /* This is tied to WaForceContextSaveRestoreNonCoherent */ 1089 + if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) { 1089 1090 /* 1090 1091 *Use Force Non-Coherent whenever executing a 3D context. This 1091 1092 * is a workaround for a possible hang in the unlikely event ··· 2091 2090 { 2092 2091 struct drm_i915_private *dev_priv = to_i915(dev); 2093 2092 struct drm_i915_gem_object *obj = ringbuf->obj; 2093 + /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ 2094 + unsigned flags = PIN_OFFSET_BIAS | 4096; 2094 2095 int ret; 2095 2096 2096 2097 if (HAS_LLC(dev_priv) && !obj->stolen) { 2097 - ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0); 2098 + ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); 2098 2099 if (ret) 2099 2100 return ret; 2100 2101 ··· 2112 2109 return -ENOMEM; 2113 2110 } 2114 2111 } else { 2115 - ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); 2112 + ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 2113 + flags | PIN_MAPPABLE); 2116 2114 if (ret) 2117 2115 return ret; 2118 2116 ··· 2458 2454 if (unlikely(total_bytes > remain_usable)) { 2459 2455 /* 2460 2456 * The base request will fit but the reserved space 2461 - * falls off the end. So only need to to wait for the 2462 - * reserved size after flushing out the remainder. 2457 + * falls off the end. So don't need an immediate wrap 2458 + * and only need to effectively wait for the reserved 2459 + * size space from the start of ringbuffer. 2463 2460 */ 2464 2461 wait_bytes = remain_actual + ringbuf->reserved_size; 2465 - need_wrap = true; 2466 2462 } else if (total_bytes > ringbuf->space) { 2467 2463 /* No wrapping required, just waiting. */ 2468 2464 wait_bytes = total_bytes;
+5 -1
drivers/gpu/drm/i915/intel_uncore.c
··· 1189 1189 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 1190 1190 dev_priv->uncore.funcs.force_wake_get = 1191 1191 fw_domains_get_with_thread_status; 1192 - dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1192 + if (IS_HASWELL(dev)) 1193 + dev_priv->uncore.funcs.force_wake_put = 1194 + fw_domains_put_with_fifo; 1195 + else 1196 + dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1193 1197 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1194 1198 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 1195 1199 } else if (IS_IVYBRIDGE(dev)) {
+2 -2
drivers/gpu/drm/nouveau/nouveau_connector.c
··· 1276 1276 break; 1277 1277 default: 1278 1278 if (disp->dithering_mode) { 1279 + nv_connector->dithering_mode = DITHERING_MODE_AUTO; 1279 1280 drm_object_attach_property(&connector->base, 1280 1281 disp->dithering_mode, 1281 1282 nv_connector-> 1282 1283 dithering_mode); 1283 - nv_connector->dithering_mode = DITHERING_MODE_AUTO; 1284 1284 } 1285 1285 if (disp->dithering_depth) { 1286 + nv_connector->dithering_depth = DITHERING_DEPTH_AUTO; 1286 1287 drm_object_attach_property(&connector->base, 1287 1288 disp->dithering_depth, 1288 1289 nv_connector-> 1289 1290 dithering_depth); 1290 - nv_connector->dithering_depth = DITHERING_DEPTH_AUTO; 1291 1291 } 1292 1292 break; 1293 1293 }
+2
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
··· 1832 1832 1833 1833 gf100_gr_mmio(gr, gr->func->mmio); 1834 1834 1835 + nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001); 1836 + 1835 1837 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); 1836 1838 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { 1837 1839 do {
+7 -4
drivers/gpu/drm/radeon/radeon_atpx_handler.c
··· 62 62 return radeon_atpx_priv.atpx_detected; 63 63 } 64 64 65 - bool radeon_has_atpx_dgpu_power_cntl(void) { 66 - return radeon_atpx_priv.atpx.functions.power_cntl; 67 - } 68 - 69 65 /** 70 66 * radeon_atpx_call - call an ATPX method 71 67 * ··· 141 145 */ 142 146 static int radeon_atpx_validate(struct radeon_atpx *atpx) 143 147 { 148 + /* make sure required functions are enabled */ 149 + /* dGPU power control is required */ 150 + if (atpx->functions.power_cntl == false) { 151 + printk("ATPX dGPU power cntl not present, forcing\n"); 152 + atpx->functions.power_cntl = true; 153 + } 154 + 144 155 if (atpx->functions.px_params) { 145 156 union acpi_object *info; 146 157 struct atpx_px_params output;
+6 -1
drivers/gpu/drm/radeon/radeon_connectors.c
··· 2002 2002 rdev->mode_info.dither_property, 2003 2003 RADEON_FMT_DITHER_DISABLE); 2004 2004 2005 - if (radeon_audio != 0) 2005 + if (radeon_audio != 0) { 2006 2006 drm_object_attach_property(&radeon_connector->base.base, 2007 2007 rdev->mode_info.audio_property, 2008 2008 RADEON_AUDIO_AUTO); 2009 + radeon_connector->audio = RADEON_AUDIO_AUTO; 2010 + } 2009 2011 if (ASIC_IS_DCE5(rdev)) 2010 2012 drm_object_attach_property(&radeon_connector->base.base, 2011 2013 rdev->mode_info.output_csc_property, ··· 2132 2130 drm_object_attach_property(&radeon_connector->base.base, 2133 2131 rdev->mode_info.audio_property, 2134 2132 RADEON_AUDIO_AUTO); 2133 + radeon_connector->audio = RADEON_AUDIO_AUTO; 2135 2134 } 2136 2135 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 2137 2136 radeon_connector->dac_load_detect = true; ··· 2188 2185 drm_object_attach_property(&radeon_connector->base.base, 2189 2186 rdev->mode_info.audio_property, 2190 2187 RADEON_AUDIO_AUTO); 2188 + radeon_connector->audio = RADEON_AUDIO_AUTO; 2191 2189 } 2192 2190 if (ASIC_IS_DCE5(rdev)) 2193 2191 drm_object_attach_property(&radeon_connector->base.base, ··· 2241 2237 drm_object_attach_property(&radeon_connector->base.base, 2242 2238 rdev->mode_info.audio_property, 2243 2239 RADEON_AUDIO_AUTO); 2240 + radeon_connector->audio = RADEON_AUDIO_AUTO; 2244 2241 } 2245 2242 if (ASIC_IS_DCE5(rdev)) 2246 2243 drm_object_attach_property(&radeon_connector->base.base,
+4 -10
drivers/gpu/drm/radeon/radeon_device.c
··· 103 103 "LAST", 104 104 }; 105 105 106 - #if defined(CONFIG_VGA_SWITCHEROO) 107 - bool radeon_has_atpx_dgpu_power_cntl(void); 108 - #else 109 - static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 110 - #endif 111 - 112 106 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 113 107 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 114 108 ··· 1299 1305 } 1300 1306 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); 1301 1307 1302 - DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1303 - radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1304 - pdev->subsystem_vendor, pdev->subsystem_device); 1308 + DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", 1309 + radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1310 + pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); 1305 1311 1306 1312 /* mutex initialization are all done here so we 1307 1313 * can recall function without having locking issues */ ··· 1433 1439 * ignore it */ 1434 1440 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1435 1441 1436 - if ((rdev->flags & RADEON_IS_PX) && radeon_has_atpx_dgpu_power_cntl()) 1442 + if (rdev->flags & RADEON_IS_PX) 1437 1443 runtime = true; 1438 1444 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1439 1445 if (runtime)
+2
drivers/gpu/drm/radeon/radeon_ttm.c
··· 235 235 { 236 236 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 237 237 238 + if (radeon_ttm_tt_has_userptr(bo->ttm)) 239 + return -EPERM; 238 240 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); 239 241 } 240 242
+1
drivers/gpu/drm/radeon/si_dpm.c
··· 2931 2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, 2932 2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, 2933 2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, 2934 + { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, 2934 2935 { 0, 0, 0, 0 }, 2935 2936 }; 2936 2937
+2
include/drm/drm_cache.h
··· 39 39 { 40 40 #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) 41 41 return false; 42 + #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3) 43 + return false; 42 44 #else 43 45 return true; 44 46 #endif