tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2023-05-20' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Regular fixes pull, amdgpu and msm make up most of these, nothing too
serious, also one i915 and one exynos.

I didn't get a misc fixes pull this week (one of the maintainers is
off, so have to engage the backup) so I think there are a few
outstanding patches that will show up next week,

amdgpu:
- update gfx11 clock counter logic
- Fix a race when disabling gfxoff on gfx10/11 for profiling
- Raven/Raven2/PCO clock counter fix
- Add missing get_vbios_fb_size for GMC 11
- Fix a spurious irq warning in the device remove case
- Fix possible power mode mismatch between driver and PMFW
- USB4 fix

exynos:
- fix build warning

i915:
- fix missing NULL check in HDCP code

msm:
- display:
- msm8998: fix fetch and qos to align with downstream
- msm8998: fix LM pairs to align with downstream
- remove unused INTF0 interrupt mask on some chipsets
- remove TE2 block from relevant chipsets
- relocate non-MDP_TOP offset to different header
- fix some indentation
- fix register offets/masks for dither blocks
- make ping-ping block length 0
- remove duplicated defines
- fix log mask for writeback block
- unregister the hdmi codec for dp during unbind
- fix yaml warnings
- gpu:
- fix submit error path leak
- arm-smmu-qcom fix for regression that broke per-process page
tables
- fix no-iommu crash"

* tag 'drm-fixes-2023-05-20' of git://anongit.freedesktop.org/drm/drm: (29 commits)
drm/amd/display: enable dpia validate
drm/amd/pm: fix possible power mode mismatch between driver and PMFW
drm/amdgpu: skip disabling fence driver src_irqs when device is unplugged
drm/amdgpu/gmc11: implement get_vbios_fb_size()
drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id
drm/amdgpu/gfx11: Adjust gfxoff before powergating on gfx11 as well
drm/amdgpu/gfx10: Disable gfxoff before disabling powergating.
drm/amdgpu/gfx11: update gpu_clock_counter logic
drm/msm: Be more shouty if per-process pgtables aren't working
iommu/arm-smmu-qcom: Fix missing adreno_smmu's
drm/i915/hdcp: Check if media_gt exists
drm/exynos: fix g2d_open/close helper function definitions
drm/msm: Fix submit error-path leaks
drm/msm/iommu: Fix null pointer dereference in no-IOMMU case
dt-bindings: display/msm: dsi-controller-main: Document qcom, master-dsi and qcom, sync-dual-dsi
drm/msm/dpu: Remove duplicate register defines from INTF
drm/msm/dpu: Set PINGPONG block length to zero for DPU >= 7.0.0
drm/msm/dpu: Use V2 DITHER PINGPONG sub-block in SM8[34]50/SC8280XP
drm/msm/dpu: Fix PP_BLK_DIPHER -> DITHER typo
drm/msm/dpu: Reindent REV_7xxx interrupt masks with tabs
...

Linus Torvalds d635f6cc 5565ec4e

+236 -162
+12
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
··· 82 82 Indicates if the DSI controller is driving a panel which needs 83 83 2 DSI links. 84 84 85 + qcom,master-dsi: 86 + type: boolean 87 + description: | 88 + Indicates if the DSI controller is the master DSI controller when 89 + qcom,dual-dsi-mode enabled. 90 + 91 + qcom,sync-dual-dsi: 92 + type: boolean 93 + description: | 94 + Indicates if the DSI controller needs to sync the other DSI controller 95 + with MIPI DCS commands when qcom,dual-dsi-mode enabled. 96 + 85 97 assigned-clocks: 86 98 minItems: 2 87 99 maxItems: 4
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
··· 582 582 if (r) 583 583 amdgpu_fence_driver_force_completion(ring); 584 584 585 - if (ring->fence_drv.irq_src) 585 + if (!drm_dev_is_unplugged(adev_to_drm(adev)) && 586 + ring->fence_drv.irq_src) 586 587 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 587 588 ring->fence_drv.irq_type); 588 589
+7 -1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 8152 8152 case IP_VERSION(10, 3, 3): 8153 8153 case IP_VERSION(10, 3, 6): 8154 8154 case IP_VERSION(10, 3, 7): 8155 + if (!enable) 8156 + amdgpu_gfx_off_ctrl(adev, false); 8157 + 8155 8158 gfx_v10_cntl_pg(adev, enable); 8156 - amdgpu_gfx_off_ctrl(adev, enable); 8159 + 8160 + if (enable) 8161 + amdgpu_gfx_off_ctrl(adev, true); 8162 + 8157 8163 break; 8158 8164 default: 8159 8165 break;
+14 -5
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 4667 4667 uint64_t clock; 4668 4668 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4669 4669 4670 - amdgpu_gfx_off_ctrl(adev, false); 4671 - mutex_lock(&adev->gfx.gpu_clock_mutex); 4672 4670 if (amdgpu_sriov_vf(adev)) { 4671 + amdgpu_gfx_off_ctrl(adev, false); 4672 + mutex_lock(&adev->gfx.gpu_clock_mutex); 4673 4673 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4674 4674 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4675 4675 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4676 4676 if (clock_counter_hi_pre != clock_counter_hi_after) 4677 4677 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4678 + mutex_unlock(&adev->gfx.gpu_clock_mutex); 4679 + amdgpu_gfx_off_ctrl(adev, true); 4678 4680 } else { 4681 + preempt_disable(); 4679 4682 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4680 4683 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4681 4684 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4682 4685 if (clock_counter_hi_pre != clock_counter_hi_after) 4683 4686 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4687 + preempt_enable(); 4684 4688 } 4685 4689 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4686 - mutex_unlock(&adev->gfx.gpu_clock_mutex); 4687 - amdgpu_gfx_off_ctrl(adev, true); 4690 + 4688 4691 return clock; 4689 4692 } 4690 4693 ··· 5153 5150 break; 5154 5151 case IP_VERSION(11, 0, 1): 5155 5152 case IP_VERSION(11, 0, 4): 5153 + if (!enable) 5154 + amdgpu_gfx_off_ctrl(adev, false); 5155 + 5156 5156 gfx_v11_cntl_pg(adev, enable); 5157 - amdgpu_gfx_off_ctrl(adev, enable); 5157 + 5158 + if (enable) 5159 + amdgpu_gfx_off_ctrl(adev, true); 5160 + 5158 5161 break; 5159 5162 default: 5160 5163 break;
+16 -21
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 4003 4003 clock = clock_lo | (clock_hi << 32ULL); 4004 4004 break; 4005 4005 case IP_VERSION(9, 1, 0): 4006 - preempt_disable(); 4007 - clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4008 - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4009 - hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4010 - /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over 4011 - * roughly every 42 seconds. 4012 - */ 4013 - if (hi_check != clock_hi) { 4014 - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4015 - clock_hi = hi_check; 4016 - } 4017 - preempt_enable(); 4018 - clock = clock_lo | (clock_hi << 32ULL); 4019 - break; 4020 4006 case IP_VERSION(9, 2, 2): 4021 4007 preempt_disable(); 4022 - clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4023 - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4024 - hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4025 - /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over 4026 - * roughly every 42 seconds. 4027 - */ 4028 - if (hi_check != clock_hi) { 4008 + if (adev->rev_id >= 0x8) { 4009 + clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4029 4010 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4011 + hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4012 + } else { 4013 + clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4014 + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4015 + hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4016 + } 4017 + /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over 4018 + * roughly every 42 seconds. 4019 + */ 4020 + if (hi_check != clock_hi) { 4021 + if (adev->rev_id >= 0x8) 4022 + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4023 + else 4024 + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4030 4025 clock_hi = hi_check; 4031 4026 } 4032 4027 preempt_enable();
+20 -1
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
··· 31 31 #include "umc_v8_10.h" 32 32 #include "athub/athub_3_0_0_sh_mask.h" 33 33 #include "athub/athub_3_0_0_offset.h" 34 + #include "dcn/dcn_3_2_0_offset.h" 35 + #include "dcn/dcn_3_2_0_sh_mask.h" 34 36 #include "oss/osssys_6_0_0_offset.h" 35 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 36 38 #include "navi10_enum.h" ··· 548 546 549 547 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 550 548 { 551 - return 0; 549 + u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL); 550 + unsigned size; 551 + 552 + if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 553 + size = AMDGPU_VBIOS_VGA_ALLOCATION; 554 + } else { 555 + u32 viewport; 556 + u32 pitch; 557 + 558 + viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 559 + pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH); 560 + size = (REG_GET_FIELD(viewport, 561 + HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 562 + REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 563 + 4); 564 + } 565 + 566 + return size; 552 567 } 553 568 554 569 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
+18
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 733 733 return ret; 734 734 } 735 735 736 + /* 737 + * Explicitly notify PMFW the power mode the system in. Since 738 + * the PMFW may boot the ASIC with a different mode. 739 + * For those supporting ACDC switch via gpio, PMFW will 740 + * handle the switch automatically. Driver involvement 741 + * is unnecessary. 742 + */ 743 + if (!smu->dc_controlled_by_gpio) { 744 + ret = smu_set_power_source(smu, 745 + adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 746 + SMU_POWER_SOURCE_DC); 747 + if (ret) { 748 + dev_err(adev->dev, "Failed to switch to %s mode!\n", 749 + adev->pm.ac_power ? "AC" : "DC"); 750 + return ret; 751 + } 752 + } 753 + 736 754 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 737 755 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 738 756 return 0;
+1 -19
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
··· 3413 3413 return 0; 3414 3414 3415 3415 ret = navi10_run_umc_cdr_workaround(smu); 3416 - if (ret) { 3416 + if (ret) 3417 3417 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 3418 - return ret; 3419 - } 3420 - 3421 - if (!smu->dc_controlled_by_gpio) { 3422 - /* 3423 - * For Navi1X, manually switch it to AC mode as PMFW 3424 - * may boot it with DC mode. 3425 - */ 3426 - ret = smu_v11_0_set_power_source(smu, 3427 - adev->pm.ac_power ? 3428 - SMU_POWER_SOURCE_AC : 3429 - SMU_POWER_SOURCE_DC); 3430 - if (ret) { 3431 - dev_err(adev->dev, "Failed to switch to %s mode!\n", 3432 - adev->pm.ac_power ? "AC" : "DC"); 3433 - return ret; 3434 - } 3435 - } 3436 3418 3437 3419 return ret; 3438 3420 }
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
··· 1770 1770 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost, 1771 1771 .get_power_limit = smu_v13_0_7_get_power_limit, 1772 1772 .set_power_limit = smu_v13_0_set_power_limit, 1773 + .set_power_source = smu_v13_0_set_power_source, 1773 1774 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode, 1774 1775 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode, 1775 1776 .set_tool_table_location = smu_v13_0_set_tool_table_location,
+2 -2
drivers/gpu/drm/exynos/exynos_drm_g2d.h
··· 34 34 return -ENODEV; 35 35 } 36 36 37 - int g2d_open(struct drm_device *drm_dev, struct drm_file *file) 37 + static inline int g2d_open(struct drm_device *drm_dev, struct drm_file *file) 38 38 { 39 39 return 0; 40 40 } 41 41 42 - void g2d_close(struct drm_device *drm_dev, struct drm_file *file) 42 + static inline void g2d_close(struct drm_device *drm_dev, struct drm_file *file) 43 43 { } 44 44 #endif
+6 -4
drivers/gpu/drm/i915/display/intel_hdcp.c
··· 204 204 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 205 205 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 206 206 struct intel_hdcp *hdcp = &connector->hdcp; 207 - struct intel_gt *gt = dev_priv->media_gt; 208 - struct intel_gsc_uc *gsc = &gt->uc.gsc; 209 207 bool capable = false; 210 208 211 209 /* I915 support for HDCP2.2 */ ··· 211 213 return false; 212 214 213 215 /* If MTL+ make sure gsc is loaded and proxy is setup */ 214 - if (intel_hdcp_gsc_cs_required(dev_priv)) 215 - if (!intel_uc_fw_is_running(&gsc->fw)) 216 + if (intel_hdcp_gsc_cs_required(dev_priv)) { 217 + struct intel_gt *gt = dev_priv->media_gt; 218 + struct intel_gsc_uc *gsc = gt ? &gt->uc.gsc : NULL; 219 + 220 + if (!gsc || !intel_uc_fw_is_running(&gsc->fw)) 216 221 return false; 222 + } 217 223 218 224 /* MEI/GSC interface is solid depending on which is used */ 219 225 mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+8 -8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
··· 98 98 99 99 static const struct dpu_lm_cfg msm8998_lm[] = { 100 100 LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, 101 - &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), 101 + &msm8998_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 102 102 LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, 103 - &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), 103 + &msm8998_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 104 104 LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, 105 - &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), 105 + &msm8998_lm_sblk, PINGPONG_2, LM_5, 0), 106 106 LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, 107 107 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 108 108 LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, 109 109 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 110 110 LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, 111 - &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), 111 + &msm8998_lm_sblk, PINGPONG_3, LM_2, 0), 112 112 }; 113 113 114 114 static const struct dpu_pingpong_cfg msm8998_pp[] = { ··· 134 134 }; 135 135 136 136 static const struct dpu_intf_cfg msm8998_intf[] = { 137 - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 138 - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 139 - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 140 - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 137 + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 138 + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 139 + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 140 + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 141 141 }; 142 142 143 143 static const struct dpu_perf_cfg msm8998_perf_data = {
+2 -2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
··· 128 128 }; 129 129 130 130 static const struct dpu_pingpong_cfg sm8150_pp[] = { 131 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 131 + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, 132 132 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 133 133 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 134 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 134 + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, 135 135 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 136 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 137 137 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+2 -2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
··· 116 116 }; 117 117 118 118 static const struct dpu_pingpong_cfg sc8180x_pp[] = { 119 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 119 + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, 120 120 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 121 121 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 122 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 122 + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, 123 123 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 124 124 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 125 125 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+2 -2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
··· 129 129 }; 130 130 131 131 static const struct dpu_pingpong_cfg sm8250_pp[] = { 132 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 132 + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, 133 133 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 134 134 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 135 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 135 + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, 136 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 137 137 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 138 138 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+2 -2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
··· 80 80 }; 81 81 82 82 static const struct dpu_pingpong_cfg sc7180_pp[] = { 83 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1), 84 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), 83 + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, -1, -1), 84 + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk, -1, -1), 85 85 }; 86 86 87 87 static const struct dpu_intf_cfg sc7180_intf[] = {
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
··· 122 122 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 123 123 BIT(MDP_SSPP_TOP0_INTR2) | \ 124 124 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 125 - BIT(MDP_INTF0_INTR) | \ 126 125 BIT(MDP_INTF1_INTR), 127 126 }; 128 127
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
··· 112 112 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 113 113 BIT(MDP_SSPP_TOP0_INTR2) | \ 114 114 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 115 - BIT(MDP_INTF0_INTR) | \ 116 115 BIT(MDP_INTF1_INTR), 117 116 }; 118 117
+6 -6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
··· 127 127 }; 128 128 129 129 static const struct dpu_pingpong_cfg sm8350_pp[] = { 130 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, 130 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 131 131 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 132 132 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 133 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, 133 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 134 134 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 135 135 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 136 - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, 136 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 137 137 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 138 138 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 139 - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, 139 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 140 140 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 141 141 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 142 - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, 142 + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 143 143 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 144 144 -1), 145 - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, 145 + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 146 146 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 147 147 -1), 148 148 };
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
··· 87 87 }; 88 88 89 89 static const struct dpu_pingpong_cfg sc7280_pp[] = { 90 - PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), 91 - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 92 - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 93 - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 90 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), 91 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 92 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 93 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 94 94 }; 95 95 96 96 static const struct dpu_intf_cfg sc7280_intf[] = {
+12 -12
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
··· 121 121 }; 122 122 123 123 static const struct dpu_pingpong_cfg sc8280xp_pp[] = { 124 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, 125 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), 126 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, 127 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), 128 - PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk_te, 129 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), 130 - PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk_te, 131 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), 132 - PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk_te, 133 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), 134 - PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk_te, 135 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), 124 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 125 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), 126 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 127 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), 128 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 129 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), 130 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 131 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), 132 + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 133 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), 134 + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 135 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), 136 136 }; 137 137 138 138 static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
+8 -8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
··· 128 128 }; 129 129 /* FIXME: interrupts */ 130 130 static const struct dpu_pingpong_cfg sm8450_pp[] = { 131 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, 131 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 132 132 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 133 133 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 134 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, 134 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 135 135 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 136 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 137 - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, 137 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 138 138 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 139 139 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 140 - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, 140 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 141 141 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 142 142 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 143 - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, 143 + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 144 144 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 145 145 -1), 146 - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, 146 + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 147 147 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 148 148 -1), 149 - PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, 149 + PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk, 150 150 -1, 151 151 -1), 152 - PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, 152 + PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk, 153 153 -1, 154 154 -1), 155 155 };
+8 -8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
··· 132 132 &sm8150_dspp_sblk), 133 133 }; 134 134 static const struct dpu_pingpong_cfg sm8550_pp[] = { 135 - PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 135 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 136 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 137 137 -1), 138 - PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 138 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 139 139 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 140 140 -1), 141 - PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 141 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 142 142 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 143 143 -1), 144 - PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 144 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 145 145 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 146 146 -1), 147 - PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 147 + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 148 148 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 149 149 -1), 150 - PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 150 + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 151 151 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 152 152 -1), 153 - PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, 153 + PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, 154 154 -1, 155 155 -1), 156 - PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, 156 + PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, 157 157 -1, 158 158 -1), 159 159 };
+6 -11
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 491 491 .len = 0x20, .version = 0x20000}, 492 492 }; 493 493 494 - #define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 494 + #define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 495 495 {\ 496 496 .name = _name, .id = _id, \ 497 497 .base = _base, .len = 0, \ ··· 587 587 588 588 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 589 589 { 590 - .pps = 1088 * 1920 * 30, 590 + .pps = 1920 * 1080 * 30, 591 591 .ot_limit = 2, 592 592 }, 593 593 { 594 - .pps = 1088 * 1920 * 60, 595 - .ot_limit = 6, 594 + .pps = 1920 * 1080 * 60, 595 + .ot_limit = 4, 596 596 }, 597 597 { 598 598 .pps = 3840 * 2160 * 30, ··· 705 705 {.fl = 10, .lut = 0x1555b}, 706 706 {.fl = 11, .lut = 0x5555b}, 707 707 {.fl = 12, .lut = 0x15555b}, 708 - {.fl = 13, .lut = 0x55555b}, 709 - {.fl = 14, .lut = 0}, 710 - {.fl = 1, .lut = 0x1b}, 711 - {.fl = 0, .lut = 0} 708 + {.fl = 0, .lut = 0x55555b} 712 709 }; 713 710 714 711 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { ··· 727 730 {.fl = 10, .lut = 0x1aaff}, 728 731 {.fl = 11, .lut = 0x5aaff}, 729 732 {.fl = 12, .lut = 0x15aaff}, 730 - {.fl = 13, .lut = 0x55aaff}, 731 - {.fl = 1, .lut = 0x1aaff}, 732 - {.fl = 0, .lut = 0}, 733 + {.fl = 0, .lut = 0x55aaff}, 733 734 }; 734 735 735 736 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
+13 -10
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
··· 15 15 16 16 /* 17 17 * Register offsets in MDSS register file for the interrupt registers 18 - * w.r.t. to the MDP base 18 + * w.r.t. the MDP base 19 19 */ 20 20 #define MDP_SSPP_TOP0_OFF 0x0 21 21 #define MDP_INTF_0_OFF 0x6A000 ··· 24 24 #define MDP_INTF_3_OFF 0x6B800 25 25 #define MDP_INTF_4_OFF 0x6C000 26 26 #define MDP_INTF_5_OFF 0x6C800 27 + #define INTF_INTR_EN 0x1c0 28 + #define INTF_INTR_STATUS 0x1c4 29 + #define INTF_INTR_CLEAR 0x1c8 27 30 #define MDP_AD4_0_OFF 0x7C000 28 31 #define MDP_AD4_1_OFF 0x7D000 29 32 #define MDP_AD4_INTR_EN_OFF 0x41c 30 33 #define MDP_AD4_INTR_CLEAR_OFF 0x424 31 34 #define MDP_AD4_INTR_STATUS_OFF 0x420 32 - #define MDP_INTF_0_OFF_REV_7xxx 0x34000 33 - #define MDP_INTF_1_OFF_REV_7xxx 0x35000 34 - #define MDP_INTF_2_OFF_REV_7xxx 0x36000 35 - #define MDP_INTF_3_OFF_REV_7xxx 0x37000 36 - #define MDP_INTF_4_OFF_REV_7xxx 0x38000 37 - #define MDP_INTF_5_OFF_REV_7xxx 0x39000 38 - #define MDP_INTF_6_OFF_REV_7xxx 0x3a000 39 - #define MDP_INTF_7_OFF_REV_7xxx 0x3b000 40 - #define MDP_INTF_8_OFF_REV_7xxx 0x3c000 35 + #define MDP_INTF_0_OFF_REV_7xxx 0x34000 36 + #define MDP_INTF_1_OFF_REV_7xxx 0x35000 37 + #define MDP_INTF_2_OFF_REV_7xxx 0x36000 38 + #define MDP_INTF_3_OFF_REV_7xxx 0x37000 39 + #define MDP_INTF_4_OFF_REV_7xxx 0x38000 40 + #define MDP_INTF_5_OFF_REV_7xxx 0x39000 41 + #define MDP_INTF_6_OFF_REV_7xxx 0x3a000 42 + #define MDP_INTF_7_OFF_REV_7xxx 0x3b000 43 + #define MDP_INTF_8_OFF_REV_7xxx 0x3c000 41 44 42 45 /** 43 46 * struct dpu_intr_reg - array of DPU register sets
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
··· 56 56 #define INTF_TPG_RGB_MAPPING 0x11C 57 57 #define INTF_PROG_FETCH_START 0x170 58 58 #define INTF_PROG_ROT_START 0x174 59 - 60 - #define INTF_FRAME_LINE_COUNT_EN 0x0A8 61 - #define INTF_FRAME_COUNT 0x0AC 62 - #define INTF_LINE_COUNT 0x0B0 63 - 64 59 #define INTF_MUX 0x25C 65 60 #define INTF_STATUS 0x26C 66 61
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
··· 61 61 for (i = 0; i < m->wb_count; i++) { 62 62 if (wb == m->wb[i].id) { 63 63 b->blk_addr = addr + m->wb[i].base; 64 + b->log_mask = DPU_DBG_MASK_WB; 64 65 return &m->wb[i]; 65 66 } 66 67 }
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
··· 21 21 #define HIST_INTR_EN 0x01c 22 22 #define HIST_INTR_STATUS 0x020 23 23 #define HIST_INTR_CLEAR 0x024 24 - #define INTF_INTR_EN 0x1C0 25 - #define INTF_INTR_STATUS 0x1C4 26 - #define INTF_INTR_CLEAR 0x1C8 27 24 #define SPLIT_DISPLAY_EN 0x2F4 28 25 #define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8 29 26 #define DSPP_IGC_COLOR0_RAM_LUTN 0x300
+12
drivers/gpu/drm/msm/dp/dp_audio.c
··· 593 593 .i2s = 1, 594 594 }; 595 595 596 + void dp_unregister_audio_driver(struct device *dev, struct dp_audio *dp_audio) 597 + { 598 + struct dp_audio_private *audio_priv; 599 + 600 + audio_priv = container_of(dp_audio, struct dp_audio_private, dp_audio); 601 + 602 + if (audio_priv->audio_pdev) { 603 + platform_device_unregister(audio_priv->audio_pdev); 604 + audio_priv->audio_pdev = NULL; 605 + } 606 + } 607 + 596 608 int dp_register_audio_driver(struct device *dev, 597 609 struct dp_audio *dp_audio) 598 610 {
+2
drivers/gpu/drm/msm/dp/dp_audio.h
··· 53 53 int dp_register_audio_driver(struct device *dev, 54 54 struct dp_audio *dp_audio); 55 55 56 + void dp_unregister_audio_driver(struct device *dev, struct dp_audio *dp_audio); 57 + 56 58 /** 57 59 * dp_audio_put() 58 60 *
+1
drivers/gpu/drm/msm/dp/dp_display.c
··· 326 326 kthread_stop(dp->ev_tsk); 327 327 328 328 dp_power_client_deinit(dp->power); 329 + dp_unregister_audio_driver(dev, dp->audio); 329 330 dp_aux_unregister(dp->aux); 330 331 dp->drm_dev = NULL; 331 332 dp->aux->drm_dev = NULL;
+2
drivers/gpu/drm/msm/msm_atomic.c
··· 155 155 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 156 156 if (drm_atomic_crtc_needs_modeset(crtc_state)) 157 157 return false; 158 + if (!crtc_state->active) 159 + return false; 158 160 if (++num_crtcs > 1) 159 161 return false; 160 162 *async_crtc = crtc;
+8 -14
drivers/gpu/drm/msm/msm_gem.c
··· 219 219 } 220 220 } 221 221 222 - static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj) 222 + static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj, 223 + unsigned madv) 223 224 { 224 225 struct msm_drm_private *priv = obj->dev->dev_private; 225 226 struct msm_gem_object *msm_obj = to_msm_bo(obj); ··· 228 227 229 228 msm_gem_assert_locked(obj); 230 229 231 - if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) { 230 + if (GEM_WARN_ON(msm_obj->madv > madv)) { 231 + DRM_DEV_ERROR(obj->dev->dev, "Invalid madv state: %u vs %u\n", 232 + msm_obj->madv, madv); 232 233 return ERR_PTR(-EBUSY); 233 234 } 234 235 ··· 251 248 struct page **p; 252 249 253 250 msm_gem_lock(obj); 254 - p = msm_gem_pin_pages_locked(obj); 251 + p = msm_gem_pin_pages_locked(obj, MSM_MADV_WILLNEED); 255 252 msm_gem_unlock(obj); 256 253 257 254 return p; ··· 476 473 477 474 msm_gem_assert_locked(obj); 478 475 479 - if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) 480 - return -EBUSY; 481 - 482 - pages = msm_gem_pin_pages_locked(obj); 476 + pages = msm_gem_pin_pages_locked(obj, MSM_MADV_WILLNEED); 483 477 if (IS_ERR(pages)) 484 478 return PTR_ERR(pages); 485 479 ··· 699 699 if (obj->import_attach) 700 700 return ERR_PTR(-ENODEV); 701 701 702 - if (GEM_WARN_ON(msm_obj->madv > madv)) { 703 - DRM_DEV_ERROR(obj->dev->dev, "Invalid madv state: %u vs %u\n", 704 - msm_obj->madv, madv); 705 - return ERR_PTR(-EBUSY); 706 - } 707 - 708 - pages = msm_gem_pin_pages_locked(obj); 702 + pages = msm_gem_pin_pages_locked(obj, madv); 709 703 if (IS_ERR(pages)) 710 704 return ERR_CAST(pages); 711 705
+18 -7
drivers/gpu/drm/msm/msm_gem_submit.c
··· 722 722 struct msm_drm_private *priv = dev->dev_private; 723 723 struct drm_msm_gem_submit *args = data; 724 724 struct msm_file_private *ctx = file->driver_priv; 725 - struct msm_gem_submit *submit; 725 + struct msm_gem_submit *submit = NULL; 726 726 struct msm_gpu *gpu = priv->gpu; 727 727 struct msm_gpu_submitqueue *queue; 728 728 struct msm_ringbuffer *ring; ··· 769 769 out_fence_fd = get_unused_fd_flags(O_CLOEXEC); 770 770 if (out_fence_fd < 0) { 771 771 ret = out_fence_fd; 772 - return ret; 772 + goto out_post_unlock; 773 773 } 774 774 } 775 775 776 776 submit = submit_create(dev, gpu, queue, args->nr_bos, args->nr_cmds); 777 - if (IS_ERR(submit)) 778 - return PTR_ERR(submit); 777 + if (IS_ERR(submit)) { 778 + ret = PTR_ERR(submit); 779 + goto out_post_unlock; 780 + } 779 781 780 782 trace_msm_gpu_submit(pid_nr(submit->pid), ring->id, submit->ident, 781 783 args->nr_bos, args->nr_cmds); ··· 964 962 if (has_ww_ticket) 965 963 ww_acquire_fini(&submit->ticket); 966 964 out_unlock: 967 - if (ret && (out_fence_fd >= 0)) 968 - put_unused_fd(out_fence_fd); 969 965 mutex_unlock(&queue->lock); 970 966 out_post_unlock: 971 - msm_gem_submit_put(submit); 967 + if (ret && (out_fence_fd >= 0)) 968 + put_unused_fd(out_fence_fd); 969 + 970 + if (!IS_ERR_OR_NULL(submit)) { 971 + msm_gem_submit_put(submit); 972 + } else { 973 + /* 974 + * If the submit hasn't yet taken ownership of the queue 975 + * then we need to drop the reference ourself: 976 + */ 977 + msm_submitqueue_put(queue); 978 + } 972 979 if (!IS_ERR_OR_NULL(post_deps)) { 973 980 for (i = 0; i < args->nr_out_syncobjs; ++i) { 974 981 kfree(post_deps[i].chain);
+7 -2
drivers/gpu/drm/msm/msm_iommu.c
··· 234 234 /* Get the pagetable configuration from the domain */ 235 235 if (adreno_smmu->cookie) 236 236 ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie); 237 - if (!ttbr1_cfg) 237 + 238 + /* 239 + * If you hit this WARN_ONCE() you are probably missing an entry in 240 + * qcom_smmu_impl_of_match[] in arm-smmu-qcom.c 241 + */ 242 + if (WARN_ONCE(!ttbr1_cfg, "No per-process page tables")) 238 243 return ERR_PTR(-ENODEV); 239 244 240 245 pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL); ··· 415 410 struct msm_mmu *mmu; 416 411 417 412 mmu = msm_iommu_new(dev, quirks); 418 - if (IS_ERR(mmu)) 413 + if (IS_ERR_OR_NULL(mmu)) 419 414 return mmu; 420 415 421 416 iommu = to_msm_iommu(mmu);
+10
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
··· 517 517 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data }, 518 518 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data }, 519 519 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data }, 520 + { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data }, 520 521 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data }, 521 522 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data }, 522 523 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data }, ··· 561 560 match = of_match_node(qcom_smmu_impl_of_match, np); 562 561 if (match) 563 562 return qcom_smmu_create(smmu, match->data); 563 + 564 + /* 565 + * If you hit this WARN_ON() you are missing an entry in the 566 + * qcom_smmu_impl_of_match[] table, and GPU per-process page- 567 + * tables will be broken. 568 + */ 569 + WARN(of_device_is_compatible(np, "qcom,adreno-smmu"), 570 + "Missing qcom_smmu_impl_of_match entry for: %s", 571 + dev_name(smmu->dev)); 564 572 565 573 return smmu; 566 574 }