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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
"Nothing frightening this time, just smaller fixes in a number of
places.

The other changes contained here are:

MAINTAINERS file updates:

- The mach-gemini maintainer is back in action and has a new git tree

- Krzysztof Kozlowski has volunteered to be a new co-maintainer for
the samsung platforms

- updates to the files that belong to Marvell mvebu

Bug fixes:

- The largest changes are on omap2, but are only to avoid some
harmless warnings and to fix reset on omap4

- a small regression fix on tegra

- multiple fixes for incorrect IRQ affinity on vexpress

- the missing system controller on arm64 juno is added

- one revert of a patch that was accidentally applied twice for
mach-rockchip

- two clock related DT fixes for mvebu

- a workaround for suspend with old DT binaries on new exynos kernels

- Another fix for suspend on exynos, needs to be backported"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits)
MAINTAINERS: Add dts entries for some of the Marvell SoCs
MAINTAINERS: ARM: EXYNOS: Add Krzysztof Kozlowski as co-maintainer
ARM: EXYNOS: Use of_machine_is_compatible instead of soc_is_exynos4
ARM: EXYNOS: Fix failed second suspend on Exynos4
Revert "ARM: rockchip: fix undefined instruction of reset_ctrl_regs"
ARM: EXYNOS: Fix dereference of ERR_PTR returned by of_genpd_get_from_provider
ARM: EXYNOS: Don't try to initialize suspend on old DT
ARM: dts: Add keep-power-in-suspend to WiFi SDIO node for Peach Boards
ARM: gemini: fix compiler warning due wrong data type
ARM: vexpress/tc2: Add interrupt-affinity to the PMU node
ARM: vexpress/ca9: Add interrupt-affinity to the PMU node
ARM: vexpress/ca9: Add unified-cache property to l2 cache node
ARM64: juno: add sp810 support and fix sp804 clock frequency
ARM: Gemini: Maintainers update
ARM: OMAP2+: Remove bogus struct clk comparison for timer clock
ARM: dove: Add clock-names to CuBox Si5351 clk generator
ARM: AM33xx+: hwmod: re-use omap4 implementations for reset functionality
ARM: OMAP4+: PRM: add support for passing status register/bit info to reset
ARM: AM43xx: hwmod: add VPFE hwmod entries
ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs
...

Linus Torvalds d6610270 73786683

+199 -165
+11 -2
MAINTAINERS
··· 974 974 ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE 975 975 M: Hans Ulli Kroll <ulli.kroll@googlemail.com> 976 976 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 977 - T: git git://git.berlios.de/gemini-board 977 + T: git git://github.com/ulli-kroll/linux.git 978 978 S: Maintained 979 979 F: arch/arm/mach-gemini/ 980 980 ··· 1193 1193 M: Philipp Zabel <philipp.zabel@gmail.com> 1194 1194 S: Maintained 1195 1195 1196 - ARM/Marvell Armada 370 and Armada XP SOC support 1196 + ARM/Marvell Kirkwood and Armada 370, 375, 38x, XP SOC support 1197 1197 M: Jason Cooper <jason@lakedaemon.net> 1198 1198 M: Andrew Lunn <andrew@lunn.ch> 1199 1199 M: Gregory Clement <gregory.clement@free-electrons.com> ··· 1202 1202 S: Maintained 1203 1203 F: arch/arm/mach-mvebu/ 1204 1204 F: drivers/rtc/rtc-armada38x.c 1205 + F: arch/arm/boot/dts/armada* 1206 + F: arch/arm/boot/dts/kirkwood* 1207 + 1205 1208 1206 1209 ARM/Marvell Berlin SoC support 1207 1210 M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 1208 1211 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1209 1212 S: Maintained 1210 1213 F: arch/arm/mach-berlin/ 1214 + F: arch/arm/boot/dts/berlin* 1215 + 1211 1216 1212 1217 ARM/Marvell Dove/MV78xx0/Orion SOC support 1213 1218 M: Jason Cooper <jason@lakedaemon.net> ··· 1225 1220 F: arch/arm/mach-mv78xx0/ 1226 1221 F: arch/arm/mach-orion5x/ 1227 1222 F: arch/arm/plat-orion/ 1223 + F: arch/arm/boot/dts/dove* 1224 + F: arch/arm/boot/dts/orion5x* 1225 + 1228 1226 1229 1227 ARM/Orion SoC/Technologic Systems TS-78xx platform support 1230 1228 M: Alexander Clouter <alex@digriz.org.uk> ··· 1379 1371 1380 1372 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES 1381 1373 M: Kukjin Kim <kgene@kernel.org> 1374 + M: Krzysztof Kozlowski <k.kozlowski@samsung.com> 1382 1375 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1383 1376 L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) 1384 1377 S: Maintained
+1 -1
arch/arm/boot/dts/armada-375.dtsi
··· 69 69 mainpll: mainpll { 70 70 compatible = "fixed-clock"; 71 71 #clock-cells = <0>; 72 - clock-frequency = <2000000000>; 72 + clock-frequency = <1000000000>; 73 73 }; 74 74 /* 25 MHz reference crystal */ 75 75 refclk: oscillator {
+1 -1
arch/arm/boot/dts/armada-38x.dtsi
··· 585 585 mainpll: mainpll { 586 586 compatible = "fixed-clock"; 587 587 #clock-cells = <0>; 588 - clock-frequency = <2000000000>; 588 + clock-frequency = <1000000000>; 589 589 }; 590 590 591 591 /* 25 MHz reference crystal */
+1 -1
arch/arm/boot/dts/armada-39x.dtsi
··· 502 502 mainpll: mainpll { 503 503 compatible = "fixed-clock"; 504 504 #clock-cells = <0>; 505 - clock-frequency = <2000000000>; 505 + clock-frequency = <1000000000>; 506 506 }; 507 507 }; 508 508 };
+1
arch/arm/boot/dts/dove-cubox.dts
··· 87 87 88 88 /* connect xtal input to 25MHz reference */ 89 89 clocks = <&ref25>; 90 + clock-names = "xtal"; 90 91 91 92 /* connect xtal input as source of pll0 and pll1 */ 92 93 silabs,pll-source = <0 0>, <1 0>;
+1
arch/arm/boot/dts/exynos5420-peach-pit.dts
··· 711 711 num-slots = <1>; 712 712 broken-cd; 713 713 cap-sdio-irq; 714 + keep-power-in-suspend; 714 715 card-detect-delay = <200>; 715 716 clock-frequency = <400000000>; 716 717 samsung,dw-mshc-ciu-div = <1>;
+1
arch/arm/boot/dts/exynos5800-peach-pi.dts
··· 674 674 num-slots = <1>; 675 675 broken-cd; 676 676 cap-sdio-irq; 677 + keep-power-in-suspend; 677 678 card-detect-delay = <200>; 678 679 clock-frequency = <400000000>; 679 680 samsung,dw-mshc-ciu-div = <1>;
+4 -4
arch/arm/boot/dts/tegra124.dtsi
··· 826 826 <&tegra_car TEGRA124_CLK_PLL_U>, 827 827 <&tegra_car TEGRA124_CLK_USBD>; 828 828 clock-names = "reg", "pll_u", "utmi-pads"; 829 - resets = <&tegra_car 59>, <&tegra_car 22>; 829 + resets = <&tegra_car 22>, <&tegra_car 22>; 830 830 reset-names = "usb", "utmi-pads"; 831 831 nvidia,hssync-start-delay = <0>; 832 832 nvidia,idle-wait-delay = <17>; ··· 838 838 nvidia,hssquelch-level = <2>; 839 839 nvidia,hsdiscon-level = <5>; 840 840 nvidia,xcvr-hsslew = <12>; 841 + nvidia,has-utmi-pad-registers; 841 842 status = "disabled"; 842 843 }; 843 844 ··· 863 862 <&tegra_car TEGRA124_CLK_PLL_U>, 864 863 <&tegra_car TEGRA124_CLK_USBD>; 865 864 clock-names = "reg", "pll_u", "utmi-pads"; 866 - resets = <&tegra_car 22>, <&tegra_car 22>; 865 + resets = <&tegra_car 58>, <&tegra_car 22>; 867 866 reset-names = "usb", "utmi-pads"; 868 867 nvidia,hssync-start-delay = <0>; 869 868 nvidia,idle-wait-delay = <17>; ··· 875 874 nvidia,hssquelch-level = <2>; 876 875 nvidia,hsdiscon-level = <5>; 877 876 nvidia,xcvr-hsslew = <12>; 878 - nvidia,has-utmi-pad-registers; 879 877 status = "disabled"; 880 878 }; 881 879 ··· 899 899 <&tegra_car TEGRA124_CLK_PLL_U>, 900 900 <&tegra_car TEGRA124_CLK_USBD>; 901 901 clock-names = "reg", "pll_u", "utmi-pads"; 902 - resets = <&tegra_car 58>, <&tegra_car 22>; 902 + resets = <&tegra_car 59>, <&tegra_car 22>; 903 903 reset-names = "usb", "utmi-pads"; 904 904 nvidia,hssync-start-delay = <0>; 905 905 nvidia,idle-wait-delay = <17>;
+1
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
··· 191 191 compatible = "arm,cortex-a15-pmu"; 192 192 interrupts = <0 68 4>, 193 193 <0 69 4>; 194 + interrupt-affinity = <&cpu0>, <&cpu1>; 194 195 }; 195 196 196 197 oscclk6a: oscclk6a {
+7 -4
arch/arm/boot/dts/vexpress-v2p-ca9.dts
··· 33 33 #address-cells = <1>; 34 34 #size-cells = <0>; 35 35 36 - cpu@0 { 36 + A9_0: cpu@0 { 37 37 device_type = "cpu"; 38 38 compatible = "arm,cortex-a9"; 39 39 reg = <0>; 40 40 next-level-cache = <&L2>; 41 41 }; 42 42 43 - cpu@1 { 43 + A9_1: cpu@1 { 44 44 device_type = "cpu"; 45 45 compatible = "arm,cortex-a9"; 46 46 reg = <1>; 47 47 next-level-cache = <&L2>; 48 48 }; 49 49 50 - cpu@2 { 50 + A9_2: cpu@2 { 51 51 device_type = "cpu"; 52 52 compatible = "arm,cortex-a9"; 53 53 reg = <2>; 54 54 next-level-cache = <&L2>; 55 55 }; 56 56 57 - cpu@3 { 57 + A9_3: cpu@3 { 58 58 device_type = "cpu"; 59 59 compatible = "arm,cortex-a9"; 60 60 reg = <3>; ··· 170 170 compatible = "arm,pl310-cache"; 171 171 reg = <0x1e00a000 0x1000>; 172 172 interrupts = <0 43 4>; 173 + cache-unified; 173 174 cache-level = <2>; 174 175 arm,data-latency = <1 1 1>; 175 176 arm,tag-latency = <1 1 1>; ··· 182 181 <0 61 4>, 183 182 <0 62 4>, 184 183 <0 63 4>; 184 + interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; 185 + 185 186 }; 186 187 187 188 dcc {
+2
arch/arm/mach-exynos/common.h
··· 159 159 160 160 extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data; 161 161 162 + extern void exynos_set_delayed_reset_assertion(bool enable); 163 + 162 164 extern void s5p_init_cpu(void __iomem *cpuid_addr); 163 165 extern unsigned int samsung_rev(void); 164 166 extern void __iomem *cpu_boot_reg_base(void);
+27
arch/arm/mach-exynos/exynos.c
··· 167 167 } 168 168 169 169 /* 170 + * Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code 171 + * and suspend. 172 + * 173 + * This is necessary only on Exynos4 SoCs. When system is running 174 + * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down 175 + * feature could properly detect global idle state when secondary CPU is 176 + * powered down. 177 + * 178 + * However this should not be set when such system is going into suspend. 179 + */ 180 + void exynos_set_delayed_reset_assertion(bool enable) 181 + { 182 + if (of_machine_is_compatible("samsung,exynos4")) { 183 + unsigned int tmp, core_id; 184 + 185 + for (core_id = 0; core_id < num_possible_cpus(); core_id++) { 186 + tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id)); 187 + if (enable) 188 + tmp |= S5P_USE_DELAYED_RESET_ASSERTION; 189 + else 190 + tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION); 191 + pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id)); 192 + } 193 + } 194 + } 195 + 196 + /* 170 197 * Apparently, these SoCs are not able to wake-up from suspend using 171 198 * the PMU. Too bad. Should they suddenly become capable of such a 172 199 * feat, the matches below should be moved to suspend.c.
+2 -37
arch/arm/mach-exynos/platsmp.c
··· 34 34 35 35 extern void exynos4_secondary_startup(void); 36 36 37 - /* 38 - * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs 39 - * during hot-(un)plugging CPUx. 40 - * 41 - * The feature can be cleared safely during first boot of secondary CPU. 42 - * 43 - * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering 44 - * down a CPU so the CPU idle clock down feature could properly detect global 45 - * idle state when CPUx is off. 46 - */ 47 - static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable) 48 - { 49 - if (soc_is_exynos4()) { 50 - unsigned int tmp; 51 - 52 - tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id)); 53 - if (enable) 54 - tmp |= S5P_USE_DELAYED_RESET_ASSERTION; 55 - else 56 - tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION); 57 - pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id)); 58 - } 59 - } 60 - 61 37 #ifdef CONFIG_HOTPLUG_CPU 62 38 static inline void cpu_leave_lowpower(u32 core_id) 63 39 { ··· 49 73 : "=&r" (v) 50 74 : "Ir" (CR_C), "Ir" (0x40) 51 75 : "cc"); 52 - 53 - exynos_set_delayed_reset_assertion(core_id, false); 54 76 } 55 77 56 78 static inline void platform_do_lowpower(unsigned int cpu, int *spurious) ··· 60 86 61 87 /* Turn the CPU off on next WFI instruction. */ 62 88 exynos_cpu_power_down(core_id); 63 - 64 - /* 65 - * Exynos4 SoCs require setting 66 - * USE_DELAYED_RESET_ASSERTION so the CPU idle 67 - * clock down feature could properly detect 68 - * global idle state when CPUx is off. 69 - */ 70 - exynos_set_delayed_reset_assertion(core_id, true); 71 89 72 90 wfi(); 73 91 ··· 337 371 udelay(10); 338 372 } 339 373 340 - /* No harm if this is called during first boot of secondary CPU */ 341 - exynos_set_delayed_reset_assertion(core_id, false); 342 - 343 374 /* 344 375 * now the secondary core is starting up let it run its 345 376 * calibrations, then wait for it to finish ··· 382 419 int i; 383 420 384 421 exynos_sysram_init(); 422 + 423 + exynos_set_delayed_reset_assertion(true); 385 424 386 425 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 387 426 scu_enable(scu_base_addr());
+2 -2
arch/arm/mach-exynos/pm_domains.c
··· 188 188 args.np = np; 189 189 args.args_count = 0; 190 190 child_domain = of_genpd_get_from_provider(&args); 191 - if (!child_domain) 191 + if (IS_ERR(child_domain)) 192 192 continue; 193 193 194 194 if (of_parse_phandle_with_args(np, "power-domains", ··· 196 196 continue; 197 197 198 198 parent_domain = of_genpd_get_from_provider(&args); 199 - if (!parent_domain) 199 + if (IS_ERR(parent_domain)) 200 200 continue; 201 201 202 202 if (pm_genpd_add_subdomain(parent_domain, child_domain))
+6 -1
arch/arm/mach-exynos/suspend.c
··· 342 342 343 343 static void exynos_pm_prepare(void) 344 344 { 345 + exynos_set_delayed_reset_assertion(false); 346 + 345 347 /* Set wake-up mask registers */ 346 348 exynos_pm_set_wakeup_mask(); 347 349 ··· 484 482 485 483 /* Clear SLEEP mode set in INFORM1 */ 486 484 pmu_raw_writel(0x0, S5P_INFORM1); 485 + exynos_set_delayed_reset_assertion(true); 487 486 } 488 487 489 488 static void exynos3250_pm_resume(void) ··· 726 723 return; 727 724 } 728 725 729 - if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) 726 + if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { 730 727 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 728 + return; 729 + } 731 730 732 731 pm_data = (const struct exynos_pm_data *) match->data; 733 732
+3 -1
arch/arm/mach-gemini/common.h
··· 12 12 #ifndef __GEMINI_COMMON_H__ 13 13 #define __GEMINI_COMMON_H__ 14 14 15 + #include <linux/reboot.h> 16 + 15 17 struct mtd_partition; 16 18 17 19 extern void gemini_map_io(void); ··· 28 26 struct mtd_partition *parts, 29 27 unsigned int nr_parts); 30 28 31 - extern void gemini_restart(char mode, const char *cmd); 29 + extern void gemini_restart(enum reboot_mode mode, const char *cmd); 32 30 33 31 #endif /* __GEMINI_COMMON_H__ */
+3 -1
arch/arm/mach-gemini/reset.c
··· 14 14 #include <mach/hardware.h> 15 15 #include <mach/global_reg.h> 16 16 17 - void gemini_restart(char mode, const char *cmd) 17 + #include "common.h" 18 + 19 + void gemini_restart(enum reboot_mode mode, const char *cmd) 18 20 { 19 21 __raw_writel(RESET_GLOBAL | RESET_CPU1, 20 22 IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
+14 -54
arch/arm/mach-omap2/omap_hwmod.c
··· 171 171 */ 172 172 #define LINKS_PER_OCP_IF 2 173 173 174 + /* 175 + * Address offset (in bytes) between the reset control and the reset 176 + * status registers: 4 bytes on OMAP4 177 + */ 178 + #define OMAP4_RST_CTRL_ST_OFFSET 4 179 + 174 180 /** 175 181 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations 176 182 * @enable_module: function to enable a module (via MODULEMODE) ··· 3022 3016 if (ohri->st_shift) 3023 3017 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", 3024 3018 oh->name, ohri->name); 3025 - return omap_prm_deassert_hardreset(ohri->rst_shift, 0, 3019 + return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift, 3026 3020 oh->clkdm->pwrdm.ptr->prcm_partition, 3027 3021 oh->clkdm->pwrdm.ptr->prcm_offs, 3028 - oh->prcm.omap4.rstctrl_offs, 0); 3022 + oh->prcm.omap4.rstctrl_offs, 3023 + oh->prcm.omap4.rstctrl_offs + 3024 + OMAP4_RST_CTRL_ST_OFFSET); 3029 3025 } 3030 3026 3031 3027 /** ··· 3056 3048 } 3057 3049 3058 3050 /** 3059 - * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args 3060 - * @oh: struct omap_hwmod * to assert hardreset 3061 - * @ohri: hardreset line data 3062 - * 3063 - * Call am33xx_prminst_assert_hardreset() with parameters extracted 3064 - * from the hwmod @oh and the hardreset line data @ohri. Only 3065 - * intended for use as an soc_ops function pointer. Passes along the 3066 - * return value from am33xx_prminst_assert_hardreset(). XXX This 3067 - * function is scheduled for removal when the PRM code is moved into 3068 - * drivers/. 3069 - */ 3070 - static int _am33xx_assert_hardreset(struct omap_hwmod *oh, 3071 - struct omap_hwmod_rst_info *ohri) 3072 - 3073 - { 3074 - return omap_prm_assert_hardreset(ohri->rst_shift, 0, 3075 - oh->clkdm->pwrdm.ptr->prcm_offs, 3076 - oh->prcm.omap4.rstctrl_offs); 3077 - } 3078 - 3079 - /** 3080 3051 * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args 3081 3052 * @oh: struct omap_hwmod * to deassert hardreset 3082 3053 * @ohri: hardreset line data ··· 3070 3083 static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, 3071 3084 struct omap_hwmod_rst_info *ohri) 3072 3085 { 3073 - return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, 3086 + return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 3087 + oh->clkdm->pwrdm.ptr->prcm_partition, 3074 3088 oh->clkdm->pwrdm.ptr->prcm_offs, 3075 3089 oh->prcm.omap4.rstctrl_offs, 3076 3090 oh->prcm.omap4.rstst_offs); 3077 - } 3078 - 3079 - /** 3080 - * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args 3081 - * @oh: struct omap_hwmod * to test hardreset 3082 - * @ohri: hardreset line data 3083 - * 3084 - * Call am33xx_prminst_is_hardreset_asserted() with parameters 3085 - * extracted from the hwmod @oh and the hardreset line data @ohri. 3086 - * Only intended for use as an soc_ops function pointer. Passes along 3087 - * the return value from am33xx_prminst_is_hardreset_asserted(). XXX 3088 - * This function is scheduled for removal when the PRM code is moved 3089 - * into drivers/. 3090 - */ 3091 - static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, 3092 - struct omap_hwmod_rst_info *ohri) 3093 - { 3094 - return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0, 3095 - oh->clkdm->pwrdm.ptr->prcm_offs, 3096 - oh->prcm.omap4.rstctrl_offs); 3097 3091 } 3098 3092 3099 3093 /* Public functions */ ··· 3876 3908 soc_ops.init_clkdm = _init_clkdm; 3877 3909 soc_ops.update_context_lost = _omap4_update_context_lost; 3878 3910 soc_ops.get_context_lost = _omap4_get_context_lost; 3879 - } else if (soc_is_am43xx()) { 3911 + } else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) { 3880 3912 soc_ops.enable_module = _omap4_enable_module; 3881 3913 soc_ops.disable_module = _omap4_disable_module; 3882 3914 soc_ops.wait_target_ready = _omap4_wait_target_ready; 3883 3915 soc_ops.assert_hardreset = _omap4_assert_hardreset; 3884 - soc_ops.deassert_hardreset = _omap4_deassert_hardreset; 3885 - soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; 3886 - soc_ops.init_clkdm = _init_clkdm; 3887 - } else if (cpu_is_ti816x() || soc_is_am33xx()) { 3888 - soc_ops.enable_module = _omap4_enable_module; 3889 - soc_ops.disable_module = _omap4_disable_module; 3890 - soc_ops.wait_target_ready = _omap4_wait_target_ready; 3891 - soc_ops.assert_hardreset = _am33xx_assert_hardreset; 3892 3916 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; 3893 - soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; 3917 + soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; 3894 3918 soc_ops.init_clkdm = _init_clkdm; 3895 3919 } else { 3896 3920 WARN(1, "omap_hwmod: unknown SoC type\n");
+70
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
··· 544 544 }, 545 545 }; 546 546 547 + static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = { 548 + .rev_offs = 0x0, 549 + .sysc_offs = 0x104, 550 + .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE, 551 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 552 + MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO), 553 + .sysc_fields = &omap_hwmod_sysc_type2, 554 + }; 555 + 556 + static struct omap_hwmod_class am43xx_vpfe_hwmod_class = { 557 + .name = "vpfe", 558 + .sysc = &am43xx_vpfe_sysc, 559 + }; 560 + 561 + static struct omap_hwmod am43xx_vpfe0_hwmod = { 562 + .name = "vpfe0", 563 + .class = &am43xx_vpfe_hwmod_class, 564 + .clkdm_name = "l3s_clkdm", 565 + .prcm = { 566 + .omap4 = { 567 + .modulemode = MODULEMODE_SWCTRL, 568 + .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET, 569 + }, 570 + }, 571 + }; 572 + 573 + static struct omap_hwmod am43xx_vpfe1_hwmod = { 574 + .name = "vpfe1", 575 + .class = &am43xx_vpfe_hwmod_class, 576 + .clkdm_name = "l3s_clkdm", 577 + .prcm = { 578 + .omap4 = { 579 + .modulemode = MODULEMODE_SWCTRL, 580 + .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET, 581 + }, 582 + }, 583 + }; 584 + 547 585 /* Interfaces */ 548 586 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { 549 587 .master = &am33xx_l3_main_hwmod, ··· 863 825 .user = OCP_USER_MPU | OCP_USER_SDMA, 864 826 }; 865 827 828 + static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = { 829 + .master = &am43xx_vpfe0_hwmod, 830 + .slave = &am33xx_l3_main_hwmod, 831 + .clk = "l3_gclk", 832 + .user = OCP_USER_MPU | OCP_USER_SDMA, 833 + }; 834 + 835 + static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = { 836 + .master = &am43xx_vpfe1_hwmod, 837 + .slave = &am33xx_l3_main_hwmod, 838 + .clk = "l3_gclk", 839 + .user = OCP_USER_MPU | OCP_USER_SDMA, 840 + }; 841 + 842 + static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = { 843 + .master = &am33xx_l4_ls_hwmod, 844 + .slave = &am43xx_vpfe0_hwmod, 845 + .clk = "l4ls_gclk", 846 + .user = OCP_USER_MPU | OCP_USER_SDMA, 847 + }; 848 + 849 + static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = { 850 + .master = &am33xx_l4_ls_hwmod, 851 + .slave = &am43xx_vpfe1_hwmod, 852 + .clk = "l4ls_gclk", 853 + .user = OCP_USER_MPU | OCP_USER_SDMA, 854 + }; 855 + 866 856 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { 867 857 &am33xx_l4_wkup__synctimer, 868 858 &am43xx_l4_ls__timer8, ··· 991 925 &am43xx_l4_ls__dss_dispc, 992 926 &am43xx_l4_ls__dss_rfbi, 993 927 &am43xx_l4_ls__hdq1w, 928 + &am43xx_l3__vpfe0, 929 + &am43xx_l3__vpfe1, 930 + &am43xx_l4_ls__vpfe0, 931 + &am43xx_l4_ls__vpfe1, 994 932 NULL, 995 933 }; 996 934
+2 -1
arch/arm/mach-omap2/prcm43xx.h
··· 144 144 #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 145 145 #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 146 146 #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0 147 - 147 + #define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068 148 + #define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070 148 149 #endif
+7 -13
arch/arm/mach-omap2/prminst44xx.c
··· 87 87 return v; 88 88 } 89 89 90 - /* 91 - * Address offset (in bytes) between the reset control and the reset 92 - * status registers: 4 bytes on OMAP4 93 - */ 94 - #define OMAP4_RST_CTRL_ST_OFFSET 4 95 - 96 90 /** 97 91 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of 98 92 * submodules contained in the hwmod module ··· 135 141 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and 136 142 * wait 137 143 * @shift: register bit shift corresponding to the reset line to deassert 138 - * @st_shift: status bit offset, not used for OMAP4+ 144 + * @st_shift: status bit offset corresponding to the reset line 139 145 * @part: PRM partition 140 146 * @inst: PRM instance offset 141 147 * @rstctrl_offs: reset register offset 142 - * @st_offs: reset status register offset, not used for OMAP4+ 148 + * @rstst_offs: reset status register offset 143 149 * 144 150 * Some IPs like dsp, ipu or iva contain processors that require an HW 145 151 * reset line to be asserted / deasserted in order to fully enable the ··· 151 157 * of reset, or -EBUSY if the submodule did not exit reset promptly. 152 158 */ 153 159 int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, 154 - u16 rstctrl_offs, u16 st_offs) 160 + u16 rstctrl_offs, u16 rstst_offs) 155 161 { 156 162 int c; 157 163 u32 mask = 1 << shift; 158 - u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET; 164 + u32 st_mask = 1 << st_shift; 159 165 160 166 /* Check the current status to avoid de-asserting the line twice */ 161 167 if (omap4_prminst_is_hardreset_asserted(shift, part, inst, ··· 163 169 return -EEXIST; 164 170 165 171 /* Clear the reset status by writing 1 to the status bit */ 166 - omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst, 172 + omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst, 167 173 rstst_offs); 168 174 /* de-assert the reset control line */ 169 175 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); 170 176 /* wait the status to be set */ 171 - omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst, 172 - rstst_offs), 177 + omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part, 178 + inst, rstst_offs), 173 179 MAX_MODULE_HARDRESET_WAIT, c); 174 180 175 181 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+5 -8
arch/arm/mach-omap2/timer.c
··· 298 298 if (IS_ERR(src)) 299 299 return PTR_ERR(src); 300 300 301 - if (clk_get_parent(timer->fclk) != src) { 302 - r = clk_set_parent(timer->fclk, src); 303 - if (r < 0) { 304 - pr_warn("%s: %s cannot set source\n", __func__, 305 - oh->name); 306 - clk_put(src); 307 - return r; 308 - } 301 + r = clk_set_parent(timer->fclk, src); 302 + if (r < 0) { 303 + pr_warn("%s: %s cannot set source\n", __func__, oh->name); 304 + clk_put(src); 305 + return r; 309 306 } 310 307 311 308 clk_put(src);
-26
arch/arm/mach-rockchip/pm.c
··· 44 44 static phys_addr_t rk3288_bootram_phy; 45 45 46 46 static struct regmap *pmu_regmap; 47 - static struct regmap *grf_regmap; 48 47 static struct regmap *sgrf_regmap; 49 48 50 49 static u32 rk3288_pmu_pwr_mode_con; 51 - static u32 rk3288_grf_soc_con0; 52 50 static u32 rk3288_sgrf_soc_con0; 53 51 54 52 static inline u32 rk3288_l2_config(void) ··· 70 72 { 71 73 u32 mode_set, mode_set1; 72 74 73 - regmap_read(grf_regmap, RK3288_GRF_SOC_CON0, &rk3288_grf_soc_con0); 74 - 75 75 regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); 76 76 77 77 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, 78 78 &rk3288_pmu_pwr_mode_con); 79 - 80 - /* 81 - * We need set this bit GRF_FORCE_JTAG here, for the debug module, 82 - * otherwise, it may become inaccessible after resume. 83 - * This creates a potential security issue, as the sdmmc pins may 84 - * accept jtag data for a short time during resume if no card is 85 - * inserted. 86 - * But this is of course also true for the regular boot, before we 87 - * turn of the jtag/sdmmc autodetect. 88 - */ 89 - regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, GRF_FORCE_JTAG | 90 - GRF_FORCE_JTAG_WRITE); 91 79 92 80 /* 93 81 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR ··· 135 151 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, 136 152 rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE 137 153 | SGRF_FAST_BOOT_EN_WRITE); 138 - 139 - regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, rk3288_grf_soc_con0 | 140 - GRF_FORCE_JTAG_WRITE); 141 154 } 142 155 143 156 static int rockchip_lpmode_enter(unsigned long arg) ··· 190 209 "rockchip,rk3288-sgrf"); 191 210 if (IS_ERR(sgrf_regmap)) { 192 211 pr_err("%s: could not find sgrf regmap\n", __func__); 193 - return PTR_ERR(pmu_regmap); 194 - } 195 - 196 - grf_regmap = syscon_regmap_lookup_by_compatible( 197 - "rockchip,rk3288-grf"); 198 - if (IS_ERR(grf_regmap)) { 199 - pr_err("%s: could not find grf regmap\n", __func__); 200 212 return PTR_ERR(pmu_regmap); 201 213 } 202 214
-4
arch/arm/mach-rockchip/pm.h
··· 48 48 #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 49 49 #define RK3288_PMU_PWRMODE_CON1 0x90 50 50 51 - #define RK3288_GRF_SOC_CON0 0x244 52 - #define GRF_FORCE_JTAG BIT(12) 53 - #define GRF_FORCE_JTAG_WRITE BIT(28) 54 - 55 51 #define RK3288_SGRF_SOC_CON0 (0x0000) 56 52 #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) 57 53 #define SGRF_PCLK_WDT_GATE BIT(6)
+27 -4
arch/arm64/boot/dts/arm/juno-motherboard.dtsi
··· 21 21 clock-output-names = "juno_mb:clk25mhz"; 22 22 }; 23 23 24 + v2m_refclk1mhz: refclk1mhz { 25 + compatible = "fixed-clock"; 26 + #clock-cells = <0>; 27 + clock-frequency = <1000000>; 28 + clock-output-names = "juno_mb:refclk1mhz"; 29 + }; 30 + 31 + v2m_refclk32khz: refclk32khz { 32 + compatible = "fixed-clock"; 33 + #clock-cells = <0>; 34 + clock-frequency = <32768>; 35 + clock-output-names = "juno_mb:refclk32khz"; 36 + }; 37 + 24 38 motherboard { 25 39 compatible = "arm,vexpress,v2p-p1", "simple-bus"; 26 40 #address-cells = <2>; /* SMB chipselect number and offset */ ··· 80 66 #size-cells = <1>; 81 67 ranges = <0 3 0 0x200000>; 82 68 69 + v2m_sysctl: sysctl@020000 { 70 + compatible = "arm,sp810", "arm,primecell"; 71 + reg = <0x020000 0x1000>; 72 + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; 73 + clock-names = "refclk", "timclk", "apb_pclk"; 74 + #clock-cells = <1>; 75 + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 76 + }; 77 + 83 78 mmci@050000 { 84 79 compatible = "arm,pl180", "arm,primecell"; 85 80 reg = <0x050000 0x1000>; ··· 129 106 compatible = "arm,sp804", "arm,primecell"; 130 107 reg = <0x110000 0x10000>; 131 108 interrupts = <9>; 132 - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 133 - clock-names = "timclken1", "apb_pclk"; 109 + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; 110 + clock-names = "timclken1", "timclken2", "apb_pclk"; 134 111 }; 135 112 136 113 v2m_timer23: timer@120000 { 137 114 compatible = "arm,sp804", "arm,primecell"; 138 115 reg = <0x120000 0x10000>; 139 116 interrupts = <9>; 140 - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 141 - clock-names = "timclken1", "apb_pclk"; 117 + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; 118 + clock-names = "timclken1", "timclken2", "apb_pclk"; 142 119 }; 143 120 144 121 rtc@170000 {